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Document overview
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Technical content
Features
Three DSPs and 24-bit Audio Router On-chip 32 kHz to 96 kHz Sampling Rate 16-bit Microcontroller On-chip Variety of I/Os, including SmartMedia™ and DataFlash® Embedded RAM for Single Chip Operation (530 Kbits) Warm Start Power-down 1 µA Typical Deep Power-down, 0.5 mW/MIPS Typical Operating External Flash/ROM Capability Available in a 100-lead TQFP Package Ideal for Real-time Audio Applications – Wavetable Synthesis (GM-Lite) –M P 3 D e c o d i n g – Effect Processing (Reverb, Echo, Chorus, etc.) – Filtering, Sampling Rate Conversion Typical Applications: Cellular Phones, MP3 Player, Musical Instruments, Consumer Electronic, Professional Audio
Description
The ATSAM3303 is a member of the new ATSAM3000 family that uses the DSP array technology. The ATSAM3303 includes three 24-bit DSPs, a 24-bit Audio Router and a general-purpose 16-bit on-chip CISC microcontroller. Its high performance and flexibil- ity allow implementation of professional-quality audio applications, such as MP3 decoding, Wavetable synthesis, effect processing and mixing. A variety of I/Os, includ- ing external Wave ROM, SmartMedia and DataFlash are provided. Sampling rates up to 96 kHz at 24 bits are supported. Audio Processing ATSAM3303 GM-Lite Synthesizer/ Professional Effects DSP
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Figure 1. ATSAM3303 DSP Array Block Diagram DSP Array The ATSAM3303 includes three on-chip DSPs. Bus. It can request external data such as compressed audio through the Async Bus. Each P24 RAM can be accessed through the Async Bus. cache, pitch control, second-order filter and two envelope generators. kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles.
6091A–DRMSD–07/04 allowing inter P24 communication at the current sampling rate. Slots 0 to 7 are reserved for a specific router DSP, which also handles audio out, audio in, and remix send. Async Bus The Async Bus is 24-bit data inside the chip and 16-bit outside. The P16 processor normally masters the Async Bus, it can read/write the P24 memories and the external or embedded ROM/RAM. However, each P24 can request a bus mas- ter cycle for accessing external ROM/RAM or other P24 memories. This allows efficient intercommunication between several P24s on asynchronous block basis. Specific P24 instructions FLOAT and FIX allow to convert fixed point DSP data to floating point 16 bits. This allows for 20-bit audio dynamic range when using 16-bit external memory. 16-bit Processor The P16 processor is widely used in ATSAM products. Using the P16 allows to keep the large firmware investments from the SAM97xx series. A built-in ROM, connected to the P16, holds basic input/output software (BIOS) for peripherals such as UART, DataFlash ® , SmartMedia® , MPU, as well as a debugger using a dedicated asynchro- nous serial line. The firmware can reside on external parallel ROM/Flash or it can be downloaded at power-up into the built-in 16K x 24 RAM from serial EEPROM, DataFlash, SmartMedia or host. MMU (Memory Management Unit) The MMU handles transfer requests between the external or embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3303 includes an on-chip 16K x 24 RAM. Router: Final ACC, MIX, Audio Out, Audio In This block includes a RAM, accessed through the Async Bus, which defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send). It takes care of mix and accumulation from Sync Bus samples. Eight channels of audio in and eight channels of audio out are provided (4 stereo in/out, I2S format). The stereo audio in channels may have a different sampling rate than the audio out channels. In this case, one or more P24s take care of sampling rate conversion. I/O The ATSAM3303 includes versatile I/Os that share common pins for reduced pin count and small IC footprint. Most I/Os, when not used for a specific function, remain available as firmware controlled general-purpose pins. The following peripherals are included on-chip: 2 x 8-bit timers 2 x 16-bit timers Parallel slave 8-bit port, MPU401 compatible Parallel master 8-bit port, for connection to SmartMedia and/or LCD display, switches, etc. 2 x asynchronous bi-directional serial ports Synchronous serial slave port (SPI type host connection) SPI master bi-directional port for EEPROM or DataFlash connection Firmware controlled I/O pins
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Figure 2. Host-controlled MP3 or Cost-optimized GM-Lite Wavetable Player (Cellular Figure 3. Ultra Low-cost Musical Keyboard
DSP Considerations The ATSAM3303 includes three P24 DSPs. Table 1 lists the performance levels achievable by the P24. able synthesis or many I/O pins are required. of operation are host controlled and stand-alone. SmartMedia reserved sectors starting at sector 1. Table 1. P24 Performance Levels
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Pin Description Identical sharing number indicates multifunction pins. Pd indicates a pin with built-in pull-down resistor. Pu indicates a pin with built-in pull-up resistor. Table 2. Pinout by Pin Name PWROUT if the built-in power switch is used. VC33 13, 50, 83 PWR - Periphery power. All these pins should be returned to nominal 3.3V.
100 In 3 Slave 8-bit interface chip select, active low
firmware will wait for SmartMedia SMPD.
firmware to know the operating freq of the chip (see FS1). corresponding CLAD3 - 0 is not used. DAAD3 - 0 if the corresponding WSAD3 - 0 is not used. the DAC/Codec sampling rate. or CLAD0 external rate when sampling rate conversion is requested. when sampling rate conversion is requested. DAAD3 - 1 have built-in pull-downs. They may be left open if not used. becomes an active low output.
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43 Out 13 SmartMedia write enable (WE ), active low
RAM/Flash/ROM at address 200:0000H.
49 Out 21 External memory write enable, active low
down. It may be left open if not used.
firmware download from an external SmartMedia, DataFlash or host. should be grounded or left open for normal operation. are available which allow warm restart of the chip.
- Test input. Should be grounded or left open.
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Table 3. ATSAM3303 Pinout by Pin Number
Figure 4. Thin Plastic 100-lead Quad Flat Pack (TQFP100B) Table 4. Package Dimensions in mm
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6091A–DRMSD–07/04
Electrical Characteristics
Absolute Maximum Ratings(*) Recommended Operating Conditions Note: 1. Operation at lower VC33 values down to VC18 is possible, however external timing may be impaired. Please contact Atmel if you plan to use these circuits with VC33 outside the recommended operating range. Maximum Ratings" may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on any pin C18 + 0.3V Table 5. Recommended Operating Conditions
Table 6. DC Characteristics (TA = 25°C, VC18 = 1.8V ± 10%, VC33 = 3.3V ± 10%)
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Pins used: D7-D0 (I/O), CS (input), A0 (input), WR (input), RD (input), IRQ (output). This interface is typically used to connect the chip to a host processor. Figure 5. Host Interface Read Cycle Figure 6. Host Interface Write Cycle Table 7. Timing Parameters
Status register is read when A0 = 1, RD = 0, CS = 0. If 0, data from ATSAM3303 to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ. If 0, then ATSAM3303 is ready to accept DATA from host. Note: If status bit RF is not checked by host, write cycle time should not be lower than 3 µs. peripherals such as LCD screens. This is a master synchronous serial interface, operating in SPI mode 0. Please refer to Atmel DataFlash datasheets for accurate SPI mode 0 timing. Figure 7. Typical DataFlash Interface Timing
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this interface. Therefore an external ROM/Flash/EEPROM is required. SCLK, therefore the host should change SDIN on the negative SCLK edge. SCLK low, indicates that SDIN will hold MSB data on the next rising SCLK. The data is stored internally in a 256-byte FIFO. sor to send data in burst mode. The maximum SCLK frequency is fck (fck being the crystal frequency). The minimum time between two bytes is 64 fck periods. The contents of the SDIN data are defined by the firmware. Figure 8. Serial Slave Interface Typical Timing
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Figure 11. Digital Audio Frame Format, 192 x Fs and 384 x Fs Modes
of 4M words (total = 16 Mbytes). Figure 12. ROM/Flash Read Cycle PLL. pLCK = tCK /4. T ypical value with crystal 12.288 MHz is pLCK = 20 ns.
- Memory access time should be lower than tACE min. Typical value with crystal 12.288 MHz is 90 ns.
Table 10. External Memory Parameters
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Figure 13. External RAM/Flash Write Timing Table 11. External Flash Timing Parameters
6091A–DRMSD–07/04 Reset and Power- down During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which takes max. 10ms. After the low-to-high transition of RESET, the following occurs: All P24s enter an idle state. P16 program execution starts in built-in ROM. The power-up sequence is as follows: STIN is sensed. If HIGH, then the built-in debugger is started. Addresses 0 & 1 from external ROM are checked. If “DR” is read, then control is transferred to address 400H from external ROM. S M C is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect (SMPD). When detected, the firmware is downloaded from SmartMedia reserved sector 1 and started. An attempt is done to read the first two bytes of an external EEPROM or DataFlash. If “DR” is read, then the built-in loader loads the firmware from the external EEPROM/DataFlash and starts it. Firmware download from a host processor is assumed. 1. The byte 0ACh is written to the host, this rises IRQ. The host can recognize that the chip is ready to accept program download. Higher speed transfer can be reach by polling the parallel interface status (CS 2. The host sends the firmware size (in words) on two bytes (Low byte first). 3. The host sends the ATSAM3303 firmware. The firmware should begin with string “DR”. 4. The byte 0ACh is written to the host, this rises IRQ. The host recognizes that the chip has accepted the firmware. 5. ATSAM3303 starts the firmware. If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power switch is used, then the chip enters a deep power-down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied. Other power reduction features allowing warm restart are controlled by firmware: P24s can be individually stopped. The clock frequency can be internally divided by 256.
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6091A–DRMSD–07/04 Recommended Board Layout Like all HCMOS high integration ICs, the following simple rules of board layout are man- datory for reliable operation: GND, VC33, VC18 Distribution and Decouplings All GND, VC33, VC18 pins should be connected. A GND plane is strongly recom- mended. The board GND + VC33 distribution should be in grid form. Recommended VC18 decoupling is 0.1 µF at each corner of the IC with an additional 10 µF decoupling close to the crystal. VC33 requires a single 0.1µF decoupling. Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C- R and the ATSAM3033 should be short and shielded. The ground return from the com- pensation capacitors and LFT filter should be the GND plane from ATSAM3033. Buses Parallel layout between D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The D0 - D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0 - WA21/WD0 - WD15 that can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D7 bus, which is connected to the host and to the ATSAM3033 GND. A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus, which is connected to the ROM/Flash grounds and to the ATSAM3033. Analog Section A specific AGND ground plane should be provided, which is connected to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the ana- log section.
Figure 14. Recommended Crystal Compensation and LFT Filter
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6091A–DRMSD–07/04 Product Development and Debugging Atmel provides an integrated product development and debugging tool SamVS. SamVS runs under Windows (98, ME, 2000, XP). Within the environment, it is possible to: E d i t A s s e m b l e Debug on real target (In-circuit Emulation) Program Flash, Dataflash, EEPROM, SmartMedia on target. Two dedicated IC pins, STIN and STOUT allow running firmware directly into the target using standard PC COM port communication at 57.6 Kbauds. Thus time-to-market is optimized by testing directly on the final prototype. A library of frequently used functions is available, such as: Wavetable synthesis Reverb/Chorus M P 3 d e c o d e 31-band equalizer Parametric equalizer Atmel engineers are available to study customer-specific applications.
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www.atmel.com/literature 6091A–DRMSD–07/04 © Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof, Dream® and DataFlash® are the registered trademarks of Atmel Corporation or its subsidiaries. SmartMedia™ is the trademark of SanDisk Corp. MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson Multimedia. Other terms and product names may be the trademarks of others.