Download PDFATR0601 ATMEL
Document overview
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Technical content
Features
- Very Low Power Design (40 mW) Single IF Architecture Excellent Noise Performance 1.5-bit ADC On Chip Small QFN Package (4 mm × 4 mm, 24 pins) Highly integrated, Few External Components Advanced BiCMOS Technology (UHF6s) Non ESD Sensitive Device 1. Description The ATR0601 is a single IF GPS front-end IC, designed to meet the requirements of mobile and automotive applications. Excellent RF performance combined with low noise figure enables high quality GPS solutions and it's very low power consumption fits perfectly to portable devices. Featuring a balanced XTO and a fully integrated bal- anced frequency synthesizer, only few external components are required. The ATR0601 offers a complete autonomous mode, utilizing t he on chip AGC in closed loop operation, to set the gain of the IF VGA. Alternatively, in combination with the baseband processor ATR0621 the optimum gain of the IF VGA can be computed and set by software, using the digital SDI interface. Figure 1-1. Block Diagram XTO PMSS Logic D A VCO PLL D A BPI TEST MO GND NBPI BP NBP VCC VCC VDIG PUXTO PURF RF NRF XTO NXTO X NX SDI SL SH SC AGCO EGC GPS Front-end IC ATR0601 Preliminary Rev. 4866A–GPS–08/05
4866A–GPS–08/05 ATR0601 [Preliminary] 2. Pin Configuration Figure 2-1. Pinning QFN24 7 8 9 10 11 12 24 23 22 21 20 19 Paddle GND VDIG AGCO NXTO NX X XTO PURF PUXTO NBPI BPI NBP BP VCC MO TEST NRF RF NC SC SH SL SDI EGC VCC Table 2-1. Pin Description Pin Symbol Type (1) Function Paddle GND S Common ground
1 VDIG S Digital supply
2 AGCO A_I/O AGC: gain control voltage output/corner frequency determination
3 NXTO A_I XTO interface (optional: TCXO input)
4 NX A_O XTO interface
5 X A_O XTO interface
6 XTO A_I XTO interface (optional: TCXO input)
7 VCC S Analog supply
8 MO A_O Testbuffer output (f
IF)
9 TEST A_I Enable testbuffer
10 NRF A_I RF input complementary
11 RF A_I RF input
12 NC – Not connected
13 BP A_O IF-Filter interface (mixer output, open collector)
14 NBP A_O IF-Filter interface (mixer output complementary, open collector)
15 BPI A_I IF-Filter interface (IF-input)
16 NBPI A_I IF-Filter interface (IF-input complementary)
17 PUXTO D_I Power-up XTO
18 PURF D_I Power-up RF
19 VCC S Analog supply
20 EGC D_I Enable external gain control (high = external; low = internal)
21 SDI D_I Input for external gain control signal ( Σ∆ modulation)
22 SL D_O Data output: “low”
23 SH D_O Data output: “high”
24 SC D_O Sample clock
Note: 1. Type: A_I Analog input, A_O Analog output, D_I Digital input, D_O Digital output, S Supply
4866A–GPS–08/05 ATR0601 [Preliminary] 3. Functional Description
3.1 General Description
The ATR0601 GPS receiver IC has been especia lly designed for GPS applications in both mobile phone and automotive applications. From this system point of vi ew, it incorporates high- est isolation between GPS and cellular bands, as well as very low power consumption. The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a centre fre- quency of: fRF = 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a chip rate of 1.023 Mbps. As the input signal power at the antenna is approximately –140 dBm, the desired signal is below the thermal noise floor.
3.2 PMSS Logic
The Power Management, Startup and Shutdown Logic ensures reliable operation within the rec- ommended operating conditions. The external power control signals PUrf and PUxto are passed thru Schmitt-trigger inputs to eliminate voltage ripple and prevent undesired behaviour during startup and shutdown. Digital and analog supply vo ltages are analyzed by a monitoring circuit, enabling the startup of the IC only within a secure operating area.
3.3 XTO
The XTO is designed for minimum phase noise and frequency perturbations. The balanced topology gives maximum isolation from ext ernal and ground coupled noise. The built-in jump start circuitry ensures reliable start-up behaviour of any specified crystal. For use with an exter- nal TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer. The recommended reference frequency is: fXTO = 23.104 MHz.
3.4 VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no external components are required. The VCO co mbines very good phase noise behaviour and excellent spurious suppression. The relation between the reference frequency (f XTO) and the VCO centre frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
3.5 RF-Mixer/Image-filter
Combined with the antenna an external LNA provides a first band path filtering of the signal. For the LNA, Atmel’s ATR0610 is recommended, due to it’s low Noise Figure, high linearity an low power consumption. The output of the LNA drives an SAW filter, which provides image rejection for the mixer and the required isolation of all GSM bands. The output of the SAW filter is fed into a highly linear mixer with high conversion gain and excellent noise performance. The IF frequency (fIF) is given by: fIF = fRF – fVCO = 1575.42 MHz – 1478.656 MHz = 96.764 MHz.
3.6 IF-filter
The mixer directly drives an external LC-Bandpat h filter via open collector outputs. In order to provide highest selectivity and conversion gain, it is recommended to design the external filter, according to the application proposal, as a 2-pole filter with a quality factor Q > 25.
4866A–GPS–08/05 ATR0601 [Preliminary]
3.7 VGA/AGC
The output of the IF-Filter drives an on-chip Variabl e Gain Amplifier (VGA) which is combined with additional low-pass filtering. The on-chip Automatic Gain Control (AGC) stage sets the gain of the VGA in order to optimally charge the input of the following analog-to-digital converter. The AGC control loop can be selected for on-chip closed loop operation or for external gain control mode. For external gain control mode, the loop needs to be closed by the baseband IC ATR0621.
3.8 A/D Converter
The analog-to-digital converter stage has a total resolution of 1.5 bit. It comprises balanced com- parators and a sub sampling unit, cloc ked by the reference frequency (f XTO). The frequency spectrum of the digital output signal (fOUT), present at the data outputs SL and SH, is then given by: fOUT = ⏐ fIF – fXTO × n⏐ . The selected sub sampling factor (n = 4) leads to the designated digital output signal, with a centre frequency given by: fOUT = fIF – fXTO × 4 = 96.764 MHz – 23.104 MHz – 4 = 4.348 MHz.
3.9 Clock and Data Driver
CMOS output drivers are providin g sign and magnitude bits as well as the system clock to the baseband IC ATR0621. The rail-to-rail output signal level is determined by the digital supply volt- age (VDIG).
4866A–GPS–08/05 ATR0601 [Preliminary] 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Analog supply voltage V CC –0.3 to +3.7 V Digital supply voltage V DIG –0.3 to +3.7 V Input voltage V in –0.3 to +3.7 V Operating temperature T op –40 to +85 °C Storage temperature T stg –55 to +125 °C 5. Thermal Resistance Parameters Symbol Value Unit Junction ambient R th 125 K/W 6. Operating Range Parameters Symbol Value Unit Analog supply voltage V CC 2.70 to 3.30 V Digital supply voltage V DIG 1.65 to 2.00 V Supply voltage difference (V∆ = VCC – VDIG)V ∆ ≥ 0.80 V Temperature range Temp –40 to +85 °C Input frequency f RF 1575.42 MHz Reference frequency f XTO 23.104 MHz 7. Electrical Characteristics No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
1 Common
1.1 Analog supply current (1) VPUxto = VPUrf = VPU,on 7, 19 I S 14.2 mA A
1.2 Digital supply current (1),(2) VPUxto = VPUrf = VPU,on 1I DIG 700 µA A
1.3 Analog supply current in
XTO mode(1) VPUxto = VPU,on, VPUrf = VPU,off 7, 19 I S_XTO 2.9 mA A
1.4 Digital supply current in
XTO mode(1),(3) VPUxto = VPU,on, VPUrf = VPU,off 1I DIG_XTO 500 µA A
1.5 Supply current in power
down mode(1) VPUxto = VPUrf = VPU,off 1, 7, 19 I PD 2µ A A 1.6 Maximum total gain V AGCO = 2.2V G max_tot 90 dB B 1.7 Noise figure (SSB) NF tot 6.8 dB C *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Conditions: V CC = 2.7V; VDIG = 1.65V; Temperature = 27°C 2. Capacitive load (C L = 3.3 pF) at pins 22, 23, 24 3. Capacitive load (C L = 3.3 pF) at pin 24
4866A–GPS–08/05 ATR0601 [Preliminary] 2M i x e r 2.1 Output frequency f XTO = 23.104 MHz 13, 14 f IF 96.764 MHz A
2.2 Input impedance
(balanced) fRF = 1575.42 MHz 10, 11 Z 11 10-j80 Ω C
2.3 Conversion Gain Recommended IF-filter 8 G MIX 20 dB B
2.4 Noise figure (SSB) 8 NF MIX 5.8 dB C
3 VGA/AGC
3.1 Minimum gain V AGCO = 1.0V G VGA,min 0d B B 3.2 Maximum gain V AGCO = 2.2V G VGA,max 70 dB B
3.3 Control-voltage sensitivity
VAGCO = 2.2V N VGA,min 6.6 dB/V D VAGCO = 1.0V N VGA,max 150 dB/V D
3.4 AGC cut-off frequency C ext = open 2 f 3dB_AGC 250 kHz D
3.5 AGC cut-off frequency C ext = 100 pF 2 f 3dB_AGC 33 kHz D
3.6 Gain-control output
voltage 2V AGCO 0.9 2.3 V B
4 Reference Oscillator
4.1 XTO phase noise at
100 Hz With specified crystal 24 Pn 100 –80 dBc/Hz C
4.2 XTO phase noise at 1 kHz With specified crystal 24 Pn 1k –100 dBc/Hz C
5 Clock and Data Driver
5.1 Clock driver frequency f XTO = 23.104 MHz 24 f CLK 23.104 MHz A 5.2 Clock output level C load,max = 10 pF 24 V CLK,high 0.9 × VDIG VB 5.3 Clock output level C load.max = 10 pF 24 V CLK,low 0.1 × VDIG VB 5.4 Data output level C load,max = 10 pF 22, 23 V Data,high 0.9 × VDIG VB 5.5 Data output level C load,max = 10 pF 22, 23 V Data,low 0.1 × VDIG VB 6P M S S 6.1 Voltage level power-on 17, 18 V PU,on 1.3 V A 6.2 Voltage level power-off 17, 18 V PU,off 0.5 V A 7. Electrical Characteristics (Continued) No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Conditions: V CC = 2.7V; VDIG = 1.65V; Temperature = 27°C 2. Capacitive load (C L = 3.3 pF) at pins 22, 23, 24 3. Capacitive load (C L = 3.3 pF) at pin 24
4866A–GPS–08/05 ATR0601 [Preliminary] 10. Demonstration Board Figure 10-1. Schematic of Demonstration Board PUXTO J9J8 12 312 3 AGCO EGC C6C5 L5 L6 C22 C3 C10 C19 C8 C9 P2 FI1 VDD1.8 VDD1.8 VDD1.8 TEST SH SDI NXTO NX PURFXX T O BPI MO 816 NBPI NRF C15 RF 651 7 18 NC 1243 19 1 7 VCC VCC VCC VCC VDIG OUT NOUT C21 C17 BP NBP FB1 FB2 J6SL J4SC 24 1 IN NIN
4866A–GPS–08/05 ATR0601 [Preliminary] Figure 10-2. Illustration of Demonstration Board Table 10-1. BOM of Demonstration Board Qty Value Device Parts Tolerance Manufacturer Mfr. Order Code
4 JP2E J3, J4, J5, J6 Molex 90120-0762
5 JP3E J1, J2, J7, J8, J9 Molex 90120-0763
1 0 RESISTOR-0402 R1 Vishay CRCW0402000Z 1 2n2 CAPACITOR-0402 C3 5% Vishay VJ0402Y222JXJA 2 1p3 CAPACITOR-0402 C15, C17 0,1 pF Tayo Yuden EVK105CH1R3BW 1 5n6 2% Multilayer INDUCTOR-0402 L2 2% Würth Elektronik 744784056G 2 5p0 ±0p1 CAPACITOR-0402 C21, C22 ± 0p1 Y ageo America 0402CG509C9B200 2 10µ ELKO-B C1, C2 20% Vishay 293D106X0016B2 1 27 RESISTOR-0402 R7 5% Vishay CRCW040227RJ 2 47p CAPACITOR-0402 C5, C6 5% Vishay VJ0402A470JXXA. 1 82p CAPACITOR-0402 C4 Vishay VJ0402A820JXXA 4 100n CAPACITOR-0402 C7, C8, C9, C19 5% Vishay VJ0402V104JXJ 1 100p CAPACITOR-0402 C10 5% Vishay VJ0402A101JXXA. 3 142-0711-841 COAX-SMA P1, P2, P4 Johnson Comp. 142-0711-841 4 220n 2% INDUCTOR_WIRE- WOUND-0603 L3, L4, L5, L6 2% Würth Elektronik 744761222G 2 74279266 FERRITE_BEAD-0603 FB1, FB2 Würth Elektronik 74279266
1 ATR0601-1 ATR0601-1 IC1 Atmel ATR0601
1 B4060 FILTER-BALANCED FI1 Epcos B4060
1 RSX-5
23.104 MHz XTAL-4PIN-6035 X1 Rakon XZC736 IEC19RSX-5
23.104 MHz
4866A–GPS–08/05 ATR0601 [Preliminary] 11. Recommended Footprint Figure 11-1. Recommended Footprint (QFN24 - 4 mm × 4 mm)
4866A–GPS–08/05 ATR0601 [Preliminary] 13. Package Information 12. Ordering Information Extended Type Number Package Remarks ATR0601-PFQW QFN24, 4 × 4 Taped and reeled Package: QFN 24 - 4 x 4 Exposed pad 2.6 x 2.6 (acc. JEDEC OUTLINE No. MO - 220) Dimensions in mm specifications according to DIN technical drawing s 0.25 0.4 0.9±0.1 0.05-0.05 0.5 nom. 712 2419 Not indicated tolerances ±0.05 Issue: 1; 03.06.05 Drawing-No.: 6.543-5101.02-4 2.6 2.5
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