Download PDFATF16V8B_1 ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 16
Technical content
Features
- Industry Standard Architecture Emulates Many 20-Pin PALs® Low Cost Easy-to-Use Software Tools
- High Speed Electrically Erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-Pin Delay
- Several Power Saving Options Device I CC , Stand-By I CC , Active ATF16V8B 50 mA 55 mA ATF16V8BQ 35 mA 40 mA ATF16V8BQL 5 mA 20 mA
- CMOS and TTL Compatible Inputs and Outputs Input and I/O Pull-Up Resistors
- Advanced Flash Technology Reprogrammable 100% Tested
- High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection 200 mA Latchup Immunity
- Commercial, and Industrial Temperature Ranges
- Dual-in-Line and Surface Mount Packages in Standard Pinouts Block Diagram 0364C ATF16V8B 1-7
(1) Programming Voltage with (1) *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Case) 0°C - 70°C -40°C - 85°C VCC Power Supply 5V ± 5% 5V ± 10% Several low power options allow selection of the best so- lution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. Description (Continued) The ATF16V8Bs incorporate a superset of the generic ar- chitectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with soft- ware, allow highly complex logic functions to be realized. 1-8 ATF16V8B
Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL (MAX) -35 -100 µA IIH Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC 10 µA ICC Power Supply Current, Standby VCC = MAX, VIN = MAX, Outputs Open B-7, -10 Com. 55 85 mA Ind. 55 95 mA B-15, -25 Com. 50 75 mA Ind. 50 80 mA BQ-10 Com. 35 55 mA BQL-15, -25 Com. 5 10 mA Ind. 5 15 mA ICC2 Clocked Power Supply Current VCC = MAX, Outputs Open BQL-15, -25 Com. 1 mA/MHz (2) Ind. 1 mA/MHz (2) ICC3 Clocked Power Supply Current VCC = MAX, Outputs Open, f = 15 MHz B-7, -10 Com. 60 90 mA Ind. 60 100 mA B-15, -25 Com. 55 85 mA Ind. 55 95 mA BQ-10 Com. 40 55 mA BQL-15, -25 Com. 20 35 mA Ind. 20 40 mA IOS (1) Output Short Circuit Current VOUT = 0.5V -130 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output High Voltage VIN = VIH or VIL, VCC = MIN IOL = -24 mA Com., Ind. 0.5 V VOH Output High Voltage VIN = VIH or VIL, VCC = MIN IOH = -4.0 mA 2.4 V Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. Low frequency only. See Supply Current versus Input Frequency curves. ATF16V8B 1-9
AC Characteristics (1) Symbol Parameter -7 (2) -10 -15 -25 Min Max Min Max Min Max Min Max Units tPD Input or Feedback to Non-Registered Output 8 outputs switching 3 7 . 5 31 0 31 5 32 5 n s 1 output switching 7n s tCF Clock to Feedback 3 6 8 10 ns tCO C l o c k t o O u t p u t 25272 1 02 1 2 n s tS Input or Feedback Setup Time 5 7.5 12 15 ns tH H o l d T i m e 0000 n s tP C l o c k P e r i o d 81 21 62 4 n s tW Clock Width 4 6 8 12 ns FMAX External Feedback 1/(tS+tCO ) 100 68 45 37 MHz Internal Feedback 1/(tS + tCF ) 125 74 50 40 MHz No Feedback 1/(tP) 125 83 62 41 MHz tEA Input to Output Enable — Product Term 3 9 3 10 3 15 3 20 ns tER Input to Output Disable — Product Term 2 9 2 10 2 15 2 20 ns tPZX OE pin to Output Enable 2 6 2 10 2 15 2 20 ns tPXZ OE pin to Output Disable 1.5 6 1.5 10 1.5 15 1.5 20 ns Notes: 1. See ordering information for valid part numbers and speed grades. 2. Recommend ATF16V8C-7. AC Waveforms (1) 1-10 ATF16V8B
Preload of Registered Outputs The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Power Up Reset The registers in the ATF16V8Bs are designed to reset dur- ing power up. At a point delayed slightly from V CC cross- ing VRST , all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the un- certainty of how V CC actually rises in the system, the fol- lowing conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3) The clock must remain stable during tPR . Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units Conditions C IN 58 p F V IN = 0V C OUT 68 p F V OUT = 0V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Parameter Description Typ Max Units tPR Power-Up Reset Time 600 1,000 ns VRST Power-Up Reset Voltage 3.8 4.5 V Input Test Waveforms and Measurement Levels: tR , tF < 5 ns (10% to 90%) Commercial Output Test Loads: ATF16V8B 1-11
Functional Logic Diagram Description The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF16V8B can be configured in one of three different modes. Each mode makes the ATF16V8B look like a dif- ferent device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The de- termining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus out- puts with output enable control. The ATF16V8B universal architecture can be pro- grammed to emulate many 20-pin PAL devices. These architectural subsets can be found in each of the configu- ration modes described in the following pages. The user can download the listed subset device JEDEC program- ming file to the PLD programmer, and the ATF16V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the Security Fuse. Compiler Mode Selection Registered Complex Simple Auto Select ABEL, Atmel-ABEL P16V8R P16V8C P16V8AS P16V8 CUPL G16V8MS G16V8MA G16V8AS G16V8A LOG/iC GAL16V8_R (1) GAL16V8_C7 (1) GAL16V8_C8 (1) GAL16V8 OrCAD-PLD “Registered” “Complex” “Simple” GAL16V8A PLDesigner P16V8R P16V8C P16V8C P16V8A Tango-PLD G16V8R G16V8C G16V8AS G16V8 Note: 1. Only applicable for version 3.4 or lower. Input and I/O Pull-Ups All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V CC . This en- sures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below). Input Diagram I/O Diagram Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/program- ming. Electronic Signature Word There are 64 bits of programmable memory that are al- ways available to the user, even if the device is secured. These bits can be used for user-specific data. 1-12 ATF16V8B
Software compilers support the three different OMC modes as different device types. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) us- age. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the soft- ware to choose the complex mode. The software will choose the simple mode only when all outputs are dedi- cated combinatorial without OE control. The different de- vice types can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently con- figured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the reg- istered mode. In complex mode pin 1 and pin 11 become dedicated in- puts and use the feedback paths of pin 19 and pin 12 re- spectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins (pins 15 and 16) will not have the feedback op- tion as these pins are always configured as dedicated combinatorial output. ATF16V8B Registered Mode PAL Device Emulation / PAL Replacement The registered mode is used if one or more registers are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combi- natorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 16R8 16RP8 16R6 16RP6 16R4 16RP4 Registered Configuration for Registered Mode (1, 2) Notes: 1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically. Combinatorial Configuration for Registered Mode (1, 2) Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically. ATF16V8B 1-13
Registered Mode Logic Diagram 1-14 ATF16V8B
PAL Device Emulation/PAL Replacement In the Complex Mode, combinatorial output and I/O func- tions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 16L8 16H8 16P8 Complex Mode Option ATF16V8B Simple Mode PAL Device Emulation / PAL Replacement In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are perma- nently configured as combinatorial outputs. Other macro- cells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular in- puts. The compiler selects this mode when all outputs are com- binatorial without OE control. The following simple PALs can be emulated using this mode: 10L8 10H8 10P8 12L6 12H6 12P6 14L4 14H4 14P4 16L2 16H2 16P2 Simple Mode Option ATF16V8B 1-15
Complex Mode Logic Diagram 1-16 ATF16V8B
Note: 1. All normalized values referenced to maximum specification in AC Characteristics in the data sheet. ATF16V8B 1-19
Ordering Information
(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 7.5 5 5 ATF16V8B-7JC (1) 20J Commercial ATF16V8B-7PC (1) 20P3 (0 °C to 70°C) ATF16V8B-7SC (1) 20S 10 7.5 7 ATF16V8B-10JC 20J Commercial ATF16V8B-10PC 20P3 (0 °C to 70°C) ATF16V8B-10SC 20S ATF16V8B-10JI 20J Industrial ATF16V8B-10PI 20P3 (-40 °C to 85°C) ATF16V8B-10SI 20S 15 12 10 ATF16V8B-15JC 20J Commercial ATF16V8B-15PC 20P3 (0 °C to 70°C) ATF16V8B-15SC 20S ATF16V8B-15JI 20J Industrial ATF16V8B-15PI 20P3 (-40 °C to 85°C) ATF16V8B-15SI 20S 25 15 12 ATF16V8B-25JC 20J Commercial ATF16V8B-25PC 20P3 (0 °C to 70°C) ATF16V8B-25SC 20S ATF16V8B-25JI 20J Industrial ATF16V8B-25PI 20P3 (-40 °C to 85°C) ATF16V8B-25SI 20S Note: 1. Recommend ATF16V8C-7. ATF16V8B 1-21
(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 10 7.5 7 ATF16V8BQ-10JC 20J Commercial ATF16V8BQ-10PC 20P3 (0 °C to 70°C) ATF16V8BQ-10SC 20S 15 12 10 ATF16V8BQL-15JC 20J Commercial ATF16V8BQL-15PC 20P3 (0 °C to 70°C) ATF16V8BQL-15SC 20S 25 15 12 ATF16V8BQL-25JC 20J Commercial ATF16V8BQL-25PC 20P3 (0 °C to 70°C) ATF16V8BQL-25SC 20S ATF16V8BQL-25JI 20J Industrial ATF16V8BQL-25PI 20P3 (-40 °C to 85°C) ATF16V8BQL-25SI 20S Package Type 20J 20 Lead, Plastic J-Leaded Chip Carrier (PLCC) 20P3 20 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 1-22 ATF16V8B