ATF-521P8 ETC1

Document overview

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Technical content

Features

  • Single voltage operation
  • High linearity and P1dB
  • Low noise figure
  • Excellent uniformity in product specifications
  • Small package size: 2.0 x 2.0 x 0.75 mm3
  • Point MTTF > 300 years[2]
  • MSL-1 and lead-free
  • Tape-and-reel packaging option available Specifications 2 GHz; 4.5V, 200 mA (Typ.)
  • 42 dBm output IP3
  • 26.5 dBm output power at 1 dB gain compression
  • 1.5 dB noise figure
  • 17 dB Gain
  • 12.5 dB LFOM [4]

Applications

  • Front-end LNA Q2 and Q3, driver or pre-driver amplifier for Cellular/ PCS and WCDMA wireless infrastructure
  • Driver amplifier for WLAN, WLL/RLL and MMDS applications
  • General purpose discrete E-pHEMT for other high linearity applications Pin Connections and Package MarkingNote: Package marking provides orientation and identification “2P” = Device Code “x” = Month code indicates the month of manufacture. Note: 1. Enhancement mode technology employs a single positive V gs, eliminating the need of negative gate voltage associated with conventional depletion mode devices. 2. Refer to reliability datasheet for detailed MTTF data 3. Conform to JEDEC reference outline MO229 for DRP-N 4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power. Pin 1 (Source) Pin 2 (Gate) Pin 3 Pin 4 (Source) Pin 8 Pin 7 (Drain) Pin 6 Pin 5 2Px Top View Pin 8 Source (Thermal/RF Gnd) Pin 7 (Drain) Pin 6 Pin 5 Pin 1 (Source) Pin 2 (Gate) Pin 3 Pin 4 (Source) Bottom View

TA = 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise specified. Symbol Parameter and T est Condition Units Min. Typ. Max.

  1. Measurements obtained using production test board described in Figure 6.

50 Ohm

Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.

Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.

110 Ohm

15 Ohm

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 40. MSG/MAG and |S21|2 vs.

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 41. MSG/MAG and |S21|2 vs.

Figure 42. MSG/MAG and |S21|2 vs.

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead.

Figure 43. MSG/MAG and |S21|2 vs.

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead.

Figure 44. MSG/MAG and |S21|2 vs.

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead.

Description

Agilent’s ATF-521P8 is an enhancement mode PHEMT designed for high linearity and medium power applications. With an OIP3 of 42 dBm and a 1dB compression point of 26 dBm, ATF-521P8 is well suited as a base station transmit driver or a first or second stage LNA in a receive chain. Whether the design is for a W-CDMA, CDMA, or GSM basestation, this device delivers good linearity in the form of OIP3 or ACLR, which is required for standards with high peak to average ratios. Application Guidelines The ATF-521P8 device operates as a normal FET requiring input and output matching as well as DC biasing. Unlike a depletion mode transistor, this enhance- ment mode device only requires a single positive power supply, which means a positive voltage is placed on the drain and gate in order for the transistor to turn on. This application note walks through the RF and DC design employed in a single FET ampli- fier. Included in this description is an active feedback scheme to accomplish this DC biasing. RF Input & Output Matching In order to achieve maximum linearity, the appropriate input s) and output (ΓL) impedances must be presented to the device. Correctly matching from these impedances to 50Ωs will result in maximum linearity. Although ATF-521P8 may be used in other impedance systems, data col- lected for this data sheet is all referenced to a 50Ω system. The input load pull parameter at

2 GHz is shown in Figure 1 along

with the optimum S11 conjugate match. 16 dB 5 dB9 dB 3 dBS11* Return Loss ΓS Figure 1. Input Match for ATF-521P8 at 2 GHz. device becomes much simpler. Figure 2. Output Match at 2 GHz. Figure 3. High Pass Circuit T opology. Figure 4. High Pass Frequency Response.

range of temperature variations. biasing resistors for Figure 9. Figure 9. Active Bias Circuit.

Figure 10. This layout provides Section 9 of the data sheet. Figure 10. Microstripline Layout. Figure 11. LPCC Package for ATF-521P8. tance from the source to ground. connected to the device source. signal becomes very nonlinear. Figure 13. ATF-521P8 Matching. Figure 12. ATF-521P8 demoboard.

Table 1. Resistors for Active Bias.

2.14 GHz Tx driver amplifier is

added as a low frequency bypass.

2140 MHz

Figure 15. Gain and Noise Figure vs. Frequency.

2170 MHz for the WCDMA

Figure 16. Input and Output Return Loss vs.

3.84 MHz, it is difficult to corre-

lated good OIP3 to good ACLR. presented to avoid ambiguity. Figure 14. 2140 MHz Schematic.

T able 4. Thermal resistance measurements. Figure 20. Derating for ATF- 521P8.

  • Maximize vias underneath and around package;
  • Maximize exposed surface metal;
  • Use 1 oz or greater copper clad;
  • Minimize board thickness;
  • Metal heat sinks or extrusions;
  • Fans or forced air;
  • Mount PCB to Chassis. Summary A high linearity Tx driver amplifier for WCDMA has been presented and designed using Agilent’s ATF-521P8. This includes RF, DC and good ther- mal dissipation practices for reliable lifetime operation. A summary of the typical perfor- mance for ATF-521P8 demoboard at 2140 MHz is as follows: Demo Board Results at 2140 MHz Gain 16.5 dB OIP3 41.2 dBm ACLR -58 dBc P1dB 24.8 dBm NF 1.55 dB References [1] Ward, A. (2001) Agilent ATF-54143 Low Noise Enhance- ment Mode Pseudomorphic HEMT in a Surface Mount Plastic Package, 2001 [Internet], Available from: <http://www.agilent.com/view/rf> [Accessed 22 August, 2002]. [2] Biasing Circuits and Considerations for GaAs MESFET Power Amplifiers, 2001 [Internet], Available from: <http://www.rf-solutions.com/ pdf/AN-0002_ajp.pdf> [Accessed

22 August, 2002]

2 x 2 LPCC (JEDEC DFP-N) Package Dimensions

Ordering Information

Part Number No. of Devices Container ATF-521P8-TR1 3000 7 ” Reel ATF-521P8-TR2 10000 13 ”Reel ATF-521P8-BLK 100 antistatic bag Device Models Refer to Agilent’s Web Site www.agilent.com/view/rf D E A P e pin1 R L b DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MIN. 0.70 0.225 1.9 0.65 1.9 1.45 NOM. 0.75 0.02

0.203 REF

0.25 2.0 0.80 2.0 1.6

0.50 BSC

MAX. 0.80 0.05 0.275 2.1 0.95 2.1 1.75 SYMBOL A b D E e pin1 2PX Top View End ViewEnd View Bottom View A A1

PCB Land Pattern and Stencil Design 2.80 (110.24) 0.70 (27.56) 0.25 (9.84) 0.25 (9.84) 0.50 (19.68) 0.28 (10.83) 0.60 (23.62) φ0.20 (7.87) PIN 1 Soldermask RF transmission line 0.80 (31.50) 0.15 (5.91) 0.55 (21.65) 1.60 (62.99) 2.72 (107.09) 0.63 (24.80) 0.22 (8.86) 0.32 (12.79) 0.50 (19.68) 0.25 (9.74) 0.63 (24.80) Stencil Layout (top view)PCB Land Pattern (top view) 0.72 (28.35) PIN 1 1.54 (60.61) USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL 8 mm 4 mm 2PX2PX2PX2PX

F W E 10° Max DESCRIPTION SYMBOL SIZE (mm) SIZE (inches) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER P 2.30 ± 0.05 2.30 ± 0.05 1.00 ± 0.05 4.00 ± 0.10 1.00 + 0.25 0.091 ± 0.004 0.091 ± 0.004 0.039 ± 0.002 0.157 ± 0.004 0.039 + 0.002 CAVITY DIAMETER PITCH POSITION D E 1.50 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 0.060 ± 0.004 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 0.254 ± 0.02 0.315 ± 0.012 8.00 – 0.10 0.315 ± 0.004 0.010 ± 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.0004 COVER TAPE D Tt 10° Max

www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788 6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright © 2003 Agilent Technologies, Inc. Obsoletes 5988-8403 July 29, 2003 5988-9974EN