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Document overview
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Technical content
Features
- PLL Transmitter IC with Single-ended Output High Output Power (6 dBm) Low Current Consumption at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Divide by 24 (ATA8404) and 32 (ATA8405) Blocks for 13 MHz Crystal Frequencies and for Low XTO Start-up Times ASK/FSK Modulation with Internal FSK Switch Up to 20 kBaud Manchester Coding, Up to 40 kBaud NRZ Coding Power-down ENABLE Input for Parallel Usage of Controlling Pins Supply Voltage 2.0V to 3.6V ESD Protection at all Pins (4 kV HBM) Small Package TSSOP10 Benefits Low Parasitic FSK Switch Integrated Fast Settling Time < 0.85 ms Small Form Factor
Applications
Remote Control Systems Alarm, Telemetering, and Energy Metering Systems Home Entertainment and Home Automation Industrial/Aftermarket Remote Keyless Entry Systems Toys 1. Description The ATA8404/ATA8405 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission systems at data rates up to 20 kBaud Man- chester coding and 40 kBaud NRZ coding. The transmitting frequency range is 313 MHz to 317 MHz (ATA8404) and 432 MHz to 448 MHz (ATA8405), respectively. It can be used in both FSK and ASK systems. Figure 1-1. System Block Diagram Demod. IF Amp LNA VCO PLL XTO Control ATA8201 ATA8202 ATA8203 ATA8204 1...3 µC Power amp. XTO VCO PLL ATA8404 ATA8405 Antenna Antenna UHF ASK/FSK TPM and Remote control transmitter UHF ASK/FSK Remote control receiver Encoder ATARx9x
1 Li cell
9136C–INDCO–10/09
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 2. Pin Configuration Figure 2-1. Pinning TSSOP10 CLK ASK FSK ANT2 ENABLE GND VS XTO1 ATA8404 ATA8405 5ANT1 6 XTO2 Table 2-1. Pin Description Pin Symbol Function Configuration 1C L K Clock output signal for the microcontroller. The clock output frequency is set by the crystal to fXTAL/8. The CLK output stays Low in power-down mode and after enabling of the PLL. The CLK output switches on if the oscillation amplitude of the crystal has reached a certain level.
2 ASK
Switches on the power amplifier for ASK modulation and enables the PLL and XTO if the ENABLE pin is open. 3F S K Switches off the FSK switch (switch has high Z if signal at pin FSK is High) and enables the PLL and the XTO if the ENABLE pin is open CLK VS 100 100 200k ASK 50k VRef = 1.1V 20 µA 200k FSK 200k VRef = 1.1V 5 µA 200k
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary]
4 ANT2 Emitter of an tenna output stage
5 ANT1 Open collector antenna output
6 XTO2 Diode switch, used for FSK modulation
7 XTO1 Connection for crystal
8 VS Supply voltage See ESD protection circuitry (see Figure 4-9 on page 14)
9 GND Ground See ESD protection circuitry (see Figure 4-9 on page 14)
10 ENABLE
If ENABLE is connected to GND and the ASK or FSK pin is High, the device stays in idle mode. In normal operation ENABLE is left open and ASK or FSK is used to enable the device. Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration ANT1 ANT2 XTO2 210 µA(FSK < 0.25V) AND (ENABLE > 1.7V) XTO1 1.2k VS 1.5k VS 182 µA ENABLE 150k 30 µA (FSK >1.7 V ) OR (ASK > 1.7 V) 250k VS
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Figure 2-2. Block Diagram 3. General Description This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature trans- mitters for remote control and other industrial applications. The VCO is locked to 24 × f XTAL/32 × fXTAL for ATA8404/ATA8405. Thus, a 13.125 MHz/13.56 MHz crystal is needed for a 315 MHz/433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance (current mode ) oscillator. Only one capacitor and a crystal connected in series to GND are needed as exte rnal elements in an ASK system. The internal FSK switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter time will result. The CLK output is switched on if the amplitude of the current flowing through the crystal has reached 35% to 80% of its final value. This is synchronized with the 1.64/1.69 MHz CLK out- put. As a result, the first period of the CLK output is always a full period. The PLL is then locked < 250 µs after CLK output activation. This means an additional wait time of ≥ 250 µs is necessary before the PA can be switched on and the data transmission can start. This results in a significantly lower time of about 0.85 ms between enabling the ATA8404/ATA8405 and the beginning of the data transmission which saves battery power. CLK FSK ANT2 ANT1 ENABLE GND VS XTO2 5 6 VCO LF CP f 24/ XTO PLL PA f Power up/down ATA8405 PFD ASK XTO1 EN OR EN Ampl. OK
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] The power amplifier is an open-collector output delivering a current pulse which is nearly inde- pendent from the load impedance and can therefore be controlled via the connected load impedance. This output configuration enables a simple ma tching to any kind of antenna or to 50 Ω. A high power efficiency for the power amplifier results if an optimized load impedance of Z Load, opt =3 8 0Ω +j 3 4 0Ω (ATA8404) at 315 MHz and Z Load, opt = 280Ω + j310Ω (ATA8405) at 433.92 MHz is used at the 3-V supply voltage. 4. Functional Description If ASK = Low, FSK = Low, and ENABLE = open or Low, the circuit is in power-down mode consuming only a very small amount of current so that a lithium cell used as power supply can work for many years. If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input pins. This means, the IC can be switched on by either the FSK of the ASK input. If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO, and power amplifier are off and the microcont roller ports controlling the ASK and FSK inputs can be used to control other devices. This can help to save ports on the microcontroller in systems where other devices with 3-wire interface are used. With FSK = High, ASK = Low, and ENABLE = open or High, the PLL and the XTO are switched on and the power amplifier is off. When the amplitude of the current through the crys- tal has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The CLK output stays Low until the CLK driver has been activated. The driver is activated syn- chronously with the CLK output frequency, hence, the first pulse on the CLK output is a complete period. The PLL is then locked within < 250 µs after the CLK driver has been acti- vated, and the transmitter is then ready for data transmission. With ASK = High, the power amplifier is switched on. This is used to perform the ASK modula- tion. During ASK modulation, the IC is enabled with the FSK or the ENABLE pin. With FSK = Low the switch at pin XTO2 is closed, with FSK = High the switch is open. To achieve a faster start-up of the crystal oscillator, the FSK pin should be High during start-up of the XTO because the series resistance of the resonator seen from pin XTO1 is lower if the switch is off. The different modes of the ATA8404/ATA8405 are listed in Table 4-1, the corresponding cur- rent consumption values can be found in the table “Electrical Characteristics” on page 15. Table 4-1. ATA8404/ATA8405 Modes ASK Pin FSK Pin ENABLE Pin Mode Low Low Low/open Power-down mode, FSK switch High Z Low Low High Power-up, PA off, FSK switch Low Z Low High High/open Power-up, PA off, FSK switch High Z High Low High/open Power-up, PA on, FSK switch Low Z High High High/open Power-up, PA on, FSK switch High Z Low/High High Low Idle mode, FSK switch High Z High Low/High Low Idle mode, FSK switch High Z
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary]
4.1 Transmission with ENABLE = open
4.1.1 ASK Mode
The ATA8404/ATA8405 is activated by ENABLE = open, FSK = High, ASK = Low. The micro- controller is then switched to external clocki ng. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal cl ocking. Then, the ATA8404/ATA8405 is switched to power-down mode with FSK = Low. Figure 4-1. Timing ASK Mode with ENABLE not Connected to the Microcontroller
4.1.2 FSK Mode
The ATA8404/ATA8405 is activated by FSK = High, ASK = Low. The microcontroller is then switched to external clocking. Af ter typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready. After another time period of ≤ 250 µs, the PLL is locked and ready to transm it. The power amplifier is switched on with ASK = H. The ATA8404/ATA8405 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower; if FSK = H the output frequency is higher. After transmission, FSK stays High and ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with FSK = Low. Figure 4-2. Timing FSK Mode with ENABLE not Connected to the Microcontroller FSK CLK Power-up, PA off ASK ΔTXTO Power-down Power-up, PA on (High) > 250 µs Power-downPower-up, PA off (Low) FSK CLK Power-up, PA off ASK ΔTXTO Power-down Power-up, PA on (fRF = High) > 250 µs Power-downPower-up, PA off (fRF = Low)
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary]
4.2 Transmission with ENABLE = High
4.2.1 FSK Mode
The ATA8404/ATA8405 is activated by ENAB LE = High, FSK = High, and ASK = Low. The microcontroller is then switched to external cl ocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The ATA8404/ATA8405 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. A fter transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low. Figure 4-3. Timing FSK Mode with ENABLE Connected to the Microcontroller
4.2.2 ASK Mode
The ATA8404/ATA8405 is activated by EN ABLE = High, FSK = High and ASK = Low. After activation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low. FSK CLK Power-up, PA off ASK ΔTXTO Power-down Power-up, PA on (fRF = High) > 250 µs Power-downPower-up, PA off (fRF = Low) ENABLE
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Figure 4-4. Timing ASK Mode with ENABLE Connected to the Microcontroller
4.3 Accuracy of Frequency Deviation
The accuracy of the frequency deviation using the XTAL pulling method is about ±20% if the following tolerances are considered. One important aspect is that the values of C 0 and CM of typical crystals are strongly correlated, which reduces the tolerance of the frequency deviation. Figure 4-5. Tolerances of Frequency Modulation Using a crystal with a motional capacitance of CM = 4.37 fF ±15%, a nominal load capacitance of C LNOM = 18 pF and a parallel capacitance of C 0 = 1.30 pF correlated with C M results in C0 =2 9 7× CM (the correlation has a tolerance of 10%, so C0 = 267 to 326 × CM). If using the internal FSK switch with C Switch = 0.9 pF ±20% and estimated parasitics of C Stray =0 . 7p F ±10%, the resulting C 4 and C5 values are C4 = 10 pF ±1% and C 5 = 15 pF ±1% for a nominal frequency deviation of ±19.3 kHz with worst case tolerances of ±15.8 kHz to ±23.2 kHz. FSK CLK Power-up, PA off ASK ΔTXTO Power-down Power-up, PA on (High) > 250 µs Power-downPower-up, PA off (Low) ENABLE VS XTAL CM LM RS CStray Crystal equivalent circuit CSwitch
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary]
4.4 Accuracy of th e Center Frequency
The imaginary part of the impedance in large signal steady state oscillation IM XTO, seen into the pin 7 (XTO1), causes some additional fr equency tolerances, due to pulling of the XTO oscillation frequency. These tolerances have to be added to the tolerances of the crystal itself (adjustment tolerance, temperature stability and ageing) and the impact on the center fre- quency due to tolerances of C 4, C5, CSwitch and CStray. The nominal value of IM XTO =1 1 0Ω, CSwitch and CStray should be absorbed into the C 4 and C5 values by using a crystal with known frequency and choosing C 4 and C5, so that the XTO center frequency equals the crystal fre- quency, and the frequency deviation is as ex pected. Then, from the nominal value, the IM XTO has ±90 Ω tolerances, using the pulling formula P = –IM XTO × C M × π × fXTO with fXTO = 13.56 MHz and C M = 4.4 fF an additional frequency tolerance of P = ±16.86 ppm results. If using crystals with other C M the additional frequency tolerance can be calculated in the same way. For example, a lower C M = 3.1 fF will reduce the frequency tolerance to 11.87 ppm, where a higher CM = 5.5 fF increases the tolerance to 21.07 ppm.
4.5 CLK Output
An output CLK signal of 1.64 MHz (ATA8404 operating at 315 MHz) and 1.69 MHz (ATA8405 operating at 433.92 MHz) is provided for a c onnected microcontroller. The delivered signal is CMOS-compatible with a High and Low time of >125 ns if the load capacitance is lower than 20 pF. The CLK output is Low in power-down mode due to an internal pull-down resistor. After enabling the PLL and XTO the signal stays Low until the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. Then, the CLK output is activated synchronously with its output signal so that the first period of the CLK output signal is a full period.
4.5.1 Clock Pulse Take-over by Microcontroller
The clock of the crystal oscillator can be us ed for clocking the mi crocontroller. Atmel’s ATARx9x microcontroller family provides the sp ecial feature of starting with an integrated RC oscillator to switch on the ATA8404/ATA8405’s external clocking and to wait automatically until the CLK output of the ATA8404/ATA8405 is activated. After a time period of 250 µs the mes- sage can be sent with crystal accuracy.
4.5.2 Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of Z Load, opt = 380Ω +j 3 4 0Ω (ATA8404) at 315 MHz and ZLoad, opt =2 8 0Ω +j 3 1 0Ω (ATA8405) at 433.92 MHz. A low resistive path to V S is required to deliver the DC current (see Figure 4-6 on page 10). The power amplifier delivers a current pulse and the maximum output power is delivered to a resistive load if the 0.66 pF output capacitance of the power amplifier is compensated by the load impedance. At the ANT1 pin, the RF output amplitude is about VS – 0.5V. The load impedance is defined as the impedance seen from the ATA8404’s ANT1, ANT2 into the matching network. Do not mix up this large-signal load impedance with a small-signal input impedance delivered as an input characteristic of RF amplifiers. The latter is measured from the application into the IC instead of from the IC into the applica- tion for a power amplifier.
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] The output capacitance of 0.66 pF will be absorbed into the load impedance, so a real imped- ance of 684 Ω (ATA8404) at 315 MHz and 623 Ω (ATA8405) at 433.92 MHz should be measured with a network analyses at pin 5 (ANT1) with the ATA8404/ATA8405 soldered, an optimized antenna connected, and the power amplifier switched off. Less output power is achieved by lowering the real parallel part where the parallel imaginary part should be kept constant. Lowering the real part of the load impedance also reduces the supply voltage dependency of the output power. Output power measurement can be done with the circuit as shown in Figure 4-6. Please note that the component values must be changed to compensate for the individual board parasitics until the ATA8404/ATA8405 has the right load impedance. Also, the damping of the cable used to measure the output power must be calibrated. Figure 4-6. Output Power Measurement ATA8404/ATA8405 Table 4-2 and Table 4-3 show the output power and the supply current versus temperature and supply voltage. Table 4-2. Output Power and Supply Current versus Temperature and Supply Voltage for the ATA8404 with ZLoad =3 8 0Ω +j 3 4 0Ω (Correlation Tested) Ambient Temperature VS = 2.0V (dBm/mA) VS = 3.0V (dBm/mA) VS = 3.6V (dBm/mA) Table 4-3. Output Power and Supply Current versus Temperature and Supply Voltage for the ATA8405 with ZLoad =2 8 0Ω +j 3 1 0Ω (Correlation Tested) Ambient Temperature VS = 2.0V (dBm/mA) VS = 3.0V (dBm/mA) VS = 3.6V (dBm/mA) ANT2 ANT1 Rin Power meter C1 = 1n L1 = 68 nH/ 39 nH C2 = 2.2 pF/1.8 pFZLopt VS Z = 50 Ω 50 Ω
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary]
4.6 Application Circuits
For the supply voltage blocking capacitor C3, a value of 68 nF/X7R is recommended (see Fig- ure 4-7 on page 12 and Figure 4-8 on page 13). C1 and C2 are used to match the loop antenna to the power amplifier. For C2, two capacitors in series should be used to achieve a better tol- erance value and to enable it to realize ZLoad,opt by using capacitors with standard values. Together with the pins of ATA8404 and the PCB board wires, C 1 forms a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally, the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (50 nH to 100 nH) can be printed on the PCB. C 4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 10 pF results in a 12 pF load-capacitance crystal due to the board parasitic capacitances and the inductive impedance of the XTO1 pin.
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Figure 4-7. ASK Application Circuit ANT2 ANT1 ENABLE AVR® (ATtiny) VS VS C4Loop Antenna BPXY OSC1 BPXY BPXY VSS VDD 1 VS XTAL BPXY CLK FSK GND VS XTO2 5 6 VCO LF CP f 24/ XTO PLL PA f Power up/down ATA8404/ATA8405 PFD ASK XTO1 EN OR EN Ampl. OK
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Figure 4-8. FSK Application Circuit ANT2 ANT1 ENABLE AVR (ATtiny) VS VS Loop Antenna BPXY OSC1 BPXY BPXY VSS VDD 1 VS XTAL BPXY CLK FSK GND VS XTO2 5 6 VCO LF CP f 24/ XTO PLL PA f Power up/down ATA8404/ATA8405 PFD ASK XTO1 EN OR EN Ampl. OK
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Figure 4-9. ESD Protection Circuit CLK FSK ANT2 ANT1 XTO1 ENABLE VS GND XTO2ASK 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Minimum Maximum Unit Supply voltage V S 5V Power dissipation P tot 100 mW Junction temperature T j 150 °C Storage temperature T stg –55 +85 °C Ambient temperature T amb1 –55 +85 °C Ambient temperature in power-down mode for 15 minutes without damage with VS ≤ 3.2V VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK <0 . 2 5 V Tamb2 175 °C Input voltage V maxASK –0.3 (V S + 0.3)(1) V 6. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 170 K/W
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 7. Electrical Characteristics VS = 2.0V to 3.6V, Tamb = –40°C to +85°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37 fF , C0 = 1.3 pF , CLNOM =1 8p F , C4 =1 0p F , C5 = 15 pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current, power-down mode VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK <0 . 2 5 V Tamb =2 5 ° C Tamb =– 4 0° C to +85°C IS_Off 1 100 350 nA nA Supply current, idle mode VENABLE < 0.25V, VS ≤ 3.2V ASK,FSK can be Low or High IS_IDLE 100 µA Supply current, power-up, PA off, FSK switch High Z VS ≤ 3.2V, VFSK >1 . 7 V , VASK < 0.25V ENABLE is open IS 3.6 4.6 mA Supply current, power-up, PA on, FSK switch High Z VS ≤ 3.2V, C CLK ≤ 10 pF VFSK >1 . 7 V , VASK >1 . 7 V ENABLE is open ATA8404 ATA8405 IS_Transmit1 8.1 8.5 9.8 10.5 mA mA Supply current, power-up, PA on, FSK Low Z VS ≤ 3.2V, C CLK ≤ 10 pF VFSK< 0.25V, VASK >1 . 7 V ENABLE is open ATA8404 ATA8405 I S_Transmit2 8.4 8.8 10.2 11.0 mA mA Output power VS =3 . 0 V , Tamb = 25°C, f = 315 MHz for ATA8404, ZLoad, opt = (380 + j340)Ω f = 433.92 MHz for ATA8405, ZLoad, opt = (280 + j310)Ω POut 468 d B m Output power for the full temperature and supply voltage range Tamb = –40°C to +85°C, VS = 2.0V to 3.2V POut 18 . 2 d B m Spurious emission fCLK = f XT0/8 Load capacitance at pin CLK ≤ 20 pF f0 ±fCLK f0 ±fXT0 other spurious are lower Spour –42 –60 dBc Harmonics With 50Ω matching network according to Figure 4-6 on page 10 2nd 3rd –16 –15 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/24 ATA8404 fXTO = f0/32 ATA8405 fXTAL = resonant frequency of the XTAL, CM = 4.37 fF , load capacitance selected accordingly Tamb = –40°C to +85°C ΔfXTO –14.0 f XTAL +14.0 ppm Imaginary part of XTO1 Impedance in steady state oscillation Since pulling P is P = –IM XTO × CM × π × fXTO ΔfXTO can be calculated out of IMXTO with CM =4 . 3 7f F IMXTO j20 j110 j200 Ω
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Real part of XTO1 impedance in small signal oscillation This value is important for crystal oscillator start-up REXTO –650 –1100 Ω Crystal oscillator start-up time Time between ENABLE of the IC with FSK = H and activation of the CLK output. The CLK is activated synchronously to the output frequency if the current through the XTAL has reached 35% to 80% of its maximum amplitude. Crystal parameters: C M = 4.37 fF , C0 = 1.3 pF , CLNOM =1 8p F , C4 =1 0p F , C5 =1 5p F , RS ≤ 60Ω ΔTXTO 0.6 1.4 ms XTO drive current Current flowing through the crystal in steady state oscillation (peak-to-peak value) IDXTO 300 µApp Locking time of the PLL Time between the activation of CLK and when the PLL is locked (transmitter ready for data transmission) ΔT PLL 250 µs PLL loop bandwidth f Loop_PLL 250 kHz In loop phase noise PLL 25 kHz distance to carrier L PLL –85 –76 dBc/Hz Phase noise VCO at 1 MHz at 36 MHz Lat1M Lat36M –90 –121 –84 –115 dBc/Hz dBc/Hz Frequency range of VCO ATA8404 ATA8405 fVCO 310 432 317 448 MHz MHz Clock output frequency (CMOS microcontroller compatible) ATA8404 ATA8405 fCLK f0/192 f0/256 MHz Clock output minimum High and Low time CLoad ≤ 20 pF , High = 0.8 × Vs, Low = 0.2 × VS, fCLK <1 . 7M H z TCLKLH 125 ns Series resonance resistance of the resonator seen from pin XTO1 For proper detection of the XTO amplitude Rs_max 150 Ω Capacitive load at Pin XTO1 C L_max 5p F FSK modulation frequency rate This corresponds to 20 kBaud in Manchester coding and 40 kBaud in NRZ coding f MOD_FSK 02 0 k H z FSK switch OFF resistance High Z R SWIT_OFF 50 k Ω FSK switch OFF capacitance High Z capacitance C SWIT_OFF 0.75 0.9 1.1 pF FSK switch ON resistance Low Z R SWIT_ON 130 175 Ω ASK modulation frequency rate Duty cycle of the modulation signal = 50%, this corresponds to 20 kBaud in Manchester coding and 40 kBaud in NRZ coding f MOD_ASK 02 0 k H z 7. Electrical Characteristics (Continued) VS = 2.0V to 3.6V, Tamb = –40°C to +85°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37 fF , C0 = 1.3 pF , CLNOM =1 8p F , C4 =1 0p F , C5 = 15 pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Max. Unit
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] ASK input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 VS V V µA FSK input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 VS V V µA ENABLE input Low level input voltage High level input voltage Input current high Input current Low V Il VIh IInh IInl 1.7 –40 –40 0.25 V S +40 +40 V V µA µA 7. Electrical Characteristics (Continued) VS = 2.0V to 3.6V, Tamb = –40°C to +85°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37 fF , C0 = 1.3 pF , CLNOM =1 8p F , C4 =1 0p F , C5 = 15 pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Max. Unit
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 9. Package Information TSSOP10 8. Ordering Information Extended Type Number Package Remarks ATA8404-6DQY TSSOP10 Pb-free ATA8405-6DQY TSSOP10 Pb-free specifications according to DIN technical drawings 0.5 nom. 0.25 13 4 52 10 8 7 69 0.15 4 x 0.5 = 2 nom. 1.1 max 0.85±0.1 3±0.1 3.8±0.3 4.9±0.1 3±0.1 Issue: 3; 16.09.05 Drawing-No.: 6.543-5095.01-4 Package: TSSOP 10 (acc. to JEDEC Standard MO-187) Dimensions in mm Not indicated tolerances ± 0.05
9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9136C-INDCO-10/09 • Section 8 “Ordering Information” on page 18 changed 9136B-INDCO-06/09
- Figure 1-1 “System Block Diagram” on page 1 changed
- Figure 4-7 “ASK Application Circuit” on page 12 changed
- Figure 4-8 “FSK Application Circuit” on page 13 changed
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