ATA8404_14 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 18

Technical content

Features

  • PLL transmitter IC with single-ended output
  • High output power (6dBm)
  • Low current consumption at 8.1mA (315MHz) and 8.5mA (433MHz)
  • Divide by 24 (Atmel® ATA8404) and 32 (Atmel ATA8405) blocks for 13MHz crystal frequencies and for low XTO start-up times
  • ASK/FSK modulation with internal FSK switch
  • Up to 20Kbps manchester coding, up to 40Kbps NRZ coding
  • Power-down
  • ENABLE input for parallel usage of controlling pins
  • Supply voltage range: 1.9V to 3.6V
  • ESD protection at all pins (4kV HBM)
  • Small package TSSOP10 Benefits
  • Low parasitic FSK switch integrated
  • Fast settling time < 0.85ms
  • Small form factor

Applications

  • Remote control systems
  • Alarm, telemetering, and energy metering systems
  • Home entertainment and home automation
  • Industrial/aftermarket remote keyless entry systems
  • Toys ATA8404/ATA8405 UHF ASK/FSK Transmitter DATASHEET

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 1. Description The Atmel® ATA8404/ATA8405 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission systems at data rates up to 20kBaud Manchester coding and 40kBaud NRZ coding. The transmitting frequency range is 313MHz to 317MHz (Atmel ATA8404) and 432MHz to 448MHz (Atmel ATA8405), respectively. It can be used in both FSK and ASK systems. Figure 1-1. System Block Diagram Micro- controller PLL UHF ASK/FSK Remote control receiver UHF ASK/FSK TPM and Remote control transmitter ATA8404 ATA8405 ATA8201 ATA8202 ATA8203 ATA8204 LNA VCO PLL XTO Power amp. VCO Antenna Demod IF Amp Control 1 to 3 Encoder ATARx9x XTO

1 Li cell

3ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 2. Pin Configuration Figure 2-1. Pinning TSSOP10 Table 2-1. Pin Description Pin Symbol Function Configuration

1 CLK

Clock output signal for the microcontroller. The clock output frequency is set by the crystal to f XTAL/8. The CLK output stays Low in power-down mode and after enabling of the PLL. The CLK output switches on if the oscillation amplitude of the crystal has reached a certain level.

2 ASK

Switches on the power amplifier for ASK modulation and enables the PLL and XTO if the ENABLE pin is open.

3 FSK

Switches off the FSK switch (switch has high Z if signal at pin FSK is High) and enables the PLL and the XTO if the ENABLE pin is open CLK ASK FSK ANT2 ENABLE GND VS XTO1 ATA8404 ATA8405 5ANT1 6 XTO2 100Ω 100Ω 200kΩ CLK VS 20μA VREF = 1.1VASK 50kΩ 200kΩ 5μA VREF = 1.1VFSK 200kΩ 200kΩ

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14

4 ANT2 Emitter of antenna output stage

5 ANT1 Open collector antenna output

6 XTO2 Diode switch, used for FSK

7 XTO1 Connection for crystal

8 VS Supply voltage See ESD protection circuitry (see Figure 4-9 on page 12)

9 GND Ground See ESD protection circuitry (see Figure 4-9 on page 12)

10 ENABLE

If ENABLE is connected to GND and the ASK or FSK pin is High, the device stays in idle mode. In normal operation ENABLE is left open and ASK or FSK is used to enable the device. Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration ANT1 ANT2 210μA XT02 (FSK < 0.25V) and (ENABLE > 1.7V) 182μA XTO1 VSVS 1.5kΩ 1.2kΩ 30μA VS ENABLE (FSK > 1.7V) or (ASK > 1.7V) 250kΩ 150kΩ

5ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 Figure 2-2. Block Diagram 3. General Description This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmitters for remote control and other industrial applications. The VCO is locked to 24 × fXTAL/32 × fXTAL for Atmel® ATA8404/ATA8405. Thus, a 13.125MHz/13.56MHz crystal is needed for a 315MHz/433.92MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal connected in series to GND are needed as external elements in an ASK system. The internal FSK switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator needs typically 0.6ms until the CLK output is activated if a crystal as defined in the electrical characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter time will result. The CLK output is switched on if the amplitude of the current flowing through the crystal has reached 35% to 80% of its final value. This is synchronized with the 1.64/1.69MHz CLK output. As a result, the first period of the CLK output is always a full period. The PLL is then locked < 250µs after CLK output activation. This means an additional wait time of ≥ 250µs is necessary before the PA can be switched on and the data transmission can start. This results in a significantly lower time of about 0.85ms between enabling the Atmel ATA8404/ATA8405 and the beginning of the data transmission which saves battery power. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance and can therefore be controlled via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency for the power amplifier results if an optimized load impedance of ZLoad, opt = 380Ω + j340Ω (Atmel ATA8404) at 315MHz and ZLoad, opt =2 8 0Ω +j 3 1 0Ω (Atmel ATA8405) at 433.92MHz is used at the 3-V supply voltage. ATA8405 CP Power up/down PDFOR 24/ XTO2 XTO1 GND ENABLE ANT1 ANT2 FSK CLK f LF PA VCO PLL XTO Ampl. OK EN EN f VS ASK

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 4. Functional Description If ASK = Low, FSK = Low, and ENABLE = open or Low, the circuit is in power-down mode consuming only a very small amount of current so that a lithium cell used as power supply can work for many years. If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input pins. This means, the IC can be switched on by either the FSK of the ASK input. If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO, and power amplifier are off and the microcontroller ports controlling the ASK and FSK inputs can be used to control other devices. This can help to save ports on the microcontroller in systems where other devices with 3-wire interface are used. With FSK = High, ASK = Low, and ENABLE = open or High, the PLL and the XTO are switched on and the power amplifier is off. When the amplitude of the current through the crystal has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The CLK output stays Low until the CLK driver has been activated. The driver is activated synchronously with the CLK output frequency, hence, the first pulse on the CLK output is a complete period. The PLL is then locked within < 250µs after the CLK driver has been activated, and the transmitter is then ready for data transmission. With ASK = High, the power amplifier is switched on. This is used to perform the ASK modulation. During ASK modulation, the IC is enabled with the FSK or the ENABLE pin. With FSK = Low the switch at pin XTO2 is closed, with FSK = High the switch is open. To achieve a faster start-up of the crystal oscillator, the FSK pin should be High during start-up of the XTO because the series resistance of the resonator seen from pin XTO1 is lower if the switch is off. The different modes of the Atmel® ATA8404/ATA8405 are listed in Table 4-1, the corresponding current consumption values can be found in the table “Electrical Characteristics” on page 13.

4.1 Transmission with ENABLE = open

4.1.1 ASK Mode

The Atmel ATA8404/ATA8405 is activated by ENABLE = open, FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the Atmel ATA8404/ATA8405 is switched to power-down mode with FSK = Low. Table 4-1. Atmel ATA8404/ATA8405 Modes ASK Pin FSK Pin ENABLE Pin Mode Low Low Low/open Power-down mode, FSK switch High Z Low Low High Power-up, PA off, FSK switch Low Z Low High High/open Power-up, PA off, FSK switch High Z High Low High/open Power-up, PA on, FSK switch Low Z High High High/open Power-up, PA on, FSK switch High Z Low/High High Low Idle mode, FSK switch High Z High Low/High Low Idle mode, FSK switch High Z

7ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 Figure 4-1. Timing ASK Mode with ENABLE not Connected to the Microcontroller

4.1.2 FSK Mode

The Atmel® ATA8404/ATA8405 is activated by FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready. After another time period of ≤ 250µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The Atmel ATA8404/ATA8405 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower; if FSK = H the output frequency is higher. After transmission, FSK stays High and ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with FSK = Low. Figure 4-2. Timi ng FSK Mode with ENABLE not Connected to the Microcontroller

4.2 Transmission with ENABLE = High

4.2.1 FSK Mode

The Atmel ATA8404/ATA8405 is activated by ENABLE = High, FSK = High, and ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The Atmel ATA8404/ATA8405 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the Atmel ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low. Power-downPower-down Power-up, PA off Power-up, PA on (High) Power-up, PA off (Low) FSK ASK CLK ΔTXTO > 250 μs Power-downPower-down Power-up, PA off Power-up, PA on (fRF = High) Power-up, PA off (fRF = Low) FSK ASK CLK ΔTXTO > 250 μs

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 Figure 4-3. Timi ng FSK Mode with ENABLE Connected to the Microcontroller

4.2.2 ASK Mode

The Atmel ATA8404/ATA8405 is activated by ENABLE = High, FSK = High and ASK = Low. After activation the microcontroller is switched to external clocking. After typically 0.6ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the Atmel ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low. Figure 4-4. Timing ASK Mode with ENABLE Connected to the Microcontroller Power-downPower-down Power-up, PA off Power-up, PA on (fRF = High) Power-up, PA off (fRF = Low) FSK ENABLE ASK CLK ΔTXTO > 250 μs Power-downPower-down Power-up, PA off Power-up, PA on (High) Power-up, PA off (Low) FSK ENABLE ASK CLK ΔTXTO > 250 μs

9ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14

4.3 Accuracy of Frequency Deviation

The accuracy of the frequency deviation using the XTAL pulling method is about ±20% if the following tolerances are considered. One important aspect is that the values of C0 and CM of typical crystals are strongly correlated, which reduces the tolerance of the frequency deviation. Figure 4-5. Tolerances of Frequency Modulation Using a crystal with a motional capacitance of CM = 4.37fF ±15%, a nominal load capacitance of CLNOM = 18pF and a parallel capacitance of C0 = 1.30pF correlated with CM results in C0 = 297 × CM (the correlation has a tolerance of 10%, so C0 = 267 to 326 × CM). If using the internal FSK switch with CSwitch = 0.9pF ±20% and estimated parasitics of CStray = 0.7pF ±10%, the resulting C4 and C5 values are C4 = 10pF ±1% and C5 = 15pF ±1% for a nominal frequency deviation of ±19.3kHz with worst case tolerances of ±15.8kHz to ±23.2kHz.

4.4 Accuracy of the Center Frequency

The imaginary part of the impedance in large signal steady state oscillation IMXTO, seen into the pin 7 (XTO1), causes some additional frequency tolerances, due to pulling of the XTO oscillation frequency. These tolerances have to be added to the tolerances of the crystal itself (adjustment tolerance, temperature stability and ageing) and the impact on the center frequency due to tolerances of C4, C5, CSwitch and CStray. The nominal value of IMXTO = 110Ω, CSwitch and CStray should be absorbed into the C4 and C5 values by using a crystal with known frequency and choosing C4 and C5, so that the XTO center frequency equals the crystal frequency, and the frequency deviation is as expected. Then, from the nominal value, the IMXTO has ±90Ω tolerances, using the pulling formula P = –IMXTO × CM × π × fXTO with fXTO = 13.56MHz and CM = 4.4fF an additional frequency tolerance of P = ±16.86ppm results. If using crystals with other CM the additional frequency tolerance can be calculated in the same way. For example, a lower CM = 3.1fF will reduce the frequency tolerance to 11.87ppm, where a higher CM = 5.5fF increases the tolerance to 21.07ppm.

4.5 CLK Output

An output CLK signal of 1.64MHz (Atmel® ATA8404 operating at 315MHz) and 1.69MHz (Atmel ATA8405 operating at 433.92MHz) is provided for a connected microcontroller. The delivered signal is CMOS-compatible with a High and Low time of >125ns if the load capacitance is lower than 20pF. The CLK output is Low in power-down mode due to an internal pull- down resistor. After enabling the PLL and XTO the signal stays Low until the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. Then, the CLK output is activated synchronously with its output signal so that the first period of the CLK output signal is a full period.

4.5.1 Clock Pulse Take-over by Microcontroller

The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x microcontroller family provides the special feature of starting with an integrated RC oscillator to switch on the Atmel ATA8404/ATA8405’s external clocking and to wait automatically until the CLK output of the Atmel ATA8404/ATA8405 is activated. After a time period of 250µs the message can be sent with crystal accuracy. RS LM C4 CM VS XTAL Crystal equivalent circuit C0 C5 CSwitch CStray

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14

4.5.2 Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad, opt =3 8 0Ω +j 3 4 0Ω (Atmel ATA8404) at 315MHz and ZLoad, opt =2 8 0Ω +j 3 1 0Ω (Atmel ATA8405) at 433.92MHz. A low resistive path to VS is required to deliver the DC current (see Figure 4-6 on page 10). The power amplifier delivers a current pulse and the maximum output power is delivered to a resistive load if the 0.66pF output capacitance of the power amplifier is compensated by the load impedance. At the ANT1 pin, the RF output amplitude is about VS – 0.5V. The load impedance is defined as the impedance seen from the ATA8404’s ANT1, ANT2 into the matching network. Do not mix up this large-signal load impedance with a small-signal input impedance delivered as an input characteristic of RF amplifiers. The latter is measured from the application into the IC instead of from the IC into the application for a power amplifier. The output capacitance of 0.66pF will be absorbed into the load impedance, so a real impedance of 684Ω (Atmel® ATA8404) at 315MHz and 623Ω (Atmel ATA8405) at 433.92MHz should be measured with a network analyses at pin 5 (ANT1) with the Atmel ATA8404/ATA8405 soldered, an optimized antenna connected, and the power amplifier switched off. Less output power is achieved by lowering the real parallel part where the parallel imaginary part should be kept constant. Lowering the real part of the load impedance also reduces the supply voltage dependency of the output power. Output power measurement can be done with the circuit as shown in Figure 4-6. Please note that the component values must be changed to compensate for the individual board parasitics until the Atmel ATA8404/ATA8405 has the right load impedance. Also, the damping of the cable used to measure the output power must be calibrated. Figure 4-6. Output Power Measurement Atmel ATA8404/ATA8405 Table 4-2 and Table 4-3 show the output power and the supply current versus temperature and supply voltage. Table 4-2. Output Power and Supply Current versus Temperature and Supply Voltage for the Atmel ATA8404 with ZLoad = 380Ω +j 3 4 0Ω (Correlation Tested) Ambient Temperature VS = 2.0V (dBm/mA) VS = 3.0V (dBm/mA) VS = 3.6V (dBm/mA) Table 4-3. Output Power and Supply Current versus Temperature and Supply Voltage for the Atmel ATA8405 with ZLoad = 280Ω +j 3 1 0Ω (Correlation Tested) Ambient Temperature VS = 2.0V (dBm/mA) VS = 3.0V (dBm/mA) VS = 3.6V (dBm/mA) L1 = 68 nH/ 39 nH C2 = 2.2 pF/ 1.8 pF C1 = 1 nF VS Rin ANT2 ANT1 ZLopt Power meter 50Ω Z = 50Ω

11ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14

4.6 Application Circuits

For the supply voltage blocking capacitor C3, a value of 68nF/X7R is recommended (see Figure 4-7 on page 11 and Figure 4-8 on page 12). C1 and C2 are used to match the loop antenna to the power amplifier. For C2, two capacitors in series should be used to achieve a better tolerance value and to enable it to realize ZLoad,opt by using capacitors with standard values. Together with the pins of Atmel® ATA8404 and the PCB board wires, C1 forms a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally, the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5mm, otherwise the Q-factor of the loop antenna is too high. L1 (50nH to 100nH) can be printed on the PCB. C4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 10pF results in a 12pF load-capacitance crystal due to the board parasitic capacitances and the inductive impedance of the XTO1 pin. Figure 4-7. ASK Application Circuit ATA8404 ATA8405 CP Power up/down PDFOR 24/ XTO2 XTO1 XTAL GND ENABLE ANT1 ANT2 FSK CLK f LF VS PA VCO PLL XTO Ampl. OK EN EN f VS VS ASK Loop Antenna VDD BPXY VSS VS OSC1 BPXY BPXY BPXYS1 AVR® (ATtiny)

13ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Minimum Maximum Unit Supply voltage VS 5 V Power dissipation Ptot 100 mW Junction temperature Tj 150 °C Storage temperature Tstg –55 +85 °C Ambient temperature Tamb1 –55 +85 °C Ambient temperature in power-down mode for 15 minutes without damage with VS ≤ 3.2V VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK <0 . 2 5 V Tamb2 175 °C Input voltage VmaxASK –0.3 (VS + 0.3)(1) V 6. Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 170 K/W 7. Electrical Characteristics VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37fF, C0 = 1.3pF, CLNOM = 18pF, C4 =1 0 p F , C5 = 15pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply voltage VS 1.9 3.6 V Ambient temperature Tamb 0 +50 °C Supply current, power-down mode VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK <0 . 2 5 V Tamb = 25°C Tamb = 0°C to +50°C IS_Off 1 100 350 nA nA Supply current, idle mode VENABLE <0 . 2 5 V , VS ≤ 3.2V ASK,FSK can be Low or High IS_IDLE 100 µA Supply current, power-up, PA off, FSK switch High Z VS ≤ 3.2V, VFSK >1 . 7 V , VASK < 0.25V ENABLE is open IS 3.6 4.6 mA Supply current, power-up, PA on, FSK switch High Z VS ≤ 3.2V, CCLK ≤ 10pF VFSK >1 . 7 V , VASK >1 . 7 V ENABLE is open Atmel ATA8404 Atmel ATA8405 IS_Transmit1 8.1 8.5 9.8 10.5 mA mA Supply current, power-up, PA on, FSK Low Z VS ≤ 3.2V, CCLK ≤ 10pF VFSK<0 . 2 5 V , VASK >1 . 7 V ENABLE is open Atmel ATA8404 Atmel ATA8405 IS_Transmit2 8.4 8.8 10.2 11.0 mA mA

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 Output power f = 315MHz for Atmel ATA8404, ZLoad, opt = (380 + j340)Ω f = 433.92MHz for Atmel ATA8405, ZLoad, opt = (280 + j310)Ω POut 4 6 8 dBm Output power for the full temperature and supply voltage range Tamb = 0°C to +50°C POut 1 8.2 dBm Spurious emission fCLK = f XT0/8 Load capacitance at pin CLK ≤ 20pF f0 ±fCLK f0 ±fXT0 other spurious are lower Spour –42 –60 dBc Harmonics With 50Ω matching network according to Figure 4-6 on page 10 2nd 3rd –16 –15 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/24 Atmel ATA8404 fXTO = f0/32 Atmel ATA8405 fXTAL = resonant frequency of the XTAL, CM = 4.37fF, load capacitance selected accordingly Tamb = 0°C to +50°C ΔfXTO –14.0 fXTAL +14.0 ppm Imaginary part of XTO1 Impedance in steady state oscillation Since pulling P is P = –IM XTO × CM × π × fXTO ΔfXTO can be calculated out of IMXTO with CM =4 . 3 7 f F IMXTO j20 j110 j200 Ω Real part of XTO1 impedance in small signal oscillation This value is important for crystal oscillator start-up REXTO –650 –1100 Ω Crystal oscillator start-up time Time between ENABLE of the IC with FSK = H and activation of the CLK output. The CLK is activated synchronously to the output frequency if the current through the XTAL has reached 35% to 80% of its maximum amplitude. Crystal parameters: C M =4 . 3 7 f F , C0 = 1.3pF, CLNOM = 18pF, C4 = 10pF, C5 = 15pF, RS ≤ 60Ω ΔTXTO 0.6 1.4 ms XTO drive current Current flowing through the crystal in steady state oscillation (peak-to-peak value) IDXTO 300 µApp Locking time of the PLL Time between the activation of CLK and when the PLL is locked (transmitter ready for data transmission) ΔTPLL 250 µs PLL loop bandwidth fLoop_PLL 250 kHz In loop phase noise PLL 25kHz distance to carrier LPLL –85 –76 dBc/Hz Phase noise VCO at 1MHz at 36MHz Lat1M Lat36M –90 –121 –84 –115 dBc/Hz dBc/Hz Frequency range of VCO Atmel ATA8404 Atmel ATA8405 fVCO 310 432 317 448 MHz MHz 7. Electrical Characteristics (Continued) VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37fF, C0 = 1.3pF, CLNOM = 18pF, C4 =1 0 p F , C5 = 15pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Max. Unit

15ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 Clock output frequency (CMOS microcontroller compatible) Atmel ATA8404 Atmel ATA8405 fCLK f0/192 f0/256 MHz Clock output minimum High and Low time CLoad ≤ 20pF, High = 0.8 × Vs, Low = 0.2 × VS, fCLK <1 . 7 M H z TCLKLH 125 ns Series resonance resistance of the resonator seen from pin XTO1 For proper detection of the XTO amplitude Rs_max 150 Ω Capacitive load at Pin XTO1 CL_max 5 pF FSK modulation frequency rate This corresponds to 20kBaud in Manchester coding and 40kBaud in NRZ coding fMOD_FSK 0 20 kHz FSK switch OFF resistance High Z RSWIT_OFF 50 kΩ FSK switch OFF capacitance High Z capacitance CSWIT_OFF 0.75 0.9 1.1 pF FSK switch ON resistance Low Z RSWIT_ON 130 175 Ω ASK modulation frequency rate Duty cycle of the modulation signal = 50%, this corresponds to 20kBaud in Manchester coding and 40kBaud in NRZ coding fMOD_ASK 0 20 kHz ASK input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 VS V V µA FSK input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 VS V V µA ENABLE input Low level input voltage High level input voltage Input current high Input current Low VIl VIh IInh IInl 1.7 –40 –40 0.25 VS +40 +40 V V µA µA 7. Electrical Characteristics (Continued) VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37fF, C0 = 1.3pF, CLNOM = 18pF, C4 =1 0 p F , C5 = 15pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Max. Unit

ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 9. Package Information TSSOP10 8. Ordering Information Extended Type Number Package Remarks ATA8404C-6DQY TSSOP10 Pb-free ATA8405C-6DQY TSSOP10 Pb-free Package Drawing Contact: packagedrawings@atmel.com GPC DRAWING NO. REV. TITLE 6.543-5095.01-4 3 09/16/05 Package: TSSOP (acc. to JEDEC Standard MO-187) Not indicated tolerances ±0.05 Dimensions in mm specifications according to DIN technical drawings 0.5 nom. 0.25 13 4 52 10 8 7 69 0.15 4 x 0.5 = 2 nom. 1.1 max 0.85±0.1 3±0.1 3.8±0.3 4.9±0.1 3±0.1

17ATA8404/ATA8405 [DATASHEET] 9136G–AUTO–06/14 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9136G-AUTO-06/14 • Put datasheet in the latest template 9136F-AUTO-12/12 • Section 8 “Ordering Information” on page 18 changed 9136E-AUTO-10/11

  • Features on page 1 changed
  • Table 4.2 “Output Power and Supply Current ...” on page 10 changed
  • Table 4.3 “Output Power and Supply Current ...” on page 10 changed
  • Section 7 “Electrical Characteristics” on page 15 changed 9136D-AUTO-10/11 • Set datasheet from Preliminary to Standard 9136C-AUTO-10/09 • Section 8 “Ordering Information” on page 18 changed 9136B-AUTO-06/09
  • Figure 1-1 “System Block Diagram” on page 1 changed
  • Figure 4-7 “ASK Application Circuit” on page 12 changed
  • Figure 4-8 “FSK Application Circuit” on page 13 changed

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