ATA8403_08 ATMEL

Document overview

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Technical content

Features

  • Integrated PLL Loop Filter  ESD Protection also at ANT1/ANT2 (4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM)  High Output Power (5.5 dBm) with Low Supply Current (8.5 mA)  Modulation Scheme ASK/FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor Between the XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller  Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply  Single Li-cell for Power Supply  Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C  Package TSSOP8L  Single-ended Antenna Output with High Efficient Power Amplifier  CLK Output for Clocking the Microcontroller  One-chip Solution with Minimum External Circuitry

Applications

 Industrial/Aftermarket Remote Keyless Entry Systems  Alarm, Telemetering, and Energy Metering Systems  Remote Control Systems for Consumer and Industrial Markets  Access Control Systems  Home Automation  Home Entertainment  Toys 1. Description The ATA8403 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission systems for indust rial applications at data rates up to 50 kBaud ASK and 32 kBaud FSK modulation scheme. The transmitting frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK systems. Figure 1-1. System Block Diagram Micro- controller PLL UHF ASK/FSK Remote control receiver UHF ASK/FSK Remote control transmitter ATA8403 ATA5760/ ATA5761 LNA VCO PLL XTO LNA VCO Antenna Demod Control 1 to 3 Encoder ATARx9x XTO

1 Li cell

4983B–INDCO–10/08

4983B–INDCO–10/08 ATA8403 2. Pin Configuration Figure 2-1. Pinning TSSOP8L ENABLE VS GND XTAL CLK PA_ENABLE ANT2 ANT1 Table 2-1. Pin Description Pin Symbol Function Configuration 1C L K Clock output signal for microconroller The clock output frequency is set by the crystal to fXTAL/4

2 PA_ENABLE Switches on power amplifier, which is

Emitter of antenna output stage Open collector antenna output 100Ω 100Ω CLK VS 50 kΩ 20 µA UREF = 1.1V PA_ENABLE ANT1 ANT2

4983B–INDCO–10/08 ATA8403 Figure 2-2. Block Diagram

5 XTAL Connection for crystal

6 VS Supply voltage See ESD protection circuitry (see Figure 4-5 on page 9)

7 GND Ground See ESD protection circuitry (see Figure 4-5 on page 9)

8 ENABLE Enable input

Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration 1.5 kΩ 1.2 kΩ 182 µA XTAL VS VS 200 kΩ ENABLE ATA8403 CP Power up/down PDF XTAL VS GND ENABLE ANT1 ANT2 PA_ENABLE CLK f LF PA VCO PLL XTO f

4983B–INDCO–10/08 ATA8403 3. General Description This fully integrated PLL transmit ter allows particularly simple, low-cost RF miniature transmit- ters to be assembled. The VCO is locked to 64 × fXTAL, and therefore a 13.5672 MHz crystal is needed for a 868.3 MHz transmitter and a 14.2969 MHz crystal for a 915 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor toget her with a crystal con- nected in series to GND are needed as external elements. The crystal oscillator together with the PLL typically needs < 1 ms until the PLL is locked and the CLK output is stable. There is a wait time of ≥ 4 ms must be used until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse, which is nearly inde- pendent from the load impedance. The delivered output power is therefore controllable via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A high power efficiency of η=P out/(IS,PA × VS) of 24% for the power amplifier at 868.3 MHz results when an optimized load impedance of ZLoad = (166 + j226)Ω is used at 3V supply voltage. 4. Functional Description If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode, consuming only a very small amount of current, so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL, and the CLK driv er are switched on. If PA_ENABLE remains L, only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller. The VCO locks to 64 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are on. The power amplifier can be switched on and off with PA_ENABLE. This is used to perform the ASK modulation.

4.1 ASK Transmission

The ATA8403 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK signal can be taken to clock the microcontroller, and the output power can be modulated by means of the PA_ENABLE pin. After transmission, PA_ENABLE is switched to L, and the micro- controller switches back to internal clocking. The ATA8403 is switched back to standby mode with ENABLE = L.

4.2 FSK Transmission

The ATA8403 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for F SK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. A fter transmission PA_ENABLE is switched to L and the microcontroller switches back to inte rnal clocking. The ATA8403 is switched back to standby mode with ENABLE = L. The accuracy of the frequency dev iation with XTAL pulling method is about ±25% when the fol- lowing tolerances are considered.

4983B–INDCO–10/08 ATA8403 Figure 4-1. Tolerances of Frequency Modulation Using C4 =9 . 2p F± 2 % , C5 = 6.8 pF ±5%, a switch port with C Switch = 3 pF ±10%, stray capaci- tances on each side of the crystal of C Stray1 =C Stray2 = 1 pF ±10%, a parallel capacitance of the crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, typically results in an FSK devi- ation of ±21.5 kHz with worst case tolerances of ±16.8 kHz to ±28.0 kHz.

4.3 CLK Output

An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF.

4.3.1 Clock Pulse Take-over

The clock of the crystal oscillato r can be used for clocking the mi crocontroller. A special feature of Atmel®’s ATARx9x is that it starts with an integrated RC-oscillator to switch on the ATA8403 with ENABLE = H, and after 4 ms assumes the clock signal of the transmission IC, so that the message can be sent with crystal accuracy.

4.3.2 Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of Z Load,opt = (166 + j226)Ω at 868.3 MHz. There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 7.7 mA. The maximum output power is delivered to a resistive load of 475 Ω if the 0.53 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad =4 7 5Ω || j/(2 × p × f × 0.53 pF) = (166 + j226)Ω thus results in the maximum output power of 5.5 dBm. The load impedance is defined as the impedance seen from the ATA8403’s ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 475Ω where the parallel imag- inary part should be kept constant. Output power measurement can be done with the circuit shown in Figure 4-2 on page 6 . Note that the component values must be changed to compensate for the individual board parasitics until the ATA8403 has the right load impedance Z Load,opt = (166 + j226)Ω at 868.3 MHz. Also the damping of the cable used to measure the output power must be calibrated out. RS LM C4 CM VS XTAL C0 C5 CSwitch CStray1 CStray2

4983B–INDCO–10/08 ATA8403 Figure 4-2. Output Power Measurement

4.4 Application Circuit

A value of 68 nF/X7R is recommended for the supply-voltage blocking capacitor C 3 (see Figure 4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C 1 typically is 3.9 pF/NP0 and C 2 is 1 pF/NP0. For C 2, two capacitors in series should be used to achieve a better tolerance value and to have the possibility of realizing the ZLoad,opt using standard valued capacitors. C1, together with the pins of ATA8403 and the PCB board wires, forms a series resonance loop that suppresses the 1 st harmonic. Therefore, the position of C 1 on the PCB is important. Nor- mally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1. 5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (≈ 50 nH to 100 nH) can be printed on PCB. C 4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Norm ally, a 15 pF load-capacitance crystal results in a value of 12 pF. 1 nF 1.5 pF 2.7 pF 10 nH VS Rin ANT2 ANT1 ZLopt Power meter 50Ω Z = 50Ω

4983B–INDCO–10/08 ATA8403 Figure 4-3. ASK Application Circuit ATARx9x ATA8403 CP Power up/down PDF VDD BPXY VSS VS XTAL XTAL VS VS VS GND ENABLE ANT1 Loop Antenna C2 ANT2 PA_ENABLE OSC1 BPXY BPXY BPXYS1 CLK f LF PA VCO PLL XTO f

4983B–INDCO–10/08 ATA8403 Figure 4-4. FSK Application Circuit ATARx9x ATA8403 CP Power up/down PDF VDD BPXY VSS VS XTAL XTAL VS VS VS GND ENABLE ANT1 Loop Antenna C2 ANT2 PA_ENABLE OSC1 BPXY BPXY BPXYS1 CLK f LF PA VCO PLL XTO f BP42/T2O

4983B–INDCO–10/08 ATA8403 Figure 4-5. ESD Protection Circuit CLK VS GND PA_ENABLE XTALANT2 ENABLE ANT1 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Minimum Maximum Unit Supply voltage V S 5V Power dissipation P tot 100 mW Junction temperature T j 150 °C Storage temperature T stg –55 +85 °C Ambient temperature T amb –55 +85 °C Input voltage V maxPA_ENABLE –0.3 (V S + 0.3)(1) V 6. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 170 K/W 7. Electrical Characteristics VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current Power down, VENABLE < 0.25V, –40°C to 85°C VPA_ENABLE < 0.25V, 25°C (100% correlation tested) IS_Off < 10 350 nA nA Supply current Power up, PA off, VS = 3V, VENABLE >1 . 7 V , VPA_ENABLE <0 . 2 5 V IS 3.6 4.6 mA Power up, VS =3 . 0 , VENABLE >1 . 7 V , VPA_ENABLE >1 . 7 V IS_Transmit 8.5 11 mA Output power VS =3 . 0 V , Tamb = 25°C, f = 868.3 MHz, ZLoad = (166 + j226)Ω PRef 3.5 5.5 8 dBm Note: 1. If V S is higher than 3.6V, the maximum voltage will be reduced to 3.6V.

4983B–INDCO–10/08 ATA8403 Output power variation for the full temperature range Tamb = 25°C, VS = 3.0V VS = 2.0V ΔPRef ΔPRef –1.5 –4.0 dB dB Output power variation for the full temperature range Tamb = 25°C, VS = 3.0V VS = 2.0V, POut = PRef + ΔPRef ΔPRef ΔPRef –2.0 –4.5 dB dB Achievable output-power range Selectable by load impedance P Out_typ –3 +5.5 dBm Spurious emission fCLK = f0/128 Load capacitance at pin CLK = 10 pF f O ±1 × fCLK fO ±4 × fCLK Other spurious are lower –52 –52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/64 fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF , load capacitance selected accordingly T amb = 25°C fXTO fXTAL ppm PLL loop bandwidth 250 kHz Phase noise of phase comparator Referred to fPC = fXT0, 25 kHz distance to carrier –116 –110 dBc/Hz In-loop phase noise PLL 25 kHz distance to carrier –80 –74 dBc/Hz Phase noise VCO At 1 MHz At 36 MHz –89 –120 –86 –117 dBc/Hz dBc/Hz Frequency range of VCO f VCO 868 928 MHz Clock output frequency (CMOS microcontroller compatible) f0/256 MHz Voltage swing at pin CLK C Load ≤ 10 pF V0h V0l VS × 0.8 VS × 0.2 V V Series resonance R of the crystal Rs 110 Ω Capacitive load at pin XT0 7p F FSK modulation frequency rate Duty cycle of the modulation signal = 50% 0 32 kHz ASK modulation frequency rate Duty cycle of the modulation signal = 50% 0 50 kHz ENABLE input Low level input voltage High level input voltage Input current high V Il VIh IIn 1.7 0.25 V V µA PA_ENABLE input Low level input voltage High level input voltage Input current high V Il VIh IIn 1.7 0.25 VS (1) V V µA 7. Electrical Characteristics (Continued) VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Test Conditions Symbol Min. Typ. Max. Unit Note: 1. If V S is higher than 3.6V, the maximum voltage will be reduced to 3.6V.

4983B–INDCO–10/08 ATA8403 9. Package Information 10. Revision History 8. Ordering Information Extended Type Number Package MOQ Remarks ATA8403-6AQY TSSOP8L 5000 pcs Taped and reeled, Pb-free 3±0.1 0.85±0.05 0.1±0.05 specifications according to DIN technical drawings Issue: 2; 15.03.04 Drawing-No.: 6.543-5083.01-4 14 Package: TSSOP 8L Dimensions in mm 0.65 nom. 3 x 0.65 = 1.95 nom. 0.31-0.07 +0.06 0.15 -0.02+0.05 1-0.15 +0.05 3.8±0.3 4.9±0.1 3±0.1 Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4983B-INDCO-10/08 • Put datasheet in the newest template

  • Section 7 “Electrical Characteristics” on page 10 changed

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