ATA6843

ATA6843_14 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 27

Technical content

Features

• Broad operation voltage range from 5.25V to 32V
• Atmel® ATA6843 temperature range TJ = 150°C
• Atmel ATA6844 extended temperature range TJ = 200°C
• Direct driving of six external NMOS transistors with a maximum switching frequency of 50kHz
• Integrated charge pump to provide gate voltages for high-side drivers and to supply the gate of the external battery reverse protection NMOS
• Built-in 5V/3.3V voltage regulator with current limitation
• Reset signal for the microcontroller
• Sleep Mode with supply current of typically < 45µA
• Wake-up via LIN bus or high voltage input
• Programmable window watchdog
• Battery overvoltage protection and battery undervoltage management
• Overtemperature warning and protection (shutdown)
• Jump start compatible
• 200mA peak current for each output driver
• LIN transceiver conformal to LIN 2.1 and SAEJ2602-2 with outstanding EMC and ESD performance
• QFN48 package 7mm × 7mm ATA6843/ATA6844 BLDC Motor Driver and LIN System Basis Chip DATASHEET

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 1. Description The Atmel® ATA6843 and Atmel ATA6844 are system basis chips for three-phase brushless DC motor controllers designed in Atmel’s state-of-the-art 0.8µm SOI technology SMART-I.S.™ 1. In combination with a microcontroller and six discrete power MOSFETs, the system basis chip forms a BLDC motor control unit for automotive applications. In addition, the circuits provide a 3.3V/5V linear regulator and a window watchdog. The circuit includes various control and protection functions like overvoltage and overtemperature protection, short circuit detection, and undervoltage management. Thanks to these function blocks, the driver fulfils a maximum of safety requirements and offers a high integration level to save cost and space in various applications. The target applications are most suitable for the automotive market due to the robust technology and the high qualification level. Atmel ATA6844, in particular, is designed for applications in a high-temperature environment. Figure 1-1. Block Diagram Supervisor: Short Circuit Overtemperature Undervoltage Charge Pump CC Timer WD Timer VBG LIN LIN Hall C Hall B Hall A Hall C Hall B Hall A Atmel ATA6843/44 Oscillator Driver Control VINT Regulator Control Logic VG Regulator LIN VBAT Microcontroller VINT CPHI1 CPHI2 CPLO1 PBAT CPOUT CPLO2 VG VMODE High-side Driver 1 High-side Driver 2 High-side Driver 3VCC Regulator Low-side Driver 3 Low-side Driver 2 Low-side Driver 1 VBAT DG3 /RESET DG2 DG1 WD /IH1-3 SLEEP COAST IL1-3 TX RX VCC LINGND WDEN GND PGND RWD CC SCREF EN

3ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 2. Pin Configuration Figure 2-1. Pinning QFN48 Note: YWW Date code (Y = Year - above 2000, WW = week number) ATA683x Product name ZZZZZ Wafer lot number AL Assembly sub-lot number RWD WDEN SLEEP SCREF LINGND GND NC CC WD /RESET VMODE VINT Atmel YWW ATA6843/ATA6844 ZZZZZ-AL CPLO1 CPHI1 CPLO2 CPHI2 CPOUT DG3 NC PBAT VG PGND VBAT EN /COAST NC VCC TXD /IH3 IL2 /IH2 RXD DG1 DG2 /IH1 IL1 IL3 NC LIN 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 Table 2-1. Pin Description Pin Symbol I/O Function

1 VMODE I Selector for VCC and interface logic voltage level

2 VINT I/O Blocking capacitor

3 RWD I Resistor defining the watchdog interval

4 CC I/O RC combination to adjust cross conduction time

5 /RESET O Reset signal for microcontroller

6 WD I Watchdog trigger signal

7 WDEN I Enable and disable the watchdog

8 SLEEP I Microcontroller output to switch system in Sleep Mode

9 SCREF I Short circuit comparator Reference input

10 NC Connect to GND

11 GND I Ground

12 LINGND I Ground for LIN, Connect to GND

13 LIN I/O LIN-bus terminal

14 NC Connect to GND

15 TXD I Transmit signal to LIN bus from microcontroller

16 IL3 I Control Input for output L3

17 /IH3 I Control Input for output H3

18 IL2 I Control Input for output L2

19 /IH2 I Control Input for output H2

20 IL1 I Control Input for output L1

21 /IH1 I Control Input for output H1

22 RXD O Receive signal from LIN bus for microcontroller

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

23 DG1 O Diagnostic output 1

24 DG2 O Diagnostic output 2

25 DG3 O Diagnostic output 3

26 H3 O Gate voltage high-side 3

27 S3 I/O Voltage at half bridge 3

28 H2 O Gate voltage high-side 2

29 S2 I/O Voltage at half bridge 2

30 H1 O Gate voltage high-side 1

31 S1 I/O Voltage at half bridge 1

32 CPOUT I/O Charge pump output capacitor

33 CPHI2 I Charge pump capacitor 2

34 CPLO2 O Charge pump capacitor 2

35 CPHI1 I Charge pump capacitor 1

36 CPLO1 O Charge pump capacitor 1

37 NC Connect to GND

38 PBAT I Power supply (after reverse protection) for charge pump and

39 VG I/O Blocking capacitor

40 L1 O Gate voltage H-bridge, low-side 1

41 L2 O Gate voltage H-bridge, low-side 2

42 L3 O Gate voltage H-bridge, low-side 3

43 PGND I Power ground for H-bridge and charge pump

44 VCC O 5V/100mA supply for microcontroller

45 NC Connect to GND

46 VBAT I Supply voltage for IC core (after reverse protection)

47 EN I High voltage enable input

48 /COAST I Control input for coast function of bridge Table 2-1. Pin Description Pin Symbol I/O Function

5ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 3. Functional Description

3.1 Power Supply Unit with Supervisor Functions

3.1.1 Power Supply

The IC has to be supplied by a reverse-protected battery voltage. To prevent damage to the IC, proper external protection circuitry has to be added. It is recommended to use at least one capacitor combination of storage and RF capacitors be-hind the reverse protection circuitry, which is connected close to the VBAT and GND pins of the IC. A fully integrated low-power and low-drop regulator (VINT regulator), stabilized by an external blocking capacitor, provides the necessary low-voltage supply needed for the wake-up process. A trimmed low-power band gap is used as reference for the VINT regulator as well as for the VCC regulator. All internal blocks are supplied by VINT regulator. VINT regulator must not be used for any external supply purposes. Nothing inside the IC except the logic interface to the external microcontroller is supplied by the 5V/3.3V VCC regulator. Both voltage regulators are checked by a “power-good comparator”, which keeps the whole chip in reset as long as the internal supply voltage (VINT regulator output) is too low and gnerates a reset for the external microcontroller if the out-put voltage of the VCC regulator is not sufficient.

3.1.2 Voltage Supervisor

This function is implemented to protect the IC and the external power MOS transistors from damage due to overvoltage on PBAT input. In the event of overvoltage (VTHOV) or undervoltage (VTHUV), the external NMOS motor driver transistors will be switched off. The failure state will be flagged on DG2 pin. It is recommended to block PBAT with an external RF capacitor to suppress high frequency disturbances.

3.1.3 Temperature Supervisor

An integrated temperature sensor prevents the IC from overheating. If the temperature is above the overtemperature prewarning threshold TJPW set, the diagnostic pin DG3 will be switched to HIGH to signal this event to the external microcontroller. The microcontroller should take actions to reduce the power dissipation in the IC. If the temperature rises above the overtemperature shutdown threshold TJ switch off, the VCC regulator and all output drivers together with the LIN transceiver will be switched OFF immediately and the /RESET signal will go LOW. Both thresholds have a built-in hysteresis to avoid oscillations. The IC will return to normal operation (Active Mode) when it has cooled down below the shutdown threshold. When the junction temperature drops below the pre-warning threshold, bit DG3 will be switched LOW.

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

3.2 Active Mode and Sleep Mode

The IC has two modes: Active Mode and Sleep Mode. By default the IC starts in Active Mode (normal operation) after power- on. An Enter Sleep Mode procedure switches the IC from Active Mode to Sleep Mode (standby). Enter Active Mode procedures wake up the IC back from Sleep Mode. When in Sleep Mode the internal 5V supply (VINT regulator), the EN input pin, and a small part of the LIN receiver remain active to ensure a proper startup of the system. The VCC regulator is turned off. The Enter Sleep Mode and Enter Active Mode procedures are implemented as follows: Enter Sleep Mode: Pin SLEEP is a low-voltage input supplied by the VCC regulator. It is ESD protected by diodes against VCC and GND. Thus the input voltage at pin SLEEP must not go below GND or exceed the output voltage of the VCC regulator. A transition from HIGH to LOW followed by a permanent LOW signal for a minimum time period t gotosleep (typical 10µs) at pin SLEEP switches the IC to Sleep Mode as the SLEEP is edge triggered. VCC is switched off in Sleep Mode. It is recommended to keep SLEEP LOW during normal operation. Enter Active Mode Using Pin EN: Pin EN is a high-voltage input for external wake-up signals. Its input structure consists of a comparator with a built-in hysteresis. It is ESD-protected by diodes against GND and VBAT, and for this reason the applied input voltage must not go below GND or exceed VBAT. Pulling EN up to VBAT switches the IC to Active Mode. EN is debounced and edge triggered. Enter Active Mode Using the LIN Interface: Using the LIN interface provides a second possibility to wake-up the IC (see Figure 3-1). A voltage lower than the LIN pre- wake detection V LINL at pin LIN activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at pin LIN followed by a dominant bus level VBUSdom maintained for a minimum time period (Tbus) and ending with a rising edge leads to a remote wake-up request. The device switches from Sleep Mode to Active Mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. Figure 3-1. Wake-up Using the LIN Interface In Sleep Mode the device has a very low current consumption even during short circuits or floating conditions on the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., it is switched off when the LIN-Master is in Sleep Mode or even if the power supply of the Master node is switched off. In order to minimize the current consumption IVBAT during voltage levels at the LIN-pin below the LIN pre-wake threshold, the receiver is activated only for a specific time tmon. If tmon elapses while the voltage at the bus is lower than Pre-wake detection low (VLINL) and higher than the LIN dominant level, the receiver is switched off again and the circuit changes back to sleep mode. The current consumption is then the result of IVBAT plus ILINwake. If a dominant state is reached on the bus no wake-up will occur. Even if the voltage rises above the Pre-wake detection high (VLINH), the IC will stay in sleep mode (see Figure 3-2). This means the LIN-bus must be above the Pre-wake detection threshold VLINH for a few microseconds before a new LIN wake-up is possible. Sleep Mode LIN VCC SLEEP Active ModeActive Mode Tbus = 90µs Regulator Wake-up Time = 4 x T OSCTgotosleep = 10µs Tdebounce

9ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

3.4 Reset and Watchdog Management

The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time TOSC is determined by the external resistor RWD. A HIGH signal on WDEN pin enables the watchdog function; a LOW signal disables it. Since the WDEN pin is equipped with an internal pull-up resistor the watchdog is enabled by default. In order to keep the current consumption as low as possible the watchdog is switched off during Sleep Mode. The timing diagram in Figure 3-6 shows the watchdog and external reset timing. Figure 3-6. Timing Di agram of the Watchdog in Conjunction with the /RESET Signal After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET output stays LOW for the timeout period tres (typical 10ms). Subsequently /RESET output switches to HIGH. During the following time td (typical 500ms) a rising edge at the input WD is expected otherwise another external reset will be triggered. When the watchdog has been correctly triggered for the first time, normal watchdog operation begins. A normal watchdog cycle consists of two time sections t1 and t2 followed by a short pulse for the time tresshort at /RESET if no valid trigger has been applied at pin WD during t2. Rising edges on WD pin during t1 also cause a short pulse on /RESET. Start for such a cycle is always the time of the last rising edge either on WD pin or on /RESET pin. If the watchdog is disabled (WDEN = LOW), only the initial reset for the time tres after power-up will be generated. Additional resets will be generated if the VCC output voltage drops below 80% of its nominal value. The following example demonstrates how to calculate the timing scheme for valid watchdog trigger pulses, which the external microcontroller has to provide in order to prevent undesired resets. Example: Using an external resistor RWD =3 3 kΩ ±1% results in typical parameters as follows: TOSC = 12.4µs t1 = 980 × TOSC = 12.1ms ±10% t2 = 780 × TOSC = 9.6ms ±10% t1 + t2 = 21.7ms ±10% Hence, the minimum time the external microcontroller has to wait before pin WD can be triggered is in worst case watchdog trigger input must remain within tmax –t min =6 . 2 m s . Watchdog trigger edge Reset and lead time, no trigger Watchdog cycle, no trigger Watchdog cycle, trigger during t2 window Reset and lead time, trigger during lead time tresshort t1 t2t1 tdtres td t1tres Watchdog trigger in t2 window 88% VCC VCC WD /RESET

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 Other values can be set up by picki ng a different resistor value for R WD. The dependency of T OSC on the value of R WD is shown in Figure 3-7. Figure 3-7. T OSC versus RWD The tolerance of TOSC is ±10% for resistors RWD with maximum ±1% in tolerance.

3.5 Charge Pump

A charge pump has been implemented in order to provide sufficient voltage to operate the external high-side power-NMOS transistors and the VG regulator, which drives the low-side Power-NMOS transistors. The charge pump output voltage at CPOUT pin is controlled to settle typically about 15V above the voltage at pin PBAT. A built-in supervisor circuit checks if the output voltage is sufficient to operate the VG regulator and external Power-NMOS transistors. The output voltage is accepted as good when it rises above VCPCPGOOD. A charge pump failure is flagged at DG2 if this minimum can not be reached or if the output voltage drops below the lower threshold of VCPCPGOOD due to overloading. The two shuffle capacitors should have the same value. The value of the reservoir capacitor should be at least twice the value of one shuffle capacitor. Two external shuffle capacitors and an external reservoir capacitor have to be provided. The typical value for the two shuffle capacitors is 100nF, and for the reservoir capacitor is 1.5µF. All capacitors should be ceramic. The greater the capacitors are, the greater the output current capability.

3.6 VG Regulator

The VG regulator provides a stable voltage to supply the low-side gate drivers and to deliver sufficient voltage for the external low-side Power-NMOS transistors. Typically the output voltage is 12V. In order to guarantee reliable operation even with a low battery voltage, the VG regulator is supplied by the charge pump output. For stability, an external ceramic capacitor of typically 470nF has to be provided. There is no internal supervision of the VG output voltage.

3.7 Output Drivers and Control Inputs IL1-IL3, /IH1-/IH3 and /COAST

This IC offers six push-pull output drivers for the external low-side and high-side power-NMOS transistors. To guarantee reliable operation, the low-side drivers are supplied by the VG regulator while the high-side drivers are supplied directly by the charge pump. All drivers are designed to operate at switching frequencies in the range of DC up to 50kHz. The maximum gate charge that can be delivered to each external Power-NMOS transistor at 50kHz is 100nC. The output drivers L1 to L3 and H1 to H3 are directly controlled by the digital input pins IL1 to IL3 and /IH1 to /IH3 (see Table 3-1 on page 11). IL1 to IL3 are high active digital inputs equipped with an internal pull-down resistor, while /IH1 to /IH3 are low active digital inputs equipped with an internal pull-up resistor. The pin /COAST is a low active input with internal pull-up resistor, which forces low all output drivers L1-L3 and H1-H3, and turns off all external FETs. As a safety function, /COAST allows to emergency switch off all output drivers to coast a BLDC motor. 10 20 40 30 60 90 807050 100 TOSC (μs) TOSCmax (µs) TOSCmin (µs) TOSC (µs) RWD (kΩ)

11ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 To operate the output drivers properly the following requirements have to be fulfilled: 1. Device is in Active Mode. 2. In case of watchdog is enabled, at leas t one valid watchdog trigger has been accepted. 3. The voltage at pin PBAT lies within its operation ra nge. Neither undervoltage nor overvoltage is present. 4. The charge pump output voltage has been accepted as good, thus it exceeded VCPCPGOOD. 5. No overtemperature shutdown has occurred. 6. /COAST is high If a short circuit is detected by one of the sense inputs S1 to S3, the output drivers will be switched off after a blanking time tSC of typically 6 µs and the output DG1 will be flagged (see also Section 3.8 “Short Circuit Detection and Short Circuit Comparator Reference Input” on page 11). The output drivers will be enabled again and DG1 will be cleared with a rising edge at one of the control inputs IL1 to IL3, or falling edge at one of the control inputs /IH1 to /IH3. Additional logic prevents short circuits due to switching on one power-NMOS transistor while the opposite one in the same branch is switched on already.

3.8 Short Circuit Detection and Short Circuit Comparator Reference Input

Short circuits in the motor bridge circuitry are sensed by S1 to S3 inputs. Internal comparators monitor the voltage differences between the drain and the source terminals of the external power-NMOS transistors and compare it to voltage VSCREF applied at pin SCREF. If one transistor switches on and its drain-source voltage exceeds VSCREF threshold after a blanking time tSC (see Figure 3-8 on page 12), a short circuit in this branch will be detected. In this case, the short-circuit detected output will be switched off immediately and pin DG1 will be set to HIGH. With a rising edge at any of the pins IL1 to IL3 or a falling edge at any of the pins /IH1 to /IH3, the diagnostic output DG1will be reset and the drivers switched on again. Note, valid voltage range for short-circuit reference is 0.5V≤ VSCREF ≤ 3.3V. Voltages outside this range will lead to incorrect short circuit thresholds. If pin SCREF is floating VSCREF will be set to approximately 2.5V by an integrated resistive voltage divider.

3.9 Cross Conduction Timer

In order to prevent damage of the motor bridge due to peak currents a non-overlapping phase for switching the power- NMOS transistors is mandatory. Therefore, a cross conduction timer has been implemented to prevent switching on any output driver for a time tCC after any other driver has been switched off. This also accounts for toggling any other driver after a short circuit was detected. An external RC parallel combination defines the value for tCC and can be estimated as follows: tCC = KCC × RCC (kΩ) × CCC (nF), KCC is specified in Section 8. “Electrical Characteristics” on page 16. The RC combination is connected between CC and GND pins. When one of the drivers has been switched off the RC combination is charged to 5V (VINT) and discharged with its time constant. Any low to high transition at IL1 to IL3 or any high to low transition at /IH1 to IH3 will be masked out at the driver outputs until the voltage at CC pin drops below 67% of its initial value (VINT). The timer will be re-triggered at any time by any falling edge at the control inputs. This is shown in the following figure. Table 3-1. Status of the Output Drivers Depending on the Control Inputs Mode Control Inputs IL(1..3) Control Inputs /IH(1..3) /COAST Driver Stage for External Power MOS L(1..3), H(1..3) Comments Sleep X X X OFF Sleep Mode Active X X 0 OFF Coast function active Active 0 1 1 OFF Active 1 1 1 L(1..3) ON, H(1..3) OFF Active 0 0 1 L(1..3) OFF, H(1..3) ON Active 1 0 1 OFF Shoot-through protection

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 Figure 3-8. Interaction of Short Circuit Detection and Cross Conduction Timer At least 5kΩ minimum and 5nF at maximum should be used as values for the RC combination. 10kΩ is recommended. If the non-overlapping phase is controlled by the external microcontroller, it is possible to do without the external capacitor. The minimum time tCC is defined by the parasitic capacitance at CC pin.

3.10 Diagnostic Outputs DG1 - DG3

As mentioned in the sections above, the diagnostic outputs DG1 to DG3 are used to signal failures. This is summarized in the following table. Note: This is only valid for VCC > V tHRESHLow. Otherwise all diagnostic outputs will be tristated. In order to differentiate between LIN and EN wake-up, DG1 output will be set to LOW or HIGH respectively. LOW indicates wake-up by LIN, HIGH indicates wake-up by EN. DG1 output will be cleared by the first valid watchdog trigger after wake-up or by the first rising edge at IL1 to IL3 if the watchdog is disabled or by the first falling edge at /IH1 to /IH3if the watchdog is disabled. tcc tcc tcc /IH1 IL3 CC IL1 VCC = 67% VVINT VCC = VVINT Ignore VS1 for tSC = 6µs Shut off if VS1 > 4V Ignore VPBAT - VS1 for tSC = 6µs Shut off if VPBAT - VS1 > 4V Ignore VS3 for tSC = 6µs Shut off if VS3 > 4V Table 3-2. Status of the Diagnostic Outputs (Normal Operation) Device Status Diagnostic Outputs CommentsCPOK OT1 OV UV SC DG1 DG2 DG3

0 X X X X – 1 – Charge pump failure

X 1 X X X – – 1 Overtemperature prewarning X X 1 X X – 1 – Overvoltage X X X 1 X – 1 – Undervoltage X X X X 1 1 – – Short circuit Note: X represents: no effect) OT1: overtemperature warning OV: overvoltage of PBAT UV: undervoltage of PBAT SC: short circuit CPOK: charge pump OK

13ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

3.11 LIN Transceiver

Atmel® ATA6843 and Atmel ATA6844 include a fully integrated LIN transceiver complying with LIN specification 2.1 and SAEJ2602 2. The transceiver consists of a low-side driver with slew rate control, wave shaping, current limiting, and a high voltage comparator followed by a debouncing unit in the receiver. During transmission, the data applied at pin TXD will be transferred to the bus driver to generate a bus signal on LIN pin. TXD input has an internal pull-up resistor. To minimize the electromagnetic emission of the bus line, the bus driver has a built-in slew rate control and wave-shaping unit. The transmission will be aborted by a thermal shutdown or by a transition to Sleep Mode. Figure 3-9. Definition of Bus Timing Parameters The recessive BUS level is generated from the integrated 30kΩ pull-up resistor in series with an active diode. This diode protects against reverse currents on the bus line in case of a voltage difference between the bus line and VSUP (VBUS >V SUP). No additional termination resistor is necessary to use the IC as a LIN slave. If this IC is used as a LIN master, the LIN pin is terminated by an external 1 kΩ resistor in series with a diode to VBAT. As PWM communication directly over the LIN transceiver in both directions is possible, there is no TXD timeout feature implemented in the LIN transceiver. Table 3-3. Indicating Wake-up Source Diagnostic Outputs Wake-up SourceDG1 DG2 DG3 1 – – EN 0 – – LIN TXD (Input to transmitting node) VS (Transceiver supply of transmitting node) RXD (Output of receiving node1) RXD (Output of receiving node2) LIN Bus Signal Thresholds of receiving node1 Thresholds of receiving node2 tBus_rec(max) trx_pdr(1) trx_pdf(2)trx_pdr(2) trx_pdf(1) tBus_dom(min) tBus_dom(max) THRec(max) THDom(max) THRec(min) THDom(min) tBus_rec(min) tBit tBittBit

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to pin GND. (xxx) Values for the Atmel® ATA6844. Parameters Pin Symbol Min. Max. Unit Input voltage PGND VPGND –0.3 +0.3 V Negative input current VBAT IVBAT –15 mA Negative input current PBAT IPBAT –20 mA Supply voltage VBAT VVBAT +40 V Supply voltage PBAT VPBAT +40 V Logic output voltage /RESET, DG1, DG2, DG3, RXD V/RESET, VDG1, VDG2, VDG3, VRXD –0.3 VVCC + 0.3 V Logic input voltage IL1-3, /IH1-3, WD, WDD, SLEEP, TXD VIL1-3, V/IH1-3, VWD, VSLEEP, VTXD –0.3 VVCC + 0.3 V Output voltage VINT, VCC VINT, VVVCC –0.3 +5.5 V Analog input voltage RWD, CC, SCREF VRWD , VCC, VSCREF –0.3 VVCC + 0.3 V Digital input voltage EN VEN –0.3 VVBAT + 0.3 V Digital input voltage VMODE VVMODE –0.3 VVINT + 0.3 V Output voltage VG VVG +16 V Input voltage LIN VVLIN –27 VVBAT + 2 V Output voltage S1, S2, S3 VS1, VS2, VS3 (–6) +40 V Output voltage L1, L2, L3 VL1, VL2, VL3 VPGND – 0.3 VVG + 0.3 V Output voltage H1, H2, L3 VH1, VH2, VH3 VS1, 2, 3 – 1 VS1, 2, 3 + 16 V Charge pump CPLO1, 2 VCPLO1, VCPLO2 VPBAT + 0.3 V Charge pump CPHI1, 2 VCPHI1, VCPHI2 VCPOUT + 0.3 V Output voltage CPOUT VCPOUT +52 V Storage temperature TStorage –55 +150 °C Reverse current CPLOx, CPHIx, VG, CPOUT, Sx ICPLOx_R, ICPHIx_R, IVG_R, ICPOUT_R, ISx_R –2 mA Lx, Hx ILx_R, IHx_R –1 mA Note: Estimated values take T J > 150°C into account. 5. Thermal Resistance Parameters Symbol Value Unit Thermal resistance junction to heat slug Rthjc <5 K/W Thermal resistance junction to ambient when heat slug is soldered to PCB Rthja 25 K/W

15ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 Static latch-up tested according to AEC-Q100-004 and JESD78.

• 3 to 6 samples, 0 failures
• Electrical post-stress testing at room temperature In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when not able to drive the specified current. 6. Operating Range The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. (xxx) Values for the Atmel® ATA6844 Parameters Symbol Min Max Unit Operating supply voltage(1) VVBAT 5.5 VTHOV V Operating supply voltage(2) VVBAT 4.3 5.5 V Operating supply voltage(3) VVBAT VTHOV 40 V Ambient temperature range TA –40 +150 °C Junction temperature range TJ –40 +150 (200) °C Notes: 1. Full functionality 2. Output drivers are switched off, extended range for parameters for voltage regulators 3. Output drivers and char ge pump are switched off 7. Noise and Surge Imm unity, ESD and Latch-up Parameters Standard and Test Conditions Value Conducted interferences ISO 7637-1 Level 4(1) Conducted disturbances CISP25 Level 5 ESD according to IBEE LIN EMC - Pins LIN, PBAT, VBAT - Pin EN (33kΩ serial resistor) Test specification 1.0 following IEC 61000-4-2 ±6kV ±5kV ESD HBM with 1.5kΩ/100pF ESD- STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ±2kV ESD HBM with 1.5kΩ/100pF Pins EN, LIN, PBAT, VBAT against GND ESD- STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ±8kV ESD CDM (field induced method) ESD STM5.3.1 - 1999 ±500V Note: 1. Test pulse 5: V bat max = 40V

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 8. Electrical Characteristics All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Power Supply and Supervisor Functions

1.1 Current consumption

VVBAT = 13.5V(1) 46 IVBAT 7 mA A

1.3 Current consumption

VVBAT in Standby Mode VVBAT = 13.5V 46 IVBAT 65 µA A

1.4 Current consumption

V PBAT in Standby Mode VPBAT = 13.5V 38 IVPBAT 9.0 20.0 µA A 1.5 Internal power supply VVBAT > 7V 2 VVINT 4.7 5.0 5.3 V A

1.6 Overvoltage lock-out

38 VTHOVLO 32.0 34.0 V A 1.7 Overvoltage hysteresis 38 VTOVhys 1.5 2.5 V A

1.8 Undervoltage lock-out

38 VTHUVRC 4.75 5.25 V A

1.9 Undervoltage threshold

hysteresis 38 VTUVhys 0.2 0.4 V A

1.11 Thermal prewarning set TJPW set

(170) 145 (195) 170 (220) °C B

1.12 Thermal prewarning reset TJPW reset

(155) 130 (180) 155 (205) °C B

1.13 Thermal prewarning

hysteresis ΔTJPW 15 °C B

1.14 Thermal shutdown off TJ switch off

(200) 175 (225) 200 (250) °C B

1.15 Thermal shutdown on TJ switch on

(185) 160 (210) 185 (235) °C B

1.16 Thermal shutdown

hysteresis ΔTJ switch off 15 °C B

1.17 Ratio thermal shutdown

off/thermal prewarning set TJ switch off/ TJPW set 1.05 1.15 B 1.18 Ratio thermal shutdown on/thermal prewarning reset TJ switch on/ TJPW reset 1.05 1.15 B 2 5V/3.3V Regulator

2.1 Regulated output voltage

VMODE =V INT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT <4 0 V ILoad = 0 to 100mA

44 VVCC

4.85 3.20 5.15 3.40 V A

2.2 Regulated output voltage

VMODE =V INT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT <4 0 V ILoad =0t o8 0 m A 150°C < TJ <2 0 0 ° C 4.85 3.20 5.15 3.40 V A

2.3 Regulated output voltage

VMODE =V INT, 5.5V < VBAT <7 V VMODE = GND, 5V < VBAT <5 . 5 V ILoad =0t o6 0 m A 4.50 2.97 5.15 3.40 V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

17ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

2.4 Regulated output voltage

VMODE =V INT, 5.5V < VBAT <7 V VMODE = GND, 5V < VBAT <5 . 5 V ILoad =0t o5 0 m A 150°C < TJ <2 0 0 ° C 4.50 2.97 5.15 3.40 V A

2.5 Line regulation

VMODE =V INT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT <4 0 V ILoad = 50mA, –40°C < TJ <1 5 0 ° C 50 mV A

2.6 Load regulation

VMODE =V INT, VBAT >7 V VMODE = GND, VBAT >5 . 5 V ILoad = 0 to 100mA ILoad =0t o8 0 m A , 150°C < TJ <2 0 0 ° C mV A

2.7 Output current limit

VMODE =V INT, VBAT >7 V VMODE = GND, VBAT >5 . 5 V ILoad at RESET

44 IOS1

2.8 Output current limit

VMODE =V INT, VBAT >7 V VMODE = GND, VBAT >5 . 5 V ILoad at RESET, 150°C < TJ <2 0 0 ° C 2.12 HIGH threshold VMODE 1 VVMODE H 4.0 V A 2.13 LOW threshold VMODE 1 VVMODE L 0.7 V A

3 Reset and Watchdog

3.1 VCC threshold voltage level

VMODE = VINT (VMODE = GND)

5 VtHRESHLow

3.8 2.5 4.2 2.8 V A B

3.2 Hysteresis VMODE = VINT

(VMODE = GND) 5 HYSRESth 0.2 0.13 0.6 0.4 V A B

3.3 Length of pulse at /RESET 5 tres 8 12 ms A

3.4 Length of short pulse at

/RESET 5 tresshort 1.6 2.4 ms A

3.5 Wait for the first WD trigger 5 td 400 600 ms A

3.6 Time for VCC < VtHRESL

before activating /RESET 5 tdelayRESL 2 µs C 3.8 Watchdog oscillator period RRWD = 33kΩ ±1% (5) TOSC 11.09 13.55 µs A

3.12 Close window (5) t1 980 ×

A

3.13 Open window (5) t2 780 ×

A

3.14 Output low-level at pin

/RESET IOLRES = 1mA 5 VOLRES 0.4 V A

3.15 Internal pull-up resistor at

pin /RESET 5 RPURES 5 10 15 kΩ D 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

4 LIN Transceiver

4.1 Low-level output current Normal mode;

VLIN =0 V , VRXD =0 . 4 V 22 ILRXD 2 mA D

4.2 High-level output current Normal mode; VLIN =V BAT

VRXD =V CC –0 . 4 V 22 IHRXD –2 mA D

4.3 Driver recessive output

VTXD =V CC; ILIN =0 m A 13 VBUSrec 0.9 × VBAT V A

4.4 Driver dominant voltage

VBUSdom_DRV_LoSUP VVBAT = 7.3V Rload = 500Ω 13 V_LoSUP 1.2 V A

4.5 Driver dominant voltage

VBUSdom_DRV_HiSUP VVBAT = 18V Rload = 500Ω 13 V_HiSUP 2 V A

4.6 Driver dominant voltage

VBUSdom_DRV_LoSUP VVBAT = 7.3V Rload = 1000Ω 13 V_LoSUP_1k 0.6 V A

4.7 Driver dominant voltage

VBUSdom_DRV_HiSUP VVBAT = 18V Rload = 1000Ω 13 V_HiSUP_1k_ 0.8 V A

4.8 Pull up resistor to VS Serial diode required 13 RLIN 20 47 kΩ A

4.9 Current limitation VBUS = VBAT_max 13 IBUS_LIM 50 200 mA A

4.10 Input leakage current at the receiver including pull- up resistor as specified Input leakage current driver off V BUS = 0V VBAT = 12V

13 IBUS_PAS_dom –1 mA A

4.11 Leakage current LIN

8V < V BAT < 18V 8V < VBUS < 18V VBUS = VBAT

13 IBUS_PAS_rec 20 µA A

4.12 Leakage current at ground loss Control unit disconnected from ground Loss of local ground must not affect communication in the residual network GNDDevice = VS VBAT = 12V 0V < VBUS < 18V

13 IBUS_NO_gnd –1 +1 mA A

4.13 Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition VBAT disconnected VSUP_Device = GND 0V < VBUS < 18V

13 IBUS 100 µA A

4.14 Center of receiver

VBUS_CNT = (Vth_dom +V th_rec)/2 13 VBUS_CNT 0.475 × VVBAT 0.5 × VVBAT 0.525 × VVBAT V A

4.15 Receiver dominant state VEN = 5V 13 VBUSdom

0.4 × VVBAT V A

4.16 Receiver recessive state VEN = 5V 13 VBUSrec

0.6 × VVBAT V A

4.17 Receiver input hysteresis VHYS = Vth_rec – Vth_dom 13 VBUShys

0.175 × VVBAT V A 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

19ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

4.18 Duty cycle 1

7V < VVBAT < 18V THrec(max) =0 . 7 4 4× VVBAT THDom(max) = 0.581 × VVBAT tBit = 50µs D1 = tBus_rec(min)/(2 × tBit) Load1: 1nF + 1kΩ Load2: 10nF + 500Ω 13 D1 0.396 A

4.19 Duty cycle 2

7V < VVBAT < 18V THrec(min) =0 . 4 2 2× VVBAT THDom(min) = 0.284 × VVBAT tBit = 50µs D2 = tBus_rec(max)/(2×tBit) Load1: 1nF + 1kΩ Load2: 10nF + 500Ω 13 D2 0.581 A

4.20 Duty cycle 3

7V < VVBAT < 18V THrec(max) =0 . 7 7 8× VVBAT THDom(max) = 0.616 × VVBAT tBit = 96µs D3 = tBus_rec(min)/(2 × tBit) Load1: 1nF + 1kΩ Load2: 10nF + 500Ω 13 D3 0.417 A

4.21 Duty cycle 4

7V < VVBAT < 18V THrec(max) =0 . 3 8 9× VVBAT THDom(max) = 0.251 × VVBAT tBit = 96µs D4 = tBus_rec(min)/(2 × tBit) Load1: 1nF + 1kΩ Load2: 10nF + 500Ω 13 D4 0.590 A

4.22 Receiver propagation

7V < VVBAT < 18V trec_pd = max(trx_pdr, trx_pdf) 22 trx_pd 6 µs A 4.23 Symmetry of receiver propagation delay rising edge minus falling edge 7V < VVBAT < 18V trx_sym = trx_pdr – trx_pdf 22 trx_sym –2 +2 µs A

4.24 Dominant time for wake-up

VLIN = 0V 13 TBUS 30 90 150 µs A

4.25 Monitoring time for wake-

up over LIN Bus 13 Tmon 6 10 15 ms B

4.26 Pre-wake detection LIN

Switches the LIN receiver on 13 VLINL –27 VVBAT –

3.3 V A

4.27 Pre-wake detection LIN

High-Level Input Voltage 13 VLINH VVBAT – VVBAT +

0.3 V A

4.28 LIN Pre-Wake pull-up

VVBAT < 27V VLIN = 0V 13 ILINWake –30 –10 µA A

4.29 Capacitance on LIN Pin to

13 CLIN 10 pF D

1. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

5 Control Inputs WD, WDEN, SLEEP , TXD, IL1-3, /IH1-3, /COAST

5.1 Input low-level threshold 6-8, 15-

21, 48 VIL 0.3 × VVCC V A

5.2 Input high-level threshold 6-8, 15-

21, 48 VIH 0.7 × VVCC V A

5.3 Hysteresis 6-8, 15-

21, 48 HYS 0.3 C

5.4 Pull-down resistor WD, SLEEP, IL1-3 6, 8, 16,

18, 20 RPD 25 50 100 kΩ A

5.5 Pull-up resistor WDEN, TXD, /IH1-3, /COAST

7, 15, 17, 19, 21, 48 RPU 25 50 100 kΩ A

5.7 Debounce time SLEEP 8 tgotosleep 9 10 11 µs A

6 Charge Pump

6.1 Charge pump voltage

VVBAT > 7V ILoadCPOUT = 0A ILoadVG = 0A CCP1,2 = 47nF CCPOUT = 220nF

32 VCPOUT

+ 11V VVBAT + 18 V A

6.2 Charge pump voltage

VVBAT > 7V ILoadCPOUT = 7.5mA, ILoadVG = 0A CCP1,2 = 47nF CCPOUT = 220nF +10V V A

6.3 Period charge pump

TCP 2.5 µs B

6.4 Charge pump output

voltage for active drivers 32 VCPCPGOOD 5.25 8.0 V A

7 VG Regulator

7.1 VG Regulator Output

VBAT = 13.5V VCPOUT = 20V ILoadVG = 7.5mA 39 VVG 11 12.5 14 V A

7.2 VG Regulator Line

VBAT = 13.5V VCPOUT1 = 20V, VCPOUT2 = 35V ILoadVG = 7.5mA 39 ΔVVG_Line 100 mV A

7.3 VG Regulator Load

VBAT = 13.5V VCPOUT = 25V ILoadVG1 =1 m A , ILoadVG2 =6 0 m A 39 ΔVVG_Load 100 mV A

8 H-bridge Driver

8.1 Low-side driver HIGH

output voltage 40-42 VLxH VVG V D

8.2 ON-resistance of sink

ILX = 100mA 40-42 RDSON_LxL 20 Ω A

8.3 ON-resistance of source

stage of pins Lx ILX = 100mA 40-42 RDSON_LxH 20 Ω A 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

21ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14

8.6 Sink resistance between

43 RLxsink 45 75 115 kΩ A

8.7 ON-resistance of sink

stage of pins Hx VSx = 0V 26, 28,

30 RDSON_HxL 20 Ω A

8.8 ON-resistance of source

VSx = VVBAT IHx = 100mA 26, 28,

30 RDSON_HxH 20 Ω A

8.13 Output voltage low level

VSx = 0V IHx = 1mA 26, 28, 30 VHxL 0.3 V A

8.14 Output voltage high level

pins Hx IHx = –100µA 26, 28,

30 VHxHstat

– 1V VVCPOUT V A

8.15 Sink resistance between

26-31 RHxsink 45 75 115 kΩ A

8.16 Sink resistance between

27, 29, 31, 38 RSxsink 1 MΩ D Dynamic Parameters 8.17 Propagation delay time, low-side driver from high to low 40-42 tLxHL 0.9 µs A 8.18 Propagation delay time, low-side driver from low to high 40-42 tLxLH 0.9 µs A 8.19 Fall time low-side driver VVBAT = 13.5V CGx = 5nF 40-42 tLxf 0.3 µs A 8.20 Rise time low-side driver VVBAT = 13.5V CGx = 5nF 40-42 tLxr 0.3 µs A 8.21 Propagation delay time, high-side driver from high to low 26, 28, 30 tHxHL 0.9 µs A 8.22 Propagation delay time, high-side driver from low to high 26, 28, 30 tHxLH 0.9 µs A 8.23 Fall time high-side driver VVBAT = 13.5V, CGx = 5nF 26, 28, 30 tHxf 0.3 µs A 8.24 Rise time high-side driver VVBAT = 13.5V, CGx = 5nF 26, 28, 30 tHxr 0.3 µs A

8.25 Valid Short circuit

detection voltage range 9 VSCREF 0.5 3.3 V A

8.26 Accuracy Short circuit

0.5V ≤≤ VSCREF ≤≤ 3.3V 9, 27, 29, 31 VSCREF –10 +10 % A

8.27 Default Short Circuit

detection voltage 9 VSCREF_DEF 2.5 V C

8.28 Internal resistor to GND 9 RiGND 80 100 120 kΩ A

8.29 Internal resistor to VBAT 9 RiVBAT 80 100 120 kΩ A

1. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 8.30 Short circuit blanking time tSC 5.4 6 6.6 µs A Cross Conduction Timer

8.31 Cross conduction time

constant KCC 0.345 0.405 0.465 B

9 Input EN

9.1 Input low level threshold 47 VIL 2.3 3.6 V A 9.2 Input high level threshold 47 VIH 2.8 4.0 V A 9.3 Hysteresis 47 HYS 0.47 V C

9.4 Pull-down resistor 47 RPD 50 100 200 kΩ A

9.5 Debounce time 47 tdb 10 20 25 µs A

10 Diagnostic Outputs DG1, DG2, DG3

10.1 Low level output current VDG = 0.4V 23-25 IL 2 mA A 10.2 High level output current VDG = VCC – 0.4V 23-25 IH –2 mA A 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

23ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 9. Application This section describes the principal application for which the Atmel® ATA6843/ATA6844 was designed. Figure 9-1. Typical Application Supervisor: Short Circuit Overtemperature Undervoltage Charge Pump CC Timer WD Timer VBG LIN KL 15 LIN DAC Hall C Hall B Hall A Atmel ATA6843/44 Oscillator Driver Control VINT Regulator Control Logic VG Regulator LIN VBAT Microcontroller VINT CPHI1 CPHI2 CPLO1 PBAT CPOUT CPLO2 VG VMODE High-side Driver 1 High-side Driver 2 High-side Driver 3 CCP1 CCPOUT CVINT CVCC CVG RWD CCP2 CPBAT CVBAT VCC Regulator Low-side Driver 3 Low-side Driver 2 Low-side Driver 1 Battery DG3 /RESET DG2 DG1 WD /IH1-3 SLEEP COAST IL1-3 TX RX VCC LINGND WDEN GND PGND RWD CC SCREF RCC CCC VCC ADC EN

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 Table 9-1. Typical Ex ternal Components Component Function Min. Typical Max. CVINT Blocking capacitor at VINT 100nF 220nF/10V 470nF CVCC Blocking capacitor at VCC 1.5µF 10µF ESL (CVCC) Serial inductance to CVCC including PCB 1nH 20nH ESR (CVCC) Serial resistance to CVCC including PCB 2Ω 15Ω CVG Blocking capacitor at VG 220nF 470nF, 25V 1µF CCP1 Charge pump shuffle capacitor 47nF 100nF/25V 220nF CCP2 Charge pump shuffle capacitor 47nF 100nF/25V 220nF CCPOUT Charge pump reservoir capacitor 470nF 15 × CCPx/25V 3.3µF RRWD Resistor defining internal bias currents for watchdog oscillator 10kΩ 33 kΩ 91kΩ RCC Cross conduction time definition resistor 5kΩ 10kΩ CCC Cross conduction time definition capacitor 330pF 5nF CVBAT Blocking capacitor VBAT 100nF CPBAT Blocking capacitor PBAT 100nF

25ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 11. Package Information 10. Ordering Information Extended Type Number Package Remarks ATA6843-PLQW QFN48 - ATA6844-PLQW QFN48 - Package Drawing Contact: packagedrawings@atmel.com GPC DRAWING NO. REV. TITLE 6.543-5137.01-4 2 09/07/11 Package: VQFN_7x7_48L Exposed pad 4.5x4.5 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM NOTE MAXSymbol Standard Singulation process Dimensions in mm specifications according to DIN technical drawings 0.02 0.050.0A1 77 . 16.9E 0.23 0.30.16b

0.5 BSCe

0.4 0.50.3L 4.5 4.654.35E2 4.5 4.654.35D2 77 . 16.9D 0.2 0.250.15A3 0.9 10.8A Top View PIN 1 ID D E A Z 10:1 Side View Bottom View e 13 24 48 37 b L Z

ATA6843/ATA6844 [DATASHEET] 9189J–AUTO–05/14 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9189J-AUTO-05/14 • Section 8 “Electrical Characteristics” numbers 8.4 and 8.5 on page 20 removed 9189I-AUTO-03/14

• Section 3.8 “Short Circuit Detection and Short Comparator Reference Input” on page 11 updated
• Section 4 “Absolute Maximum Ratings” on page 14 updated
• Section 8 “Electrical Characteristics” numbers 8.9 to 8.12 on page 21 removed 9189H-AUTO-07/12
• Figure 3-1 “Wake-up Using the LIN Interface” on page 6 updated
• Section 11 “Package Information” on page 25 updated 9189G-AUTO-03/12 • Section 4 “Absolute Maximum Ratings” on page 14 changed 8.19, 8.21 and 8.26 on pages 23 to 25 changed 9189E-AUTO-08/11
• Example test changed and text under figure 3-5 on page 11 added
• Section 8 “Electrical Characteristics” number 3.8 on page 20 changed
• Section 8 “Electrical Characteristics” number 8.31 on page 25 changed
• Figure 9-1 “Typical Application” on page 26 changed
• Table 9-1 “Typical External Components” on page 27 changed 9189D-AUTO-03/11
• Features on page 1 changed
• Section 8 “Electrical Characteristics” number 1.6 on page 19 changed
• Section 8 “Electrical Characteristics” numbers 8.10 and 8.12 on page 24 changed 9189C-AUTO-01/11 • Section 8 “Electrical Characteristics” numbers 8.28 and 8.29 on page 25 added 9189B-AUTO-10/10
• Section 4 “Absolute Maximum Ratings” on page 17 changed
• Section 8 “Electrical Characteristics” numbers 8.23 and 8.24 on page 25 changed.

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