ATA6662_10 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 18

Technical content

Features

  • Operating Range from 5V to 27V  Baud Rate up to 20 Kbaud  Improved Slew Rate Control According to LIN Specification 2.0, 2.1 and SAEJ2602-2  Fully Compatible with 3.3V and 5V Devices  Dominant Time-out Function at Transmit Data (TXD)  Normal and Sleep Mode  Wake-up Capability via LIN Bus (90 µs Dominant)  External Wake-up via WAKE Pin (35 µs Low Level)  Control of External Voltage Regulator via INH Pin  Very Low Standby Current During Sleep Mode (10 µA)  Wake-up Source Recognition  Bus Pin Short-circuit Protected versus GND and Battery  LIN Input Current < 2 µA if VBAT Is Disconnected  Overtemperature Protection  High EMC Level  Interference and Damage Protection According to ISO/CD 7637  Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.0” 1. Description The ATA6662 is a fully integrated LIN transceiver complying with the LIN specification 2.0, 2.1 and SAEJ2602-2. It interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN bus ensures secure data communication up to 20 Kbaud with an RC oscillator for protocol han- dling. Sleep Mode guarantees minimal current consumption. The ATA6662 has advanced EMI and ESD performance. Figure 1-1. Block Diagram VS GND5

6 LIN

4916O–AUTO–05/10

4916O–AUTO–05/10 ATA6662 2. Pin Configuration Figure 2-1. Pinning SO8 RXD EN WAKE TXD INH VS LIN GND Table 2-1. Pin Description Pin Symbol Function

1 RXD Receive data output (open drain)

2 EN Enables Normal Mode; when the input is open or low, the device is in Sleep Mode

3 WAKE High voltage input for local wake-up request. If not needed, connect directly to VS

4 TXD Transmit data input; active low output (s trong pull-down) after a local wake-up request

5 GND Ground, heat sink

6 LIN LIN bus line input/output

7 VS Battery supply

8I N H Battery-related inhibit output for controlling an external voltage regulator; active high after a wake-up request

4916O–AUTO–05/10 ATA6662 3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from hi gher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer any restrictions.

3.2 Supply Pin (V S)

Undervoltage detection is implemented to disable transmission if V S falls to a value below 5V in order to avoid false bus messages. After switching on VS, the IC switches to Fail-safe Mode and INHIBIT is switched on. The supply current in Sleep Mode is typically 10 µA.

3.3 Ground Pin (GND)

The ATA6662 does not affect the LIN Bus in the case of a GND disconnection. It is able to han- dle a ground shift up to 11.5% of VS.

3.4 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor are implemented as specified for LIN 2.x. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to V S, even in the case of a GND shift or V Batt disconnection. The LIN receiver thresholds are co mpatible to the LIN protocol specification.The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a self-adapting short circuit limitation; that is, during current limitation, as the chip temperature increases, the current is reduced.

3.5 Input/Output Pin (TXD)

In Normal Mode the TXD pin is the microcontroller interface to control the state of the Lin output. TXD must be at Low- level in order to have a low LIN Bus. If TXD is high, the LIN output transistor is turned off and the Bus is in recess ive state. The TXD pin is compatible to both a 3.3V or 5V supply. During fail-safe Mode, this pin is used as output and is signalling the wake-up source (see Section 3.14 “Wake-up Source Recognition” on page 7 ). It is current limited to <8m A .

3.6 TXD Dominant Ti me-out Function

The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low longer than t DOM >6m s , t h e pin LIN will be switched off (Reces sive Mode). To reset this mode, switch TXD to high (> 10 µs) before switching LIN to dominant again.

3.7 Output Pin (RXD)

This pin reports to the microcontroller the state of the LIN bus. LIN high (recessive) is reported by a high level at RXD, LIN low (dominant) is reported by a low voltage at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V power supply. The AC characteristics are defined with a pull-up resistor of 5 k Ω to 5V and a load capacitor of 20 pF. The output is short- protected. In Unpowered Mode (V S = 0V), RXD is switched off. For ESD protection a Zener diode is integrated, with VZ =6 . 1 V .

4916O–AUTO–05/10 ATA6662

3.8 Enable I nput Pin (EN)

This pin controls the Operation Mode of the interface. If EN = 1, the interface is in Normal Mode, with the transmission path from TXD to LIN and from LIN to RXD both active. At a falling edge on EN, while TXD is already set to high, the device is switched to Sleep Mode and no transmis- sion is possible. In Sleep Mode, the LIN bus pin is connected to V S with a weak pull-up current source. The device can transmit only after being woken up (see Section 3.9, “Inhibit Output Pin (INH)” ). During Sleep Mode the device is still supplied from the battery voltage. The supply current is typically 10 µA. The pin EN provides a pull-down resistor in order to force the transceiver into Sleep Mode in case the pin is disconnected.

3.9 Inhibit Output Pin (INH)

This pin is used to control an external switchable voltage regulator having a wake-up input. The inhibit pin provides an internal switch towards pin VS. If the device is in Normal Mode, the inhibit high-side switch is turned on and the external voltage regulator is activated. When the device is in Sleep Mode, the inhibit switch is turned off and disables the voltage regulator. A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the V S level. After a system power-up (VS rises from zero), the pin INH switches automatically to the VS level.

3.10 Wake-up Input Pin (WAKE)

This pin is a high-voltage input used to wake the device up from Sleep Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source with typically –10 µA is implemented. The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typically –3 µA. If you do not need a local wake-up in your application, connect pin WAKE directly to pin VS.

4916O–AUTO–05/10 ATA6662

3.11 Operation Modes

  1. Normal Mode This is the normal transmitting and Receiving Mode. All features are available. 2. Sleep Mode In this mode the transmission path is disabled and the device is in low power mode. Supply current from V Batt is typically 10 µA. A wake-up signal from the LIN bus or via pin WAKE will be detected and will switch the device to Fail-safe Mode. If EN then switches to high, Normal Mode is activated. Input debounce timers at pin WAKE (tWAKE), LIN (tBUS) and EN (tsleep,tnom) prevent unwanted wake-up events due to automotive transients or EMI. In Sleep Mode the INH pin is left floating. The internal termination between pin LIN and pin V S is disabled. Only a weak pull-up current (typical 10 µA) between pin LIN and pin VS is present. The Sleep Mode can be activated independently from the actual level on pin LIN or WAKE. 3. Fail-safe Mode At system power-up or after a wake-up event, the device automatically switches to Fail- safe Mode. It switches the INH pin to a high state, to the VS level. LIN communication is switched off. The microcontroller of the application will then confirm the Normal Mode by setting the EN pin to high. 4. Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor. After VS is higher than the VS undervoltage threshold VS th, the IC mode changes from Unpowered Mode to Fail-safe Mode. Figure 3-1. Mode of Operation Table 3-1. Table of Modes Mode of Operation Transceiver INH RXD LIN Fail-safe Off On High, except after wake up Recessive Normal On On LIN depending TXD depending Sleep Off Off High ohmic Recessive Fail-safe Mode INH: high (INH internal high-side switch ON) Communication: OFF ab Sleep Mode INH: high impedance (INH HS switch OFF) Communication: OFF EN = 0; after 1 → 0 while TXD = 1 Go to sleep command EN = 1 Local wake-up event a: VS > 5V b: VS < 5V c: Bus wake-up event d: Wake-up from wake switch b EN = 1 b c d Normal Mode INH: high (INH HS switch ON) Communication: ON Unpowered Mode VBatt = 0V

4916O–AUTO–05/10 ATA6662 Wake-up events from Sleep Mode: L I N b u s E N p i n  WAKE pin  VS Undervoltage Figure 3-1 on page 5 , Figure 3-2 on page 6 and Figure 3-3 on page 7 show details of wake-up operations.

3.12 Remote Wake-up via Dominant Bus State

A voltage less than the LIN pre-wake detection V LINL at pin LIN activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. A falling edge at pin LIN, followed by a dominant bus level VBUSdom maintained for a certain time period (t BUS) and a rising edge at pin LIN results in a remote wake-up request. The device switches to Fail-safe Mode. Pin INH is activated (switches to V S) and the internal termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-2 on page 6). Figure 3-2. LIN Wake-up Waveform Diagram Microcontroller start-up delay time Bus wake-up filtering time (tBUS) Off state Node in sleep state High or floating Low or floating Low High EN High Normal ModeRegulator wake-up time delay INH External voltage regulator EN RXD LIN bus

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3.13 Local Wake-up via Pin WAKE

A falling edge at pin WAKE, followed by a low level maintained for a certain time period (t WAKE), results in a local wake-up request. The wake-up time (t WAKE) ensures that no transient, accord- ing to ISO7637, creates a wake-up. The device switches to Fail-safe Mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a strong pull-down at pin TXD (see Figure on page 9). The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical –3 µA. Even in the case of a continuous low at pin WAKE it is possible to switch the IC into Sleep Mode via a low at pin EN. The IC will stay in Sleep Mode for an unlimited time. To generate a new wake up at pin WAKE it needs first a high signal > 6 µs before a negative edge starts the wake-up filtering time again. Figure 3-3. Wake-up from Wake-up Switch

3.14 Wake-up Source Recognition

The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (LIN bus). The wake-up source can be read on pin TXD in Fail-safe Mode. If an external pull-up resistor (typically 5 kΩ) has been added on pin TXD to the power supply of the microcon- troller, a high level indicates a remote wake-up request (weak pull-down at pin TXD) and a low level indicates a local wake-up request (strong pull-down at pin TXD). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately if the mi crocontroller sets pin EN to high (see Figure 3-2 on page 6 and Figure 3-3 on page 7). Microcontroller start-up delay time Wake filtering time tWAKE Off state Node in sleep state High or floating TXD weak pull-down resistor Low or floating State change TXD strong pull-down Node in operation Weak pull-down EN High HighLow On state High Regulator wake-up time delay Wake pin INH EN TXD RXD Voltage regulator

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3.15 Fail-safe Features

 The reverse current is < 2 µA at pin LIN during loss of V BAT; this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition.  Pin EN provides a pull-down resistor to force the transceiver into Sleep Mode if EN is disconnected.  Pin RXD is set floating if VBAT is disconnected.  Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected.  The LIN output driver has a current limitation, and if the junction temperature T j exceeds the thermal shut-down temperature Toff, the output driver switches off.  The implemented hysteresis, Thys, enables the LIN output again after the temperature has been decreased.

4916O–AUTO–05/10 ATA6662 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Typ. Max. Unit V S - Continuous supply voltage –0.3 +40 V Wake DC and transient voltage (with 33-kΩ serial resistor) - Transient voltage due to ISO7637 (coupling 1 nF) –150 +40 +100 V V Logic pins (RXD, TXD, EN) –0.3 +5.5 V LIN - DC voltage - Transient voltage due to ISO7637 (coupling 1 nF) –27 –150 +40 +100 V V INH - DC voltage –0.3 V S + 0.3 V ESD according to IBEE LIN EMC Test specification 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (33 kΩ serial resistor) KV KV ESD HBM following STM5.1 with 1.5 kΩ/100 pF - Pin VS, LIN, WAKE, INH to GND ±6 KV HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) ±3 KV CDM ESD STM 5.3.1 ±750 V Machine Model ESD AEC-Q100-RevF(003) ±100 V Junction temperature T j –40 +150 °C Storage temperature T stg –55 +150 °C 5. Thermal Characteristics Parameters Symbol Min. Typ. Max. Unit Thermal resistance junction ambient R thJA 145 K/W Special heat sink at GND (pin 5) on PCB (fused lead frame to pin 5) RthJA 80 K/W Thermal shutdown T off 150 165 180 °C Thermal shutdown hysteresis T hys 5 1 02 0° C

4916O–AUTO–05/10 ATA6662 6. Electrical Characteristics 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1V S Pin 1.1 DC voltage range nominal 7 V S 5 13.5 27 V A

1.2 Supply current in Sleep Mode

VLIN > VS – 0.5V VS < 14V 7I VSsleep 10 20 µA A 1.3 Supply current in Normal Mode Bus recessive VS < 14V 7I VSrec 0.9 1.3 mA A 1.4 Bus dominant VS < 14V Total bus load > 500Ω 7I VSdom 1.2 2 mA A

1.5 Supply current in Fail-safe Mode Bus recessive

VS < 14V 7I VSfail 0.5 1.1 mA A 1.6 V S undervoltage threshold on V Sth 44 . 9 5 V A 1.7 V S undervoltage threshold off V Sth 4.05 5 V A

1.8 VS undervoltage threshold

hysteresis 7V Sth_hys 50 500 mV A

2 RXD Output Pin (Open Drain)

2.1 Low-level output sink current Normal Mode

VLIN = 0V, VRXD = 0.4V 1I RXDL 1.3 2.5 8 mA A 2.2 RXD saturation voltage 5-k Ω pull-up resistor to 5V 1 Vsat RXD 0.4 V A

2.3 High-level leakage current Normal Mode

VLIN = VBAT, VRXD = 5V 1I RXDH –3 +3 µA A 2.4 ESD zener diode I RXD = 100 µA 1 VZ RXD 5.8 8.6 V A

3 TXD Input Pin

3.1 Low-level voltage input 4 V TXDL –0.3 +0.8 V A 3.2 High-level voltage input 4 V TXDH 25 . 5 V A

3.3 Pull-down resistor V TXD = 5V 4 R TXD 125 250 600 k Ω A

3.4 Low-level leakage current V TXD = 0V 4 I TXD_leak –3 +3 µA A

3.5 Low-level output sink current

Fail-safe Mode, local wake up VTXD = 0.4V VLIN = VBAT 4I TXD 1.3 2.5 8 mA A 4E N I n p u t P i n 4.1 Low-level voltage input 2 V ENL –0.3 +0.8 V A 4.2 High-level voltage input 2 V ENH 25 . 5 V A

4.3 Pull-down resistor V EN = 5V 2 R EN 125 250 600 k Ω A

4.4 Low-level input current V EN = 0V 2 I EN –3 +3 µA A

5 INH Output Pin

5.1 High-level voltage Normal Mode

IINH = –2 mA 8V INHH VS – 3 V S VA

5.2 Leakage current Sleep Mode

VINH = 0V/27V, VS = 27V 8I INHL –3 +3 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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6 WAKE Pin

6.1 High-level input voltage 3 V WAKEH

VS – VS + 0.3V VA

6.2 Low-level input voltage I WAKE = Typically –3 µA 3 V WAKEL –1V VS –

3.3V VA

6.3 Wake pull-up current V S < 27V 3 I WAKE –30 –10 µA A

6.4 High-level leakage current V S = 27V, VWAKE = 27V 3 I WAKE –5 +5 µA A

7 LIN Bus Driver

7.1 Driver recessive output voltage R LOAD = 500Ω /1k Ω 6V BUSrec

0.9 × VS VS VA

7.2 Driver dominant voltage

VBUSdom_DRV_LoSUP VVS = 7V, Rload = 500Ω 6V _LoSUP 1.2 V A

7.3 Driver dominant voltage

VBUSdom_DRV_HiSUP VVS = 18V, Rload = 500Ω 6V _HiSUP 2V A

7.4 Driver dominant voltage

VBUSdom_DRV_LoSUP VVS = 7V, Rload = 1000Ω 6V _LoSUP_1k 0.6 V A

7.5 Driver dominant voltage

VBUSdom_DRV_HiSUP VVS = 18V, Rload = 1000Ω 6V _HiSUP_1k_ 0.8 V A

7.6 Pull-up resistor to V S The serial diode is mandatory 6 R LIN 20 30 60 k Ω A

7.7 Voltage drop at the serial diodes In pull-up path with Rslave

ISerDiode = 10 mA 6V SerDiode 0.4 1.0 V D

7.8 LIN current limitation

VBUS = VBAT_max 6I BUS_LIM 40 120 200 mA A 7.9 Input leakage current at the receiver, including pull-up resistor as specified Input leakage current Driver off VBUS = 0V, VS = 12V 6I BUS_PAS_dom –1 mA A

7.10 Leakage current LIN recessive

8V < VBAT < 18V 8V < VBUS < 18V VBUS ≥ VBAT 6I BUS_PAS_rec 10 20 µA A 7.11 Leakage current at ground loss; Control unit disconnected from ground; Loss of local ground must not affected communication in the residual network GND Device = VS VBAT =12V 0V < VBUS < 18V 6I BUS_NO_gnd –10 +0.5 +10 µA A 7.12 Leakage current at loss of battery; Node has to substain the current that can flow under this condition; Bus must remain operational under this condition V BAT disconnected VSUP_Device = GND 0V < VBUS < 18V 6I BUS_NO_bat 0.1 2 µA A

7.13 Capacitance on pin LIN to GND 6 C LIN 20 pF D

  1. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4916O–AUTO–05/10 ATA6662

8 LIN Bus Receiver

8.1 Center of receiver threshold VBUS_CNT =

(Vth_dom + Vth_rec)/2 6V BUS_CNT 0.475 × VS 0.5 × VS 0.525 × VS VA 8.2 Receiver dominant state V EN = 5V 6 V BUSdom –27 0.4 × VS VA

8.3 Receiver recessive state V EN = 5V 6 V BUSrec

0.6 × VS

40 V A

8.4 Receiver input hysteresis V HYS = Vth_rec – Vth_dom 6V BUShys

0.028 × VS 0.1 × VS 0.175 × VS VA

8.5 Pre-wake detection LIN

High-level input voltage 6V LINH VS – VS + 0.3V VA

8.6 Pre-wake detection LIN

Low-level input voltage Switches the LIN receiver on 6 V LINL –27V VS – 3.3V VA

9 Internal Timers

9.1 Dominant time for wake-up via

LIN bus VLIN = 0V 6 t BUS 30 90 150 µs A

9.2 Time of low pulse for wake-up

via pin WAKE VWAKE = 0V 3 t WAKE 73 5 5 0 µ s A 9.3 Time delay for mode change from Fail-safe Mode to Normal Mode via pin EN VEN = 5V 2 t norm 2 7 15 µs A 9.4 Time delay for mode change from Normal Mode into Sleep Mode via pin EN VEN = 0V 2 t sleep 2 7 12 µs A

9.5 TXD dominant time out time V TXD = 0V 4 t dom 69 2 0 m s A

9.6 Power-up delay between VS =5 V

until INH switches to high VVS = 5V t VS 200 µs A LIN Bus Driver AC Parameter with Different Bus Loads Load 1 (small): 1 nF , 1 kΩ ; Load 2 (large): 10 nF , 500Ω ; RRXD = 5 kΩ ; CRXD = 20 pF; Load 3 (medium): 6.8 nF , 660Ω characterized on samples; 10.1 and 10.2 specifies the timing parameters for proper operation at 20 Kbit/s, 10.3 and 10.4 at 10.4 Kbit/s.

10.1 Duty cycle 1

THRec(max) = 0.744 × VS THDom(max) = 0.581 × VS VS = 7.0V to 18V tBit = 50 µs D1 = tbus_rec(min) /( 2 × tBit) 6D 1 0 . 3 9 6 A

10.2 Duty cycle 2

THRec(min) = 0.422 × VS THDom(min) = 0.284 × VS VS = 7.0V to 18V tBit = 50 µs D2 = tbus_rec(max) /( 2 × tBit) 6 D2 0.581 A

10.3 Duty cycle 3

THRec(max) = 0.778 × VS THDom(max) = 0.616 × VS VS = 7.0V to 18V tBit = 96 µs D3 = tbus_rec(min) /( 2 × tBit) 6D 3 0 . 4 1 7 A 6. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4916O–AUTO–05/10 ATA6662 Figure 6-1. Definition of Bus Timing Parameter

10.4 Duty cycle 4

THRec(min) = 0.389 × VS THDom(min) = 0.251 × VS VS = 7.0V to 18V tBit = 96 µs D4 = tbus_rec(max) /( 2 × tBit) 6 D4 0.590 A

11 Receiver Electrical AC Parameters of the LIN Physical Layer

LIN receiver, RXD load conditions: CRXD = 20 pF , Rpull-up = 5 kΩ

11.1 Propagation delay of receiver

(see Figure 6-1 on page 13) trec_pd = max(trx_pdr, trx_pdf) VS = 7.0V to 18V 1t rx_pd 6µ s A 11.2 Symmetry of receiver propagation delay rising edge minus falling edge t rx_sym = trx_pdr – trx_pdf VS = 7.0V to 18V 1t rx_sym –2 +2 µs A 6. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter VS (Transceiver supply of transmitting node) TXD (Input to transmitting node) RXD (Output of receiving node 1) LIN Bus Signal tBit tBus_dom(max) tBus_dom(min) tBus_rec(min) tBus_rec(max) RXD (Output of receiving node 2) THRec(max) THDom(max) THDom(min) THRec(min) Thresholds of receiving node 1 Thresholds of receiving node 2 trx_pdf(1) trx_pdr(1) trx_pdr(2) trx_pdf(2) tBit tBit

4916O–AUTO–05/10 ATA6662 Figure 6-2. Application Circuit VS VS INH EN RXD 12V VBATTERY 5 kΩ 100 nF ATA6662 33 kΩ 10 kΩ Short-circuit and overtemperature protection Control unit Slew rate control Wake-up bus timer Filter Master node pull-up Wake-up timer TXD Time-out timer Sleep mode Receiver WAKE TXD Microcontroller IO VDD External switch GND VS LIN LIN sub bus 220 pF 22 µF GND

4916O–AUTO–05/10 ATA6662 8. Package Information 7. Ordering Information Extended Type Number Package Remarks ATA6662-TAQY SO8 LIN transceiver, Pb-free, 4k, taped and reeled ATA6662C-TAQY SO8 LIN transceiver, Pb-free, 4k, taped and reeled Package: SO 8 Dimensions in mm specifications according to DIN technical drawings Issue: 1; 15.08.06 Drawing-No.: 6.541-5031.01-4 0.2 5±0.2 3.8±0.1 6±0.2 3.7±0.1 4.9±0.1 3.81 0.4 1.27 0.1+0.15 1.4

4916O–AUTO–05/10 ATA6662 9. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4916O-AUTO-05/10 • Features on page 1 changed

  • Heading 3.6: text changed 4916N-AUTO-03/10
  • Features on page 1 changed
  • Section 4 “Absolute Maximum Ratings” on page 9 changed
  • Section 6 “Electrical Characteristics” number 7.13 on page 11 added
  • Section 7 “Ordering Information” on page 16 changed 4916M-AUTO-09/09
  • Figure 1-1 “Block Diagram” on page 1 changed
  • Section 4 “Absolute Maximum Ratings” on page 8 changed
  • Figure 6-2 “Application Circuit” on page 14 changed 4916L-AUTO-02/09 • Section 6 “El.Characteristics” numbers 3.2 and 4.2 on page 9 changed 4916K-AUTO-12/08
  • Figure 2-1 “Pinning SO8” on page 2 changed
  • Section 3.2 “Supply Pin (VS)” on page 3 changed
  • Section 3.8 “Enable Input Pin (EN)” on page 4 changed
  • Section 3.11 “Operation Modes” on page 5 changed
  • Section 3.12 “Remote Wake-up via Dominant Bus State” on page 5 changed
  • Section 3.14 “Wake-up Source Recognition” on page 6 changed
  • Figure 3.2 “LIN Wake-up Waveform Diagram” on page 7 changed
  • Figure 3.3 “Wake-up from Wake-up Switch” on page 7 changed
  • Section 4 “Absolute Maximum Ratings” on page 8 changed
  • Section 5 “Thermal Resistance” on page 8 changed
  • Section 6 “Electrical Characteristics” on pages 9 to 12 changed
  • Figure 6-2 “Application Circuit” on page 13 changed 4916J-AUTO-02/08
  • “Pre-normal Mode” in “Fail-safe Mode” changed
  • Section 3.9 “Inhibit Output Pin (INH) on page 4 changed
  • Section 4 “Absolute Maximum Ratings” on page 8 changed
  • Section 6 “Electrical Characteristics” number 5.1 on page 9 changed 4916I-AUTO-12/07 • Section 3.1 “Physical Layer Compatibility” on page 3 added
  • Section 6 “El.Characteristics” numbers 1.5, 1.6 and 1.7 on page 9 changed 4916H-AUTO-10/07 • Section 7 “Ordering Information” on page 14 changed 4916G-AUTO-07/07 • Put datasheet in a new template
  • Capital T for time generally changed in a lower case t

4916O–AUTO–05/10 ATA6662 4916F-AUTO-05/07

  • Figure 1-1 “Block Diagram” on page 1 changed
  • Figure 6-2 “Application Circuit” on page 13 changed
  • Features on page 1 changed 4916E-AUTO-02/07 • Section 4 “Absolute Maximum Ratings” on page 8 changed
  • Section 2 “Electrical Characteristics” on pages 9 to 11 changed 4916D-AUTO-02/07
  • Features on page 1 changed
  • Section 1 “Description” on page 1 changed
  • Table 2-1 “Pin Description” on page 2 changed
  • Section 3.2 “Ground Pin (GND) on page 3 changed
  • Section 3.7 “Enable Input Pin (EN)” on page 4 changed
  • Section 3.11 “Remote Wake-up via Dominant Bus State” on page 5 changed
  • Figure 3-1 “Mode of Operation” on page 6 changed
  • Section 3-14 “Fail-safe Features” on page 6 changed
  • Section 4 “Absolute Maximum Ratings” on page 8 changed
  • Section 6 “Electrical Characteristics” on pages 9 to 11 changed Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. (Continued) Revision No. History

4916O–AUTO–05/10 Headquarters International Atmel Corporation

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