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Features
- Usable for Automotive 12V/24V and Industrial Applications Maximum High-speed Data Transmissions up to 1 MBaud Fully Compatible with ISO 11898 Controlled Slew Rate Standby Mode TXD Input Compatible to 3.3V Short-circuit Protection Overtemperature Protection High Voltage Bus Lines Protection, –40V to +40V High Speed Differential Receiver Stage with a Wide Common Mode Range, –10V to +10V, for High Electromagnetic Immunity (EMI) Fully Controlled Bus Lines, CANH and CANL to Minimize Electromagnetic Emissions (EME) High ESD Protection at CANH, CANL HBM 8 kV, MM 300V 1. Description The ATA6660 is a monolithic circuit based on the Atmel ®’s Smart Power BCD60-III technology. It is especially designed for high speed CAN-Controller (CAN-C) differen- tial mode data transmission between CAN-Controllers and the physical differential bus lines. Figure 1-1. Block Diagram
4 RXD
5 VREF
7 CANH
6 CANL
2 GND
3 VCC
1 TXD TXD Input Stage
0.5*VCC Receiver High-speed Can Transceiver ATA6660 4582E–AUTO–02/08
4582E–AUTO–02/08 ATA6660 2. Pin Configuration Figure 2-1. Pinning SO8 TXD GND VCC RXD RS CANH CANL VREF Table 2-1. Pin Description Pin Symbol Function
1 TXD Transmit data input
2 GND Ground
3 VCC Supply voltage
4 RXD Receive data output
5 VREF Reference voltage output
6 CANL Low level CAN voltage input/output
7 CANH High level CAN voltage input/output
8 RS Switch Standby Mode/Normal Mode
4582E–AUTO–02/08 ATA6660 3. Functional Description The ATA6660 is a monolithic circuit based on At mel’s Smart Power BCD60-III technology. It is especially designed for high-speed differential mode data transmission in harsh environments like automotive and industrial applications. Baudrate can be adjusted up to 1 Mbaud. The ATA6660 is fully compatible to the ISO11898, the developed standard for high speed CAN-C (Controller Area Network) communication.
3.1 Voltage Protection and ESD
High voltage protection circuitry on both line pins, CANH (pin 7) and CANL (pin 6), allow bus line voltages in the range of –40V to +40V. ESD protection circuitry on line pins allow HBM = 8 kV, MM = 300V. The implemented high voltage protection on bus line output/input pins (7/6) makes the ATA6660 suitable for 12V automotive applications as well as 24V automotive applications.
3.2 Slope Control
A fixed slope is adjusted to prevent unsymmetrical transient s on bus lines causing EMC prob- lems. Controlled bus lines, both CANH and CANL signal, will reduce radio frequency interference to a minimum. In well designed bus configurations the filter design costs can be reduced dramatically.
3.3 Overcurrent Protection
In the case of a line shorts, like CANH to GND, CANL to VCC, integrated short current limitation allows a maximum current of I CANH_SC or ICANL_SC. If junction temperature rises above 165°C an internal overtemperature protection circuitry shuts down both output stages, the receiver will stay activated.
3.4 Standby Mode
The ATA6660 can be switched to Standby Mode by forcing the voltage VRS > 0.87 × VCC. In Standby Mode the supply current will reduce dram atically, supply current during Standby Mode is typical 600 µA (IVCC_stby). Transmitting data function will no t be supported, but the opportunity will remain to receive data. A high-speed comparator is listening for activities on the bus. A dom- inant bus signal will force the output RXD to a low level in typical tdRXDL = 400 ns. If the RS pin is not connected, causing through a broken connection to the controller, the ATA6660 will switch to Standby Mode automatically.
3.5 High-speed Receiver
In Normal Mode a fast receiver circuitry combined with a resistor network is able to detect differ- ential bus line voltages V rec_th > 0.9V as dominant bit, differential bus line voltages V rec_th <0 . 5 V as recessive bit. The wide receiver common mode range, –10V to +10V, combined with a symmetrical differential receiver stage offers high immunity against elec tromagnetic interference. A typical hysteresis of 70 mV is implemented. Dominant differential bus voltages forces RXD output (pin 4) to low level, recessive differential bus voltages to high level.
4582E–AUTO–02/08 ATA6660
3.6 TXD Input
The input stage pin 1 (TXD) is compatible for 3.3V output levels from new controller families. Pull-up resistance (25 k Ω) forces the IC to Recessive Mode, if TXD-Pin is not connected. TXD low signal drives the transmitter into dominant state.
3.7 Transmitter
A integrated complex compensation technique allows stable data transmission up to 1 MBaud. Low level on TXD input forces bus line voltages CANH to 3.5V, CANL to 1.5V with a termination resistor of 60Ω. In the case of a line short circuit, like CANH to GND, CANL to VCC, integrated short current limitation circuitry allows a maxi mum current of 150 mA. If junction temperature rises above typical 163°C an internal overtemperature protection shuts down both output stages, the Receive Mode will stay activated.
3.8 Split Termination Concept
With a modified bus termination (see Figure 8-3 on page 10 ) a reduction of emission and a higher immunity of the bus system can be achieved. The one 120 Ω resistor at the bus line end nodes is split into two resistors of equal value, i.e., two resistors of 60 Ω. The resistors for the stub nodes is recommended with two resistors of 1.3 k Ω. (for example 8 stub nodes and 2 bus end nodes) Notice: The bus load of all the termination resistors has to stay within the range of 50Ω to 65Ω. The common mode signal at the centre tap of the termination is connected to ground via a capacitor of e.g., C split = 10 nF to 100 nF. A separate ground lead to the ground pin of the mod- ule connector is recommended.
4582E–AUTO–02/08 ATA6660 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Conditions Min. Max. Unit Supply voltage V CC –0.3 +6 V DC voltage at pins 1, 4, 5 and 8 VTXD, VREF, VRS, VRXD –0.3 V CC +0.3 V DC voltage at pins 6 and 7 V CANH, VCANL 0V < VCC < 5.25V; no time limit –40.0 +40.0 V Transient voltage at pins 6 and 7 –150 +100 V Storage temperature T Stg –55 +150 °C Operating ambient temperature T amb –40 +125 °C ESD classification All pins HBM ESD S.5.1 MM JEDEC A115A ±3000 ±200 V V ESD classification Pin 6, 7 versus pin 2 HBM 1.5 kΩ, 100 pF MM 0Ω, 200 pF ±8000 ±300 V V 5. Thermal Resistance Parameters Symbol Value Unit Thermal resistance from junction to ambient R thJA 160 K/W 6. Truth Table VCC TXD RS CANH CANL Bus State RXD 7. RS (Pin 8) Functionality Slope Control Mode Voltage and Current Levels VRS > 0.87 × VCC Standby I RS < | 10 µA | VRS < 0.3 × VCC Constant slope control I RS ≤ 500 µA
4582E–AUTO–02/08 ATA6660 8. Electrical Characteristics VCC = 4.75V to 5.25V; Tamb = –40°C to +125°C; RBus = 60Ω; unless otherwise specified. All voltages referenced to ground (pin 2); positive input current. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
1 Supply Current
1.1 Supply current
VTXD = 0V VRS = 0V 3I vcc_dom 45 60 mA A
1.2 Supply current
VTXD = 5V VRS = 0V 3I vcc_rec 10 15 mA A
1.3 Supply current standby V RS = 5V 3 I vcc_stby 600 980 µA A
2 Transmitter Data Input TXD
2.1 HIGH level input
VTXD = 5V VRS = 0V 1V TXDH 2V CC + 0.3 V A
2.2 LOW level input voltage VTXD = 0V
VRS = 0V 1V TXDL –0.3 +1 V A
2.3 HIGH level input current V TXD = VCC 1I IH –1 0 µA A
2.4 LOW level input voltage V TXD = 0V 1 I IL –500 -50 µA A
3 Receiver Data Output RXD
3.1 High level output
voltage IRXD = –100 µA 4 V RXDH 0.8 × VCC VCC VA 3.2 Low level output voltage I RXD = 1 mA 4 V RXDL 00 . 2 × VCC VA
3.3 Short current at RXD VTXD = 5V
VRXD = 0V 4I RXDs1 –3 -1 mA A
3.4 Short current at RXD VTXD = 0V
VRXD = 5V 4I RXDs2 26 m A A
4 Reference Output Voltage VREF
4.1 Reference output
VRS = 0V; –50 µA < I5 < 50 µA 5V ref_no 0.45 VCC 0.55 VCC VA
4.2 Reference output
VRS = 5 V; –5 µA < I5 < 5 µA 5V ref_stby 0.4 × VCC 0.6 VCC VA
5 DC Bus Transmitter CANH; CANL
5.1 Recessive bus voltage V TXD = VCC; no load 6, 7 VCANH;
2.0 2.5 3.0 V A
5.2 IO(CANH)(reces)
IO(CANL)(reces) –40V < VCANH; VCANL < 40V; 0V < VCC < 5.25V 6, 7 I O_reces –5 +5 mA A
5.3 CANH output voltage
dominant VTXD = 0V 6, 7 V CANH 2.8 3.5 4.5 V A
5.4 CANL output voltage
dominant VTXD = 0V 6, 7 V CANL 0.5 1.5 2.0 V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4582E–AUTO–02/08 ATA6660 5.5 Differential bus output voltage (VCANH – VCANL) VTXD = 0V; RL = 45Ω to 60Ω; VCC = 4.9V 6, 7 Vdiff dom 1.5 2 3.0 V A
5.6 V TXD = VCC; no load 6, 7 Vdiff rec –500 +50 mV A
5.7 Short-circuit CANH
VCANH = –10V TXD = 0V 6, 7 I CANH_SC –35 –100 mA A
5.8 Short-circuit CANL
VCANL = 18V TXD = 0V 6, 7 I CANL_SC 50 - 150 mA A
6 DC Bus Receiver CANH; CANL
6.1 Differential receiver threshold voltage Normal Mode –10V < VCANH < +10V –10V < VCANL < +10V 6, 7 V rec_th 0.5 0.7 0.9 V A 6.2 Differential receiver threshold voltage Standby Mode VRS = VCC 6, 7 V rec_th_stby 0.5 0.7 0.9 V A
6.3 Differential input
hysteresis 6, 7 V diff(hys) 70 mV A 6.4 CANH and CANL common mode input resistance 6, 7 R i 51 52 5 k Ω A
6.5 Differential input
resistance 6, 7 R diff 10 30 100 k Ω A 6.6 Matching between CANH and CANL common mode input resistance 6, 7 R i_m –3 +3 % A
6.7 CANH, CANL input
capacitance 6, 7 C i 20 pF D
6.8 Differential input
capacitance 6, 7 C diff 10 pF D
6.9 CANH, CANL input
VCC = 0V VCANH = 3.5V VCANL = 1.5V 6, 7 ILI(CANH); ILI(CANL) 250 µA A
7 Thermal Shut-down
7.1 Shut-down junction temperature for CANH/CANL T J(SD) 150 163 175 °C B 7.2 Switch on junction temperature for CANH/CANL TJ(SD) 140 154 165 °C B
7.3 Temperature hysteresis T Hys 10 K B
- Electrical Characteristics (Continued) VCC = 4.75V to 5.25V; Tamb = –40°C to +125°C; RBus = 60Ω; unless otherwise specified. All voltages referenced to ground (pin 2); positive input current. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4582E–AUTO–02/08 ATA6660 8 Timing Characteristics Normal Mode, V RS ≤ 0.3 × VCC (see Figure 8-1 on page 9)
8.1 Delay TXD to bus active V RS = 0V t d(TXD-BUS_ON) 120 180 ns A
8.2 Delay TXD to bus
inactive VRS = 0V t d(TXD-BUS_OFF) 50 100 ns A
8.3 Delay TXD to RXD,
recessive to dominant VRS = 0V 6, 7 t d_activ(TXD-RXD) 200 420 ns A
8.4 Delay TXD to RXD,
dominant to recessive VRS = 0V t d_inactiv(TXD-RXD) 180 460 ns A 8.5 Difference between Delay TXD to RXD dominant to Delay recessive tdiff = td_activ(TXD-RXD) – td_inactiv(TXD-RXD) tdiff –280 80 ns A 9 Timing Characterist ics Standby Mode VRS ≥ 0.87 × VCC
9.1 Bus dominant to RXD
low in Standby Mode VRS = VCC 4t dRxDL 300 450 ns A 9.2 Wake up time after Standby Mode (time delay between Standby to Normal Mode and to bus dominant) TXD = 0V VRS from 0V to V CC 6, 7 T wake_up 2µ s A
10 Standby/Normal Mode Selectable via RS (Pin 8)
10.1 Input voltage for Normal
Mode VRS = VCC 8V RS 0.3 × VCC VA
10.2 Input current for Normal
Mode VRS = 0V 8 I RS –700 µA A
10.3 Input voltage for
0.87 × VCC VA 8. Electrical Characteristics (Continued) VCC = 4.75V to 5.25V; Tamb = –40°C to +125°C; RBus = 60Ω; unless otherwise specified. All voltages referenced to ground (pin 2); positive input current. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4582E–AUTO–02/08 ATA6660 Figure 8-1. Timing Diagrams TXD Vdiff CANH CANL RXD HIGH LOW Dominant (Bus Active) Recessive (Bus Inactive) HIGH LOW 0.7VCC 0.3VCC 0.9V 0.5V t(TXD_bus_on) td_activ(TXD_RXD) td_inactiv(TXD_RXD) td(TXD_bus_off) Dominant CANH Dominant CANL
4582E–AUTO–02/08 ATA6660 10. Package Information 9. Ordering Information Extended Type Number Package Remarks ATA6660-TAPY SO8 Can transceiver, Pb-free, 1k, taped and reeled ATA6660-TAQY SO8 Can transceiver, Pb-free, 4k, taped and reeled Package: SO 8 Dimensions in mm specifications according to DIN technical drawings Issue: 1; 15.08.06 Drawing-No.: 6.541-5031.01-4 0.2 5±0.2 3.8±0.1 6±0.2 3.7±0.1 4.9±0.1 3.81 0.4 1.27 0.1+0.15 1.4
4582E–AUTO–02/08 ATA6660 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, and not to this document. Revision No. History 4582E-BCD-02/08 • Put datasheet in the newest template
- Section 9 “Ordering Information” on page 11 changed 4582D-BCD-06/06
- Put datasheet in the newest template
- Pb-free logo on page 1 deleted
- Section 9 “Ordering Information” on page 11 changed 4582C-BCD-09/05
- Put datasheet in the newest template
- Pb-free logo on page 1 added
- Heading rows on Table “Absolute Maximum Ratings” on page 5 added
- Section 9 “Ordering Information” on page 11 changed
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