ATA6630

ATA6628 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 36

Technical content

Features

• Master and Slave Operation Possible  Supply Voltage up to 40V  Operating voltage VS = 5V to 27V  Typically 10 µA Supply Current During Sleep Mode  Typically 40 µA Supply Current in Silent Mode  Linear Low-drop Voltage Regulator: – Normal, Fail-safe, and Silent Mode  ATA6628 VCC = 3.3V ±2%  ATA6630 VCC = 5.0V ±2% – In Sleep Mode V CC is Switched Off  VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical Combined at Open Drain Output NRES  High-speed Mode Up to 115 kBaud  Internal 1:6 Voltage Divider for VBattery Sensing  Negative Trigger Input for Watchdog  Boosting the Voltage Regulator Possible with an External NPN Transistor  LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2  Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin  INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up Resistor  Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery  Adjustable Watchdog Time via External Resistor  Advanced EMC and ESD Performance  Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.1”  Interference and Damage Protection According ISO7637  Package: QFN 5 mm × 5 mm with 20 Pins 1. Description The ATA6628 is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for 3.3V/50 mA output and a window watchdog. The ATA6630 has the same functionality as the ATA6628; however, it uses a 5V/50 mA regulator. The voltage regulator is able to source 50 mA, but the output current can be boosted by using an external NPN transistor. This chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for LIN-bus systems. ATA6628/ATA6630 are designed to handle the low-speed data communi cation in vehicles, e.g., in conve- nience electronics. Improved slope control at the LIN-driver ensures secure data communication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low cur- rent consumption. LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog ATA6628 ATA6630 Preliminary 9117E–AUTO–07/10

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 1-1. Block Diagram High Speed Mode Adjustable Watchdog Oscillator Short Circuit and Overtemperature ProtectionTXD Time-out Timer Edge Detection Debounce Time Internal Testing Unit Control Unit Slew Rate Control Wake-up Bus Timer Mode Select Undervoltage Reset Normal/Silent/ Fail-safe Mode 3.3V/50 mA/±2% 5V/50 mA/±2% RF Filter Watchdog RXD NTRIGGNDPV PVCC PVCC PVCC TMMODE EN TXD SP_MODE KL_15 WAKE Receiver 591 6 3 Normal and Fail-safe Mode LIN WD_OSC NRES PVCC VCC VS DIV_ON VBATT Normal and Fail-safe Mode INH

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 2. Pin Configuration Figure 2-1. Pinning QFN20 67 8 109 20 19 1 8 QFN 5 mm 5 mm 0.65 mm pitch 20 lead ATA6628/30 INH TXD NRES WD_OSC TM MODE KL15 PVCC VCC VS SP_MODE PV DIV_ON RXD LIN GND WAKE NTRIG EN VBATT Table 2-1. Pin Description Pin Symbol Function

1 VBATT Battery supply for the voltage divider

2 EN Enables the device into Normal Mode

3 NTRIG Low-level watchdog trigger input from mi crocontroller; if not needed, connect to PVCC

4 WAKE High-voltage input for local wake-up request; if not needed, connect to VS

5 GND System ground

6 LIN LIN-bus line input/output

7 RXD Receive data output

8 DIV_ON Input to switch on the internal voltage divider, active high

9 PV Voltage divider output

10 SP_MODE Input to switch the transceiver in High-speed Mode, active high

11 INH Battery related High-side switch

12 TXD Transmit data input; active low output (strong pull down) after a local wake up request

13 NRES Output undervoltage and watchdog reset (open drain)

14 WD_OSC External resistor for adjustable watchdog timing; if not needed, connect to GND

15 TM For factory testing only (tie to ground)

16 MODE Low watchdog is on; high watchdog is off

17 KL_15 Ignition detection (edge sensitive)

18 PVCC 3.3V/5V regulator sense input pin, connect to VCC 19 VCC 3.3V/5V regulator output/driver pin, connect to PVCC

20 VS Battery supply

Backside Heat slug is connected to GND

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from hi gher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer any restrictions.

3.2 Supply Pin (VS)

The LIN operating voltage is V S = 5V to 27V. An undervoltage detection is implemented to disable data transmission if V S falls below VS th in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e., 3.3V/5V/50 mA output capability). The supply current is typically 10 µA in Sleep Mode and 40 µA in Silent Mode.

3.3 Ground Pin (GND)

The ATA6628/ATA6630 does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. The mandatory system ground is pin 5.

3.4 Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads up to 50 mA. It is able to supply the microcontroller and other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold V thun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to the VCC pin and its emitter connected to PVCC.

3.5 Voltage Regulator Sense Pin (PVCC)

The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal output transistor), th is pin must be connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e., its emitter terminal.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.x specificat ion are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled.

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

3.7 Input/Output Pin (TXD)

In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe source. It is current-limited to < 8 mA.

3.8 TXD Dominant Ti me-out Function

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low for longer than t DOM >2 7m s , t h e LIN-bus driver is switched to recessive state. Nevertheless, when switching to Sleep Mode, the actual level at the TXD pin is relevant. To reactivate the LIN bus driver, switch TXD to high (> 10 µs).

3.9 Output Pin (RXD)

This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5 k Ω to PVCC. The AC characteristics can be defined with an external load capacitor of 20 pF. The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V). During Fail-safe Mode it is signalling the fail-safe source.

3.10 Enable Input Pin (EN)

The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data trans- mission is then possible, and the current consumption is reduced to I VS typ. 40 µA. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmis- sion is possible, and the voltage regulator is switched off.

3.11 Wake Input Pin (WAKE)

The WAKE Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10 µA, is implemented. If a local wake-up is not needed in the application, connect the WAKE pin directly to the VS pin.

3.12 Mode Input Pin (MODE)

Connect the MODE pin directly or via an exte rnal resistor to GND for normal watchdog opera- tion. To debug the software of the connected mi crocontroller, connect MODE pin to PVCC and the watchdog is switched off. Note: If you do not use the watchdog, connect pin MODE directly to PVCC.

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

3.13 TM Input Pin

The TM pin is used for final production measurements at Atmel ®. In normal application, it has to be always connected to GND.

3.14 KL_15 Pin

The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge-sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. Although KL_15 pin is at high voltage (V Batt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical Tdb Kl_15 of 160 µs is implemented. The input voltage threshold can be adjusted by varying the external resistor due to the input current I KL_15 . To protect this pin against voltage transients, a serial resistor of 47 k Ω and a ceramic capacitor of 100 nF are recommended. Wi th this RC combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition KL_15. You can also increase the wake-up time using external capacitors with higher values.

3.15 INH Output Pin

The INH Output pin is used to switch an external voltage regulator on during Normal and Fail-safe Mode. The INH Output is a high-side switch, which is switched-off in Sleep and Silent Mode. It is possible to switch off the external 1 k Ω master resistor via the INH pin for master node applications.

3.16 Reset Output Pin (NRES)

The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a watchdog failure.

3.17 WD_OSC Output Pin

The WD_OSC Output pin provides a typical volta ge of 1.2V, which supplies an external resistor with values between 34 kΩ and 120 kΩ to adjust the watchdog oscillator time. If the watchdog is disabled, this voltage is switched off and you can either tie to GND or leave this pin open.

3.18 NTRIG Input Pin

The NTRIG Input pin is the trig ger input for the window watchdog. A pull-up resistor is imple- mented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger.

3.19 Wake-up Events from Sleep or Silent Mode

L I N - b u s  WAKE pin E N p i n  KL_15

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

3.20 DIV_ON Input Pin

The DIV_ON pin is a low voltage input. It is used to switch on or off the internal voltage divider PV output directly with no time limitation (see Table 3-1 on page 7). It is switched on if DIV_ON is high or it is switched off if DIV_ON is low. In Sleep Mode the DIV_ON functionality is disabled and PV is off. An internal pull-down resistor is implemented.

3.21 VBATT Input Pin

The VBATT is a high voltage input pin to supply th e internal voltage divide r. In an application with battery voltage monitoring, this pin is connected to V Battery via a 47Ω resistor in series and a 10 nF capacitor to GND (see Figure 9-2 on page 31). The the divider ratio is 1:6.

3.22 PV Output Pin

For applications with battery monitoring, this pin is directly connected to the ADC of a microcon- troller. For buffering the ADC input an external capacitor might be needed. This pin guarantees a voltage and temperature stable output of a V Battery ratio. The PV output pin is controlled by the DIV_ON input pin.

3.23 SP_MODE Input Pin

The SP_MODE pin is a low-voltage input. High-speed Mode of the transceiver can be activated via a high level during Normal Mode. Return to LIN 2.x Transceiver Mode with slope control is possible if you switch the SP_MODE pin to low. Table 3-1. Table of Voltage Divider Mode of Operation Input DiV_ON Voltage Divider Output PV Fail-safe/Normal/ High-speed/Silent 0O f f 1O n Sleep 0O f f 1O f f

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 4. Modes of Operation Figure 4-1. Modes of Operation Unpowered Mode (See Section 4.5) a: VS > VSthF b: VS < VSthU c: Bus wake-up event d: Wake up from WAKE or KL_15 pin Fail-safe Mode VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF Watchdog: ON Silent Mode VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF Watchdog: OFF Sleep Mode VCC: switched off Communication: OFF Watchdog: OFF Go to silent command a TXD = 0 EN = 0 TXD = 1 EN = 0 EN = 1EN = 1 EN = 1 b b b c + d + ee c + d b Normal Mode VCC: 3.3V/5V/50 mA with undervoltage detection watchdog: ON High level at pin SP_MODE: High-speed Mode Transceiver ≤ 115 kBaud LIN 2.1 Transceiver ≤ 20 kBaud TXD time-out timer on Go to sleep command e: NRES switches to low Go to normal command Table 4-1. Table of Modes Mode of Operation Transceiver Pin LIN V CC Pin Mode Watchdog Pin WD_OSC Pin INH Unpowered Off Recessive On GND On On Off Fail-safe Off Recessive 3.3V/5V GND On 1.23V On Normal/ High-speed On TXD depending 3.3V/5V GND On 1.23V On Silent Off Recessive 3.3V/5V GND Off 0V Off Sleep Off Recessive 0V GND Off 0V Off

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

4.1 Normal Mode

This is the normal transmitting and receiving mode. The voltage regulator is active and can source up to 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode.

4.2 Silent Mode

A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (see Figure 4-2 on page 9). The transmission path is disabled in Silent Mode. The INH output is switched off and the voltage divider is enabled. The overall supply current from V Batt is a combination of the I VSsi = 40 µA plus the VCC regulator output current IVCC. The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode to minimize the current consump- tion in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between the LIN pin and the VS pin is present. Silent Mode can be activated indepen- dently from the actual level on the LIN, WAKE, or KL_15 pins . If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. Figure 4-2. Switch to Silent Mode Delay time silent mode td_silent = maximum 20 µs Mode select window LIN switches directly to rece ssive mode td = 3.2 µs LIN VCC NRES TXD EN Normal Mode Silent Mode

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

4.3 Sleep Mode

A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4 on page 11). In order to avoid any influ- ence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 µs earlier to Low than the TXD. Therefore, the best an easiest way are two falling edges at TXD and EN at the same time. The transmission path is disabled in Sleep Mode. The supply current I VSsleep from VBatt is typically 10 µA. The INH output, the PV output and the VCC regulator are switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between the LIN pin and the VS pin is present. Sleep Mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. Figure 4-4. Switch to Sleep Mode Delay time sleep mode td_sleep = maximum 20 µs LIN switches directly to rece ssive mode td = 3.2 µs LIN VCC NRES TXD EN Sleep Mode Normal Mode Mode select window

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t bus ) and a rising edge at pin LIN result in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode. The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcon- troller (see Figure 4-5 on page 12). EN high can be used to switch directly from Sleep/Silent to Fail-safe Mode. If EN is still high after VCC ramp up and undervoltage reset time, the IC switches to the Normal Mode. Figure 4-5. LIN Wake Up from Sleep Mode Regulator wake-up time Off state On state Low Fail-safe Mode Normal Mode EN High Microcontroller Reset time Low or floating Floating Watchdog NRES EN VCC voltage regulator RXD LIN bus Bus wake-up filtering time tbus TXD Watchdog off Start watchdog lead time td start-up time delay

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

4.4 Sleep or Silent Mode: Behavior at a Floating LIN-bus or a Short Circuited LIN to GND

In Sleep or in Silent Mode the device has a very low current consumption even during short-circuits or floating condi tions on the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., if it is switched off when the LIN- Master is in sleep mode or even if the power supply of the Master node is switched off. In order to minimize the current consumption IVS in sleep or silent mode during voltage levels at the LIN-pin below the LIN pre-wake threshold, th e receiver is activated only for a specific time tmon. If t mon elapses while the voltage at the bus is lower than Pre-wake detection low (V LINL) and higher than the LIN dominant level, the receiver is switched off again and the circuit changes back to sleep respectively Silent Mode. The current consumption is then the result of IVSsleep or IVSsilent plus ILINwake. If a dominant state is reached on the bus no wake-up will occur. Even if the voltage rises above the Pre-wake detection high (V LINH), the IC will stay in sleep respectively silent mode (see Figure 4-6). This means the LIN-bus must be above the Pre-wake detection threshold V LINH for a few micro- seconds before a new LIN wake-up is possible. Figure 4-6. Floating LIN-bus During Sleep or Silent Mode If the ATA6628/ATA6630 is in Sleep or Silent Mode and the voltage level at the LIN-bus is in dominant state (VLIN < VBUSdom) for a time period exceeding tmon (during a short circuit at LIN, for example), the IC switches back to Sleep Mode respectively Silent Mode. The V S current consumption then consists of IVSsleep or IVSsilent plus ILINWAKE. After a positive edge at pin LIN the IC switches directly to Fail-safe Mode (see Figure 4-7 on page 14). IVSsleep/silent IVSsleep IVSfail + ILINwake IVSsleep VBUSdom VLINL IVS tmon LIN Pre-wake LIN dominant state LIN BUS Mode of operation Int. Pull-up Resistor RLIN Wake-up Detection Ph ase off (disabled) Sleep/Silent Mode Sleep/Silent Mode

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 4-7. Short Circuit to GND on the LIN bus During Sleep- or Silent Mode Sleep/Silent Mode IVSsleep/silent IVSfail + ILINwake IVSsleep/silent VBUSdom VLINL LIN Pre-wake LIN dominant state LIN BUS IVS Mode of operation Int. Pull-up Resistor RLIN off (disabled) on (en abled) Wake-up Detection Ph aseSleep/Silent Mode F ail-Safe Mode tmon tmon

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

4.5 Fail-safe Mode

The device automatically switches to Fail-safe Mode at syst em power-up. The voltage regulator is switched on (V CC = 3.3V/5V/2%/50 mA) (see Figure 5-1 on page 19 ). The NRES output switches to low for t res = 4 ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of V Batt (VS <V SthU) during Silent or Sleep Mode switches the IC into Fail-safe Mode after power up. A low at NRES switches into Fail-safe Mode directly. During Fail-safe Mode, the TXD pin is an output and signals the fail-safe source. The watchdog is switched on. The LIN SBC can operate in different Modes, like Normal, Silent, or Sleep Mode. The functional- ity of these modes is described in Table 4-2. A wake-up event from either Silent or Sleep Mode will be signalled to the microcontroller using the two pins RXD and TXD. The coding is shown in Table 4-3. A wake-up event will lead the IC to the Fail-safe Mode. Table 4-2. TXD, RXD Depending from Operation Modes Different Modes TXD RXD Fail-safe Mode Signalling fail-safe sources (see Table 4-3 and Table 4-4) Normal Mode Follows data transmission Silent Mode High High Table 4-3. Signalling Fail-safe Sources Fail-safe Sources TXD RXD LIN wake-up (pin LIN) Low Low Local wake-up (at pin Wake, pin KL15) Low High VS th (battery) undervoltage detection High Low Table 4-4. Signalling in Fail-safe Mode after Reset (NRES was Low), Shows the Reset Source at TXD and RXD Pins Fail-safe Sources TXD RXD VCC undervoltage at NRES High Low Watchdog reset at NRES High High

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

4.6 Unpowered Mode

If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 5-1 on page 19 ). After VS is higher than the VS undervoltage threshold VS th, the IC mode changes from Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after t VCC. This time, t VCC, depends on the VCC capacitor and the load. The NRES is low for the reset time delay t reset . During this time, t reset , no mode change is possible. IF VS drops below VSth, then the IC switches to Unpowered Mode. The behavior of VCC, NRES and LIN is shown in Figure 4-8. The watchdog needs to be triggered. Figure 4-8. VCC versus VS for the VCC = 3.3V Regulator

4.7 High-speed Mode

If SP_MODE pin is high and the IC is in Normal Mode, the slew rate control is switched off. The slope time of the LIN falling edge is t S_Fall < 2 µs. The slope time of the LIN rising edge strongly depends on the LIN capacitive and resistive load. To achieve a high baud rate it is recom- mended to use a small resistor (500 Ω) and a low capacitor. This allows very fast data transmission up to 115 kBaud, e.g., for electr onic control (ECU) tests and microcontroller program or data download. In this mode superior EMC performance is not guaranteed. 0. 0 0. 5 1.0 1.5 2. 0 2. 5 3. 0 3. 5 4. 0 4. 5 5.0 5.5 6. 0 VS in V V in V VCC LIN NRES VS Regulator drop voltage VD

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 5. Wake-up Scenarios from Silent or Sleep Mode

5.1 Remote Wake-up via Dominant Bus State

A voltage less than the LIN Pre_Wake detection V LINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level V BUSdom maintained for a certain time period (t BUS) and a rising edge at pin LIN result in a remote wake-up request. A remote wake-up from Silent Mode is only possible if TXD is high. The device switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and the internal slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller and a strong pull down at TXD.

5.2 Local Wake-up via Pin WAKE

A falling edge at the WAKE pin followed by a low level maintained for a certain time period (tWAKE) results in a local wake-up request. The device switches to Fail-safe Mode. The internal slave termination resistor is switched on. The local wake-up request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. When the Wake pin is low, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high > 10 µs before the negative edge at WAKE starts a new local wake-up request.

5.3 Local Wake-up via Pin KL_15

A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> t KL_15) results in a local wake-up request. The device switches into the Fail-safe Mode. The internal slave termination resistor is switched on. The extra long wake-up time ensures that no transients at KL_15 create a wake-up. The local wake-up request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. During high-level voltage at pin KL_15, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to low > 250 µs before the positive edge at KL_15 starts a new local wake-up request. With external RC combination, the time is even longer.

5.4 Wake-up Source Recognition

The device can distinguish between different wake-up sources (see Table 4-4 on page 15). The wake-up source can be read on the TXD and RXD pin in Fail-safe Mode. These flags are immediately reset if the microcontr oller sets the EN pin to high (see Figure 4-3 on page 10 and Figure 4-5 on page 12) and the IC is in Normal mode.

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

5.5 Fail-safe Features

 During a short-circuit at LIN to V Battery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator works independently.  During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode and even in this case the current consumption is lower than 45 µA in Sleep Mode and lower than 80 µA in Silent Mode. If the short-circuit disappears, the IC starts with a remote wake-up.  Sleep or Silent Mode: During a floating condition on the bus the IC switches back to Sleep Mode/Silent Mode automatically and thereby the current consumption is lower than 45 µA/80 µA.  The reverse current is < 2 µA at the LIN pin during loss of V Batt. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition.  During a short circuit at VCC, the output limits the output current to I VCClim. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller if NRES is connected to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the value T VCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of the Fail-safe Mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start with its normal operation.  EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.  RXD pin is set floating if VBatt is disconnected.  TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.  If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE  If the WD_OSC pin has a short-circuit to GND and the NTRIG Signal has a period time > 27 ms a reset is guaranteed.  If the resistor at the WD_OSC pin is disconnected and the NTRIG Signal has a period time < 46 ms a reset is guaranteed.  If there is no NTRIG signal and a short-circuit at WD_OSC to GND the NRES switches to low after 90 ms. For an open circuit (no resistor) at WD_OSC it switches to low after 390 ms.

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

5.6 Voltage Regulator

The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current I VCC, which is needed for the application. In Figure 5-2 on page 19 the safe operating area of the ATA6628/ATA6630 is shown. Figure 5-1. VCC Voltage Regulator: Ramp-up and Undervoltage Detection Figure 5-2. Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 35 K/W For microcontroller programming, it may be necessary to supply the VCC output via an external power supply while the V S Pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip. NRES 5V/3.3V t t t VS 5V/3.3V Vthun Tres_fTResetTVCC 5.5V/3.8V 12V VCC 3 0 3 5791 1 1 3 15 17 19 VS/V IVCC/mA Tamb = 125°C Tamb = 105°C

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 6. Watchdog The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of T wd . The trigger signal must exceed a minimum time ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34 kΩ to 120 kΩ). During Silent or Sleep Mode the watchdog is switched off to reduce current consumption. The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as lead time t d. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output.

6.1 Typical Timing Sequence with RWD_OSC = 51 kΩ

The trigger signal T wd is adjustable between 20 ms and 64 ms using the external resistor RWD_OSC. For example, with an external resistor of R WD_OSC = 51 kΩ ±1%, the typical parameters of the watchdog are as follows: tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ ; tosc in µs) tOSC = 19.6 µs due to 51 kΩ td = 7895 × 19.6 µs = 155 ms t1 = 1053 × 19.6 µs = 20.6 ms t2 = 1105 × 19.6 µs = 21.6 ms tnres = constant = 4 ms After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time t reset (typically 4 ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead time, t d, follows the reset and is td = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG occurs during this time, the time t 1 starts immediately. If no trigger signal occurs during the time t d, a watchdog reset with t NRES = 4 ms will reset the microcontroller after td = 155 ms. The times t1 and t2 have a fixed relationship. A triggering signal from the microcon- troller is anticipated within the time frame of t2 = 21.6 ms. To avoid false triggering from glitches, the trigger pulse must be longer than t TRIG,min > 200 ns. This slope serves to restart the watch- dog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed window t1 immediately switches NRES to low.

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 6-1. Timing Sequence with RWD_OSC = 51 kΩ

6.2 Worst Case Calculation with R WD_OSC = 51 kΩ

The internal oscillator has a tolerance of 20%. This means that t 1 and t2 can also vary by 20%. The worst case calculation for the watchdog period twd is calculated as follows. The ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t2. t1,min = 0.8 × t1 = 16.5 ms, t1,max = 1.2 × t1 = 24.8 ms t2,min = 0.8 × t2 = 17.3 ms, t2,max = 1.2 × t2 = 26 ms twdmax = t1min + t2min = 16.5 ms + 17.3 ms = 33.8 ms twdmin = t1max = 24.8 ms twd = 29.3 ms ±4.5 ms (±15%) A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly. tnres = 4 ms Undervoltage Reset Watchdog Reset treset = 4 ms ttrig > 200 ns t1 = 20.6 ms t2 = 21 ms t2t1 twd td = 155 ms VCC 3.3V/5V NTRIG NRES Table 6-1. Typical Watchdog Timings RWD_OSC kΩ Oscillator Period tosc/µs Lead Time td/ms Closed Window t1/ms Open Window t2/ms Trigger Period from Microcontroller twd/ms Reset Time tnres/ms 34 13.3 105 14.0 14.7 19.9 4

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Typ. Max. Unit Supply voltage V S VS –0.3 +40 V Pulse time ≤ 500 ms Ta = 25°C Output current IVCC ≤ 50 mA VS +40 V Pulse time ≤ 2m i n Ta = 25°C Output current IVCC ≤ 50 mA VS 27 V WAKE (with 2.7 kΩ serial resistor) KL_15 (with 47 kΩ/100 nF) VBATT (with 47Ω/10 nF) DC voltage Transient voltage due to ISO7637 (coupling 1 nF) –150 +40 +100 V V INH - DC voltage –0.3 V S + 0.3 V LIN, VBATT - DC voltage –27 +40 V Logic pins (RxD, TxD, EN, NRES, NTRIG, WD_OSC, MODE, TM, DIV_ON, SP_MODE, PV) –0.3 VCC + 0.5V V Output current NRES I NRES +2 mA PVCC DC voltage VCC DC voltage –0.3 –0.3 +5.5 +6.5 V V ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (2.7 kΩ, serial resistor) to GND - Pin VBATT (10 nF) to GND ±6 KV HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) MIL-STD-883 (M3015.7) ±3 KV CDM ESD STM 5.3.1 ±750 V MM ESD EIA/JESD22-A115 ESD STM5.2 AEC-Q100 (002) ±200 V ESD HBM following STM5.1 with 1.5 kΩ 100 pF - Pin VS, LIN, WAKE to GND ±6 KV Junction temperature T j –40 +150 °C Storage temperature T s –55 +150 °C

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 8. Thermal Characteristics Parameters Symbol Min. Typ. Max. Unit Thermal resistance junction to heat slug R thjc 10 K/W Thermal resistance junction to ambient, where heat slug is soldered to PCB according to Jedec Rthja 35 K/W Thermal shutdown of VCC regulator 150 165 170 °C Thermal shutdown of LIN output 150 165 170 °C Thermal shutdown hysteresis 10 °C 9. Electrical Characteristics 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 VS Pin

1.1 Nominal DC voltage range VS V S 52 7 V A

1.2 Supply current in Sleep

VLIN > VS – 0.5V VS < 14V VS I VSsleep 31 0 1 4 µ A A Sleep Mode, VLIN = 0V Bus shorted to GND VS < 14V VS I VSsleep_short 61 7 3 0 µ A A

1.3 Supply current in Silent

VS < 14V (Tj = 25°C) Without load at VCC VS I VSsi 20 35 45 µA A Bus recessive VS < 14V (Tj = 125°C) Without load at VCC VS I VSsi 25 40 50 µA A Silent Mode VS < 14V Bus shorted to GND Without load at VCC VS I VSsi_short 25 50 80 µA A

1.4 Supply current in Normal

VS < 14V Without load at VCC VS I VSrec 0.3 0.8 mA A

1.5 Supply current in Normal

VS < 14V VCC load current 50 mA VS I VSdom 50 53 mA A

1.6 Supply current in Fail-safe

Bus recessive, RXD is low VS < 14V Without load at VCC for ATA6628 for ATA6630 VS VS I VSfail IVSfail 1.0 1.5 1.5 2.0 mA mA A A 1.7 VS undervoltage threshold Switch to Unpowered Mode VS V SthU 44 . 2 4 . 4 V A Switch to Fail-safe Mode VS V SthF 4.3 4.5 4.9 V A

1.8 VS undervoltage threshold

hysteresis VS V Sth_hys 0.3 V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

2 RXD Output Pin

2.1 Low-level output sink

VLIN =0 V VRXD =0 . 4 V RXD I RXD 1.3 2.5 8 mA A 2.2 Low-level output voltage I RXD = 1 mA RXD V RXDL 0.4 V A

2.3 Internal resistor to PVCC RXD R RXD 357 k Ω A

3 TXD Input/Output Pin

3.1 Low-level voltage input TXD V TXDL –0.3 +0.8 V A

3.2 High-level voltage input TXD V TXDH 2 VCC +

0.3V VA

3.3 Pull-up resistor V TXD =0 V T X D R TXD 125 250 400 k Ω A

3.4 High-level leakage current V TXD =V CC TXD I TXD –3 +3 µA A

3.5 Low-level output sink

Fail-safe Mode, wake up VLIN = VS VWAKE = 0V VTXD = 0.4V TXD I TXDwake 22 . 58 m A A

4 EN Input Pin

4.1 Low-level voltage input EN V ENL –0.3 +0.8 V A

4.2 High-level voltage input EN V ENH 2 VCC +

0.3V VA

4.3 Pull-down resistor V EN = VCC EN R EN 50 125 200 k Ω A

4.4 Low-level input current V EN = 0V EN I EN –3 +3 µA A

5 NTRIG Watchdog Input Pin

5.1 Low-level voltage input NTRIG V NTRIGL –0.3 +0.8 V A

5.2 High-level voltage input NTRIG V NTRIGH 2 VCC +

0.3V VA

5.3 Pull-up resistor V NTRIG = 0V NTRIG R NTRIG 125 250 400 k Ω A

5.4 High-level leakage current V NTRIG = VCC NTRIG I NTRIG –3 +3 µA A

6.1 Low-level voltage input MODE V MODEL –0.3 +0.8 V A

6.2 High-level voltage input MODE V MODEH 2 VCC +

0.3V VA

6.3 High-level leakage current VMODE = VCC or

VMODE = 0V MODE I MODE –3 +3 µA A

7 INH Output Pin

7.1 High-level voltage I INH = –15 mA INH V INHH VS – 0.75 V S VA

7.2 Switch-on resistance

between VS and INH INH R INH 30 50 Ω A

7.3 Leakage current Sleep Mode

VINH = 0V/27V, VS = 27V INH I INHL –3 +3 µA A

8 LIN Bus Driver

8.1 Driver recessive output

voltage Load1/Load2 LIN V BUSrec 0.9 × VS VS VA

8.2 Driver dominant voltage VVS = 7V

Rload = 500 Ω LIN V _LoSUP 1.2 V A 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

8.3 Driver dominant voltage VVS = 18V

Rload = 500 Ω LIN V _HiSUP 2V A 8.4 Driver dominant voltage VVS = 7.0V Rload = 1000 Ω LIN V _LoSUP_1k 0.6 V A

8.5 Driver dominant voltage VVS = 18V

Rload = 1000 Ω LIN V _HiSUP_1k 0.8 V A

8.6 Pull-up resistor to VS The serial diode is

mandatory LIN R LIN 20 30 47 k Ω A

8.7 Voltage drop at the serial

In pull-up path with Rslave ISerDiode =1 0m A LIN V SerDiode 0.4 1.0 V D

8.8 LIN current limitation

VBUS = VBatt_max LIN I BUS_LIM 70 120 200 mA A 8.9 Input leakage current at the receiver including pull-up resistor as specified Input leakage current Driver off V BUS = 0V VBatt = 12V LIN I BUS_PAS_dom –1 –0.35 mA A

8.10 Leakage current LIN

8V < VBatt < 18V 8V < VBUS < 18V VBUS ≥ VBatt LIN I BUS_PAS_rec 10 20 µA A 8.11 Leakage current at GND loss, control unit disconnected from ground. Loss of local ground must not affect communication in the residual network. GND Device = VS VBatt = 12V 0V < VBUS < 18V LIN I BUS_NO_gnd –10 +0.5 +10 µA A 8.12 Leakage current at loss of battery. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition. V Batt disconnected VSUP_Device = GND 0V < VBUS < 18V LIN I BUS_NO_bat 0.1 2 µA A

8.13 Capacitance on pin LIN to

9 LIN Bus Receiver

9.1 Center of receiver

VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN V BUS_CNT 0.475 × VS 0.5 × VS 0.525 × VS VA 9.2 Receiver dominant state V EN = VCC LIN V BUSdom 0.4 × VS VA 9.3 Receiver recessive state V EN = VCC LIN V BUSrec 0.6 × VS VA

9.4 Receiver input hysteresis V hys = Vth_rec – Vth_dom LIN V BUShys

0.028 × VS 0.1 × VS 0.175 × VS VA

9.5 Pre_Wake detection LIN

High-level input voltage LIN V LINH VS – 2V V S + 0.3V V A

9.6 Pre_Wake detection LIN

Low-level input voltage Activates the LIN receiver LIN V LINL –27 V S – 3.3V V A 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

10 Internal Timers

10.1 Dominant time for

wake-up via LIN bus VLIN = 0V LIN t bus 30 90 150 µs A 10.2 Time delay for mode change from Fail-safe into Normal Mode via EN pin V EN = VCC EN t norm 51 5 2 0 µ s A 10.3 Time delay for mode change from Normal Mode to Sleep Mode via EN pin V EN = 0V EN t sleep 27 1 2 µ s A

10.4 TXD dominant time-out

time VTXD = 0V TXD t dom 27 55 70 ms A 10.5 Time delay for mode change from Silent Mode into Normal Mode via EN V EN = VCC EN t s_n 51 5 4 0 µ s A

10.6 Monitoring time for

wake-up over LIN bus LIN t mon 61 0 1 5 m s A LIN Bus Driver AC Parameter with Different Bus Loads Load 1 (small): 1 nF , 1 kΩ ; Load 2 (large): 10 nF , 500Ω ; RRXD =5k Ω; CRXD =2 0p F ; Load 3 (medium): 6.8 nF , 660Ω characterized on samples; 10.7 and 10.8 specifies the timing parameters for proper operation of 20 Kbit/s, 10.9 and 10.10 at 10.4 Kbit/s

10.7 Duty cycle 1

THRec(max) = 0.744 × VS THDom(max) = 0.581 × VS VS = 7.0V to 18V tBit = 50 µs D1 = tbus_rec(min)/(2 × tBit) LIN D1 0.396 A

10.8 Duty cycle 2

THRec(min) = 0.422 × VS THDom(min) = 0.284 × VS VS = 7.6V to 18V tBit = 50 µs D2 = tbus_rec(max)/(2 × tBit) LIN D2 0.581 A

10.9 Duty cycle 3

THRec(max) = 0.778 × VS THDom(max) = 0.616 × VS VS = 7.0V to 18V tBit = 96 µs D3 = tbus_rec(min)/(2 × tBit) LIN D3 0.417 A

10.10 Duty cycle 4

THRec(min) = 0.389 × VS THDom(min) = 0.251 × VS VS = 7.6V to 18V tBit = 96 µs D4 = tbus_rec(max)/(2 × tBit) LIN D4 0.590 A

10.11 Slope time falling and

rising edge at LIN VS = 7.0V to 18V LIN tSLOPE_fall tSLOPE_rise 3.5 22.5 µs A 11 Receiver Electrical AC Parameters of the LIN Ph ysical Layer, LIN Receiver, RXD Load Conditions (CRXD): 20 pF

11.1 Propagation delay of

receiver (Figure 9-1) VS = 7.0V to 18V trx_pd = max(trx_pdr , trx_pdf) RXD t rx_pd 6µ s A 11.2 Symmetry of receiver propagation delay rising edge minus falling edge V S = 7.0V to 18V trx_sym = trx_pdr – trx_pdf RXD t rx_sym –2 +2 µs A 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

12 NRES Open Drain Output Pin

12.1 Low-level output voltage VS ≥ 5.5V INRES = 1 mA NRES V NRESL 0.14 V A

12.2 Low-level output low 10 kΩ to 5V

VCC = 0V NRES V NRESLL 0.14 V A 12.3 Undervoltage reset time VS ≥ 5.5V CNRES = 20 pF NRES t reset 246 m s A

12.4 Reset debounce time for

VS ≥ 5.5V CNRES = 20 pF NRES t res_f 1.5 10 µs A 12.5 Switch off leakage current V NRES = 5.5V NRES –3 +3 µA A

13 Watchdog Oscillator

13.1 Voltage at WD_OSC in

IWD_OSC = –200 µA VVS ≥ 4V WD_OSC V WD_OSC 1.13 1.23 1.33 V A

13.2 Possible values of resistor Resistor ±1% WD_OSC R OSC 34 120 k Ω A

13.3 Oscillator period R OSC = 34 kΩ tOSC 10.65 13.3 15.97 µs A 13.4 Oscillator period R OSC = 51 kΩ tOSC 15.68 19.6 23.52 µs A 13.5 Oscillator period R OSC = 91 kΩ tOSC 26.83 33.5 40.24 µs A 13.6 Oscillator period R OSC = 120 kΩ tOSC 34.2 42.8 51.4 µs A

14 Watchdog Timing Relative to t OSC

14.1 Watchdog lead time after

14.2 Watchdog closed window t 1 1053 cycles A

14.3 Watchdog open window t 2 1105 cycles A

14.4 Watchdog reset time

NRES NRES t nres 3 . 244 . 8 m s A

15 KL_15 Pin

15.1 High-level input voltage

RV = 47 kΩ Positive edge initializes a wake-up KL_15 V KL_15H 4V S + 0.3V V A

15.2 Low-level input voltage

RV = 47 kΩ KL_15 V KL_15L –1 +2 V A

15.3 KL_15 pull-down current VS < 27V

VKL_15 = 27V KL_15 I KL_15 50 60 µA A

15.4 Internal debounce time Without external capacitor KL_15 Tdb KL_15 80 160 250 µs A

15.5 KL_15 wake-up time R V = 47 kΩ , C = 100 nF KL_15 Tw KL_15 0 . 424 . 5 m s C

16 WAKE Pin

16.1 High-level input voltage WAKE V WAKEH VS – 1V V S + 0.3V V A 16.2 Low-level input voltage Initializes a wake-up signal WAKE V WAKEL –1 V S – 3.3V V A

16.3 WAKE pull-up current V S < 27V, VWAKE = 0V WAKE I WAKE –30 –10 µA A

16.4 High-level leakage current V S = 27V, VWAKE = 27V WAKE I WAKEL –5 +5 µA A

16.5 Time of low pulse for

wake-up via WAKE pin VWAKE = 0V WAKE I WAKEL 30 70 150 µs A 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

17 VCC Voltage Regulator ATA6628 in Normal/Fail-sa fe and Silent Mode, VCC and PVCC Short-circuited

17.1 Output voltage VCC 4V < VS < 18V

(0 mA to 50 mA) VCC VCC nor 3.234 3.366 V A

17.2 Output voltage VCC at low

VS 3V < VS < 4V VCC VCC low VS – VD 3.366 V A

17.3 Regulator drop voltage V S > 3V, IVCC = –15 mA VS, VCC V D 200 mV A

17.4 Regulator drop voltage V S > 3V, IVCC = –50 mA VS, VCC V D 500 700 mV A

17.5 Line regulation 4V < V S < 18V VCC VCC line 0.1 0.2 % A 17.6 Load regulation 5 mA < I VCC < 50 mA VCC VCC load 0.1 0.5 % A

17.7 Power supply ripple

10 Hz to 100 kHz

CVCC = 10 µF VS = 14V, IVCC = –15 mA VCC 50 dB D

17.8 Output current limitation V S > 4V VCC I VCClim –240 –160 –85 mA A

17.9 Load capacity 0.2Ω < ESR < 5Ω at 100 kHz VCC C load 1.8 10 µF D

17.10 VCC undervoltage

VS > 4V VCC V thunN 2.8 3.2 V A

17.11 Hysteresis of

VS > 4V VCC Vhys thun 150 mV A

17.12 Ramp-up time VS > 4V to

VCC = 3.3V CVCC = 2.2 µF Iload = –5 mA at VCC VCC T VCC 320 500 µs A

18 VCC Voltage Regulator ATA6630 in Normal/Fail-sa fe and Silent Mode, VCC and PVCC Short-circuited

18.1 Output voltage VCC 5.5V < VS < 18V (0 mA to 50 mA) VCC VCC nor 4.9 5.1 V A

18.2 Output voltage VCC at low

VS 4V < VS < 5.5V VCC VCC low VS – VD 5.1 V A

18.3 Regulator drop voltage V S > 4V, IVCC = –20 mA VS, VCC V D1 250 mV A

18.4 Regulator drop voltage V S > 4V, IVCC = –50 mA VS, VCC V D2 400 600 mV A

18.5 Regulator drop voltage V S > 3.3V, IVCC = –15 mA VS, VCC V D3 200 mV A 18.6 Line regulation 5.5V < V S < 18V VCC VCC line 0.1 0.2 % A

18.7 Load regulation 5m A < IVCC < 50 mA

100 kHz VCC VCC load 0.1 0.5 % A

18.8 Power supply ripple

CVCC = 10 µF VS = 14V, IVCC = –15 mA VCC 50 dB D 18.9 Output current limitation VS > 5.5V VCC I VCClim –240 –130 –85 mA A 18.10 Load capacity 0.2Ω < ESR < 5Ω at 100 kHz VCC V thunN 1.8 10 µF D

18.11 VCC undervoltage

VS > 5.5V VCC V thunN 4.2 4.8 V A

18.12 Hysteresis of

VS > 5.5V VCC Vhys thun 250 mV A 18.13 Ramp-up time VS > 5.5V to VCC = 5V CVCC = 2.2 µF Iload = –5 mA at VCC VCC t VCC 370 600 µs A 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary]

19 DIV_ON Input Pin

19.1 Low-level voltage input DIV_ON V DIV_ON –0.3 +0.8 V A 19.2 High-level voltage input DIV_ON V DIV_ON 2V CC + 0.3 V A

19.3 Pull-down resistor V DIV_ON = VCC DIV_ON R DIV_ON 125 250 400 k Ω A

19.4 Low-level input current V DIV_ON = 0V DIV_ON I DIV_ON –3 +3 µA A

20 SP_MODE Input Pin

20.1 Low-level voltage input SP_MODE V SP_MODE –0.3 +0.8 V A 20.2 High-level voltage input SP_MODE V SP_MODE 2V CC + 0.3 V A

20.3 Pull-down resistor V SP_MODE = VCC SP_MODE R SP_MODE 50 125 200 k Ω A

20.4 Low-level input current V SP_MODE = 0V SP_MODE I SP_MODE –3 +3 µA A

21 LIN Driver in High-speed Mode(VSP_Mode = VCC)

21.1 Transmission Baud rate VS = 7V to 18V

RLIN = 500Ω , CLIN =6 0 0p F LIN SP 115 kBaud C

21.2 Slope time LIN falling

edge VS = 7V to 18V LIN t SL_fall 12 µ s A 21.3 Slope time LIN rising edge, depending on RC-load V S = 14V RLIN = 500Ω , CLIN =6 0 0p F LIN t SL_rise 23 µ s A

22 ATA6628 Voltage Divider

22.1 Divider ratio VS = 5V to 18V PV 1:6 A

22.2 Divider ratio error –2 +2 % A

22.3 Divider temperature drift 3 ppm/°C C

22.4 VBATT range of divider

22.5 VBatt input current VBATT = 14V VBATT 100 220 µA A

22.6 Maximum output Voltage

at PV VBATT 18V to 40V VBATT 3 3.1 3.5 V A

22.7 Pin capacitance PV 2 pF

23 ATA6630 Voltage Divider

23.1 Divider ratio VS = 5V to 27V PV 1:6 A

23.2 Divider ratio error –2 +2 % A

23.3 Divider temperature drift 3 ppm/°C C

23.4 VBATT range of divider

23.5 VBatt input current VBATT = 14V VBATT 100 220 µA A

23.6 Maximum output Voltage

at PV VBATT 27V to 40V PV 4.4 4.8 5.2 V A

23.7 Pin capacitance PV 2 pF

1. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 9-1. Definition of Bus Timing Characteristics TXD (Input to transmitting node) VS (Transceiver supply of transmitting node) RXD (Output of receiving node1) RXD (Output of receiving node2) LIN Bus Signal Thresholds of receiving node1 Thresholds of receiving node2 tBus_rec(max) trx_pdr(1) trx_pdf(2)trx_pdr(2) trx_pdf(1) tBus_dom(min) tBus_dom(max) THRec(max) THDom(max) THRec(min) THDom(min) tBus_rec(min) tBit tBittBit

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 9-2. Typical Application Circuit 67 8 109 20 19 1 8 MLP 5 mm 5 mm 0.65 mm pitch 20 lead ATA6628 ATA6630 INH TXD NRES LIN sub bus WD_OSC TM Master node pull-up KL_15 MODE PVCC VCC VS DIV_ON PV RXD LIN SP_ GND WAKE Wake switch 51 kΩ 10 kΩ 1 kΩ 2.7 kΩ 47Ω 10 kΩ 47 kΩ 10 kΩ NTRIG EN NTRIG Microcontroller ADC SP_MODE DIV_ON RESET TXD RXD EN VCC INH Ignition KL15 KL30 VBattery VBATT debug 220 pF 100 nF10 µF + 100 nF 10 nF 10 µF 100 nF MODE GND

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 9-3. Application Circuit with External NPN-Transistor 67 8 109 20 19 1 8 QFN 5x5 mm 0.65 mm pitch 20 lead ATA6628/ ATA6630 TXD INH NRES LIN Sub Bus WD_OSC TM Master node pull-up MODE PVCC KL_15 VCC VS PV SP_MODE LIN RXD DIV_ON GND WAKE Wake switch 51 kΩ 10 kΩ 1 kΩ 2.7 kΩ 10 kΩ 10 kΩ 47Ω NTRIG NTRIG Microcontroller RESET GND TXD RXD EN VCC INH KL30 VBattery VBATT EN ADC DIV_ON SP_MODE 220 pF 100 nF 22 nF 100 nF 10 µF + 100 nF 10 µF 47 kΩ Debug Ignition KL15 2.2 µF 3.3Ω T1 *) MJD31C *) Note that the output voltage PVCC is no longer short-ciruit protected when boosting the output current by an external NPN-transistor.

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] Figure 9-4. LIN Slave Application with Minimum External Devices 67 8 109 20 19 1 8 16 TXD NRES LIN Sub Bus WD_OSC TM INH KL_15 PVCC VCC MODE VS PV SP_MODE DIV_ON RXD LIN GND EN WAKE 10 kΩ NTRIG Microcontroller RESET TXD GND RXD EN VBATT 220 pF 100 nF VCC VCC VCC 22 µF + 100 nF 10 µF + QFN 5x5 mm 0.65 mm pitch 20 lead ATA6628/ ATA6630 KL30 VBattery Note: No watchdog, no Battery voltage measurement, no loc al wake up, INH output not used

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 11. Package Information 10. Ordering Information Extended Type Number Package Remarks ATA6628-PGPW QFN20 3.3V LIN system-basis-c hip, Pb-free, 1.5k, taped and reeled ATA6630-PGPW QFN20 5V LIN system-basis-chi p, Pb-free, 1.5k, taped and reeled ATA6628-PGQW QFN20 3.3V LIN sy stem-basis-chip, Pb-free, 6k, taped and reeled ATA6630-PGQW QFN20 5V LIN system-basis-c hip, Pb-free, 6k, taped and reeled specifications according to DIN technical drawings Issue: 2; 09.02.07 Drawing-No.: 6.543-5129.01-4 0.2 0.9±0.1 0.65 nom. 16 20 10 6 3.1±0.15 Bottom 2.6 Top Pin 1 identification Package: VQFN_5 x 5_20L Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances ±0.05 0.6±0.1 0.28±0.07 0.05-0.05

9117E–AUTO–07/10 ATA6628/ATA6630 [Preliminary] 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9117E-AUTO-07/10 • Section 6 “Watchdog” on pages 20 to 21 changed 9117D-AUTO-05/10

• Features on page 1 changed
• Pin Description table: row Pin 16 changed
• Figures 4-5, 6-1 changed
• Figure 9-1 heading changed
• Figures 9-2 and 9-3 added
• El.Char.Table -> row 8.13 added 9117C-AUTO-10/09
• Complete datasheet: “LIN 2.1 specicfication” changed in “LIN 2.0, 2.1 specicfication or “2.x”
• Features on page 1 changed
• Description text on page 1 changed
• Pin Descritption table rows changed: 8, 11, 12
• Sections changed:
• New section 4.4 added (the following section numbers automatically changes...)
• Table Abs. Max. Ratings: changes in following rows: WAKE, INH - DC voltage, ESD HBM following STM5.1
• Table El. Characteristics: changes in folloring rows: new rows 10.6, 12.5, 18.8 added (the following counting changed) row 20.5 deleted
• Figure heading changed: 4-7
• Figures changed: 1-1, 4-3, 4-4, 4-5, 4-6, 4-7, 9-2
• Table headings changed: 3-1

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