ATA6621

ATA6621_06 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 27

Technical content

Features

• Supply Voltage up to 40V  Operating Voltage VS = 5V to 18V  Slew Rate Control according to LIN Specification 2.0  Supply Current during Sleep Mode Typically 10 µA  Supply Current in Silent Mode Typically 40 µA  Linear Low-drop Voltage Regulator: – Normal Mode: V CC = 5V ±2%/50 mA – Silent Mode: V CC = 5V ±7%/50 mA – Sleep Mode: V CC is Switched Off  VCC Undervoltage Detection (10 ms Reset time) and Watchdog Reset Logically Combined at Output NRES  Possibility of Boosting the Voltage Regulator with an External NPN Transistor  LIN Physical Layer according to LIN Specification 2.0  Wake-up Capability via LIN Bus or WAKE Pin  Wake-up Recognition  TXD Time-out Timer  Debug Mode Watchdog Is Switched Off  60V Load Dump Protection at LIN Pin  Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery  Adjustable Watchdog Time via External Resistor  Positive and Negative Trigger Input for Watchdog  5V CMOS Compatible I/O Pins to MCU  Analog Temperature Monitor Output  High EMC and ESD Level  Package: QFN 5 × 5 with 20 Pins 1. Description The ATA6621 is a fully integrated LIN transceiver, complying with the LIN specifica- tion, and with a low-drop voltage regulator for 5V/50 mA output and a window watchdog adjustable via an external resistor. In this QFN20 package, the voltage reg- ulator is able to source 50 mA at V S = 18V even at an ambient temperature of 105°C. The output current of the regulator can be boosted by using an external NPN transis- tor. This combination makes it possible to develop simple, but powerful and cheap, slave nodes in LIN bus systems. ATA6621 is designed to handle the low speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud. The bus output is capable of withstanding 60V. Sleep Mode and Silent Mode guarantee a very low current consumption. LIN Transceiver with 5V Regulator and Watchdog ATA6621 4887D–AUTO–12/06

4887D–AUTO–12/06 ATA6621 Figure 1-1. Block Diagram VCC VCC VS Adjustable Watchdog Oscillator Short Circuit and Overtemperature ProtectionTXD Time-out Timer Debounce Time Internal Testing Unit Control Unit Slew Rate Control Wake-up Bus Timer Standby Mode Undervoltage Reset Normal Mode 5V ± 2%/50 mA Silent Mode 5V ± 7%/50 mA Filter Watchdog OUT RXD GND GND NTRIGPTRIGTMMODE TEMP EN TXD WAKE Receiver9 VCC VCC Normal Mode LIN WD_OSC NRES PVCC VCC VS

4887D–AUTO–12/06 ATA6621 2. Pin Configuration Figure 2-1. Pinning QFN20 67 8 1 0 9 20 19 18 MLP 5 mm × 5 mm 0.65 mm pitch 20 lead ATA6621 TXD NRES WD_OSC TM MODE GND TEMP PVCC VCC VS NC RXD NC LIN NC GND WAKE NTRIG PTRIG EN Table 2-1. Pin Description Pin Symbol Function

1 EN Enables the device into Normal Mode

2 PTRIG High-level watchdog trigger input from microcontroller; if not needed, leave open or connect to GND 3 NTRIG Low-level watchdog trigger input from microcontr oller; if not needed, leave open or connect to VCC

4 WAKE High-voltage input for local wake-up request; if not needed, connect to VS

5 GND System ground

6 NC Not connected

7 LIN LIN bus line input/output

8 NC Not connected

9 RXD Receive data output

10 NC Not connected

11 TXD Transmit data input; active low output (strong pull down) after a local wake-up request

12 NRES Output undervoltage and watchdog reset

13 WD_OSC External resistor for adjustable watchdog timing

14 TM For factory testing only (tie to ground)

15 MODE For debug mode, high watchdog off, low watchdog on

16 GND Additional ground

17 TEMP Chip temperature output pi n; if not needed connect to GND

18 PVCC 5V regulator sense input pin

19 VCC 5V regulator output/driver pin

20 VS Battery supply

Backside Heat slug is connected to GND (pin 5)

4887D–AUTO–12/06 ATA6621 3. Functional Description

3.1 Supply Pin (VS)

The LIN operating voltage is V S = 5V to 18V. An undervoltage detection is implemented to dis- able transmission if V S falls below 5V in order to avoid false bus messages. In this case the NRES switches to low and the IC enters prenormal mode. After switching on VS, the IC starts with the Pre Normal Mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep Mode is typically 10 µA, and 40 µA in Silent Mode.

3.2 Ground Pin (GND)

The IC is neutral on the LIN pin in case of GND disconnection; it can handle a ground shift up to 3V for supply voltage at the VS pin above 9V.

3.3 Voltage Regulator Output Pin (VCC)

The internal 5V voltage regulator is capable of driving loads with up to 50 mA of current con- sumption; it is able to supply the microcontroller and other ICs on the PCB. It is protected against overloads by means of current limitation and overtemperature shutdown. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if the output voltage drops below a defined threshold V thun. To boost up the maximum load current, an exter- nal NPN transistor may be used with its base connected to the VCC pin and its emitter connected to PVCC.

3.4 Voltage Regulator Sense Pin (PVCC)

This is the sense input pin of the 5V voltage regulator. For normal applications (that is, when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be c onnected to the output of this transistor, its emitter terminal.

3.5 Bus Pin (LIN)

A low side driver with internal current limi tation and thermal shutdown, and an internal pull-up resistor in compliance with LIN specification 2.0 is implemented. This is a self-adapting current limitation; that is, during current limitation, as the chip temperature increases, the current decreases. The allowed voltage range is between –40V and +60V. Reverse currents from the LIN bus to VS are suppressed, even in case of ground shifts or battery disconnection. LIN receiver thresholds are compatible to the LIN protocol specification. The fall time from recessive bus state to dominant, and the rise time from dominant bus state to recessive are slope controlled.

3.6 Input Pin (TXD)

This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor.

4887D–AUTO–12/06 ATA6621

3.7 TXD Dominant Ti me-out Function

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than t DOM >6m s , t h e LIN bus driver is switched to the recessive st ate. To reset this mode switch (> 10 µs) before switching LIN to dominant again.

3.8 Output Pin (RXD)

This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD, LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 k Ω to VCC. The AC characteristics can be defined with an external load capacitor of 20 pF. The output is short-circuit protected. In Unpowered Mode (that is, VS = 0V), RXD is switched off.

3.9 Enable I nput Pin (EN)

This pin controls the operation mode of the interf ace. If EN is high, the interface is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both being active. The VCC voltage regulator is operating with 5V ±2%/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data trans- mission is then possible and the current consumption is reduced to I VS =5 0µ A . T h e c u r r e n t capability of the VCC regulator is also 50 mA, but the VCC tolerance is between 4.65V and 5.35V. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmis- sion is possible and the voltage regulator is switched off.

3.10 Wake Input Pin (WAKE)

This pin is a high voltage input used to wake the device up from Sleep Mode. It is usually con- nected to an external switch in the application to generate a local wake-up. A pull-up current source with typically 10 µA is implemented. If you don’t need a local wake-up in your application, connect pin WAKE directly to pin VS.

3.11 MODE Input Pin

For normal watchdog operation connect pin MODE via an external resistor to GND (see Figure 5-2 on page 23). For debugging your software you can connect pin MODE to 5V and the watch- dog is switched off.

3.12 TM Input Pin

Pin TM is used in final production measurement at Atmel. In the application it is always con- nected to GND.

4887D–AUTO–12/06 ATA6621

3.13 Modes of Operation

Figure 3-1. Modes of Operation

3.13.1 Normal Mode

This is the normal transmitting and receiving mode. The voltage regulator is in normal mode and can source 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from PTRIG or NTRIG to avoid resets at NRES.

3.13.2 Silent Mode

A falling edge at EN while TXD is high switches the IC into Silent Mode . The TXD signal has to be logic high during the Mode Select window (Figure 3-2 on page 7). For EN and TXD either two independent outputs can be used, or two outputs from the same microcontroller port; in the sec- ond case, the mode change is only one command. In Silent Mode, the transmission path is disabled. Supply current from V Bat is typically IVSsi = 40 µA with no load at the VCC regulator. The overall supply current from VBat is the addition of 40 µA plus the VCC regulator output current IVCCs. Pre-normal Mode VCC: 5V/50 mA with undervoltage monitoring Communication: OFF ab Silent Mode VCC: 5V ±7%/50 mA with undervoltage monitoring Communication: OFF EN = 1 Go to silent command EN = 0 TXD = 1 Local wake-up event a: VS > 5V b: VS < 4V c: Bus wake-up event d: NRES switches to low e: Wake-up from wake-up switch b EN = 1 b c + d + e Normal Mode VCC: 5V ±2%/50 mA with undervoltage monitoring Communication: ON Unpowered Mode V Batt = 0 Sleep Mode VCC: switched off Communication: OFF Go to sleep command Local wake-up event EN = 0 TXD = 0 EN = 1 bc + e d

4887D–AUTO–12/06 ATA6621 In Silent Mode, the 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is shorted to GND. Only a weak pu ll-up current (typically 10 µA) between pin LIN and pin VS is present. The Silent Mode voltage tolerance is sufficient to run the internal timers of the microcontroller. The undervoltage reset is now V ccthS < 4.4V. If an undervoltage condition occurs, the NRES is switched to low and the ATA6621 changes state to Pre Normal Mode. A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (Tbus) results in a remote wake-up request. The device switches from Silent Mode to Pre Normal Mode. The internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller. (Figure 3-5 on page 10) With EN high, you can switch directly from Silent Mode to Normal Mode. Figure 3-2. Switch to Silent Mode Delay time Silent Mode Td_sleep = maximum 15 µs Mode Select window LIN switches directly to recessive mode Td = 3.2 µs LIN VCC NRES TXD EN Silent Mode

4887D–AUTO–12/06 ATA6621 Figure 3-3. LIN Wake-up Waveform Diagram (from Silent Mode)

3.13.3 Sleep Mode

The falling edge at EN has to occure not more than tDOMmin = 6 ms after or 3.2 µs before the fall- ing edge at TXD in order to switch the IC into Sleep Mode. The TXD Signal has to stay logic low during the Mode Select window (Figure 3-4 on page 9). See also section “Silent Mode” on page In Sleep Mode the transmission path is disabled. Supply current from V Bat is typically IVSsleep =1 0µ A . T h e VCC regulator is switched off. NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is shorted to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (Tbus) results in a remote wake-up request. The device switches from Sleep Mode to Pre Normal Mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon- troller. (Figure 3-5 on page 10) With EN high you can switch directly from Silent Mode to Normal Mode. In the application where the ATA6621 supplies the microcontroller, wake-up from Sleep Mode is only possible via LIN or pin WAKE. Regulator Wake-up time If undervoltage, switch to Prenormal Mode Undervoltage detection active Silent Mode 5V/7%/50 mA Pre normal Mode 5V/50 mA Normal Mode 5V/50 mA Low Pre Normal Mode Normal Mode High EN High High NRES EN VCC Voltage Regulator RXD LIN bus Bus wake-up filtering time Tbus

4887D–AUTO–12/06 ATA6621 Figure 3-4. Switch to Sleep Mode

3.13.4 Pre Normal Mode

At system power-up the device automatically switches to Pre Normal Mode. The voltage regula- tor is switched on VCC = 5V ±2%/50 mA (see Figure 3-6 on page 12). The NRES output switches to low for t res = 10 ms and sends a reset to the microcontroller. LIN communication is switched off and the watchdog is active. The ATA6621 stays in this mode until EN is switched to high. If VBattery (VS < 4V) is powered down during Silent Mode or Sleep Mode, the IC powers up into Pre Normal Mode.

3.13.5 Unpowered Mode

If you connect battery voltage to the application circuit, the voltage at the VS pin increases due to the block capacitor (Figure 3-6 on page 12). When VS becomes higher than the VS undervolt- age threshold VS_th, the IC mode changes from Unpowered Mode to Pre Normal Mode. The VCC output voltage reaches its nominal value after t VCC. This time depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset. During this time, no mode change is possible.

3.13.6 Debug Mode

The watchdog is switched off with pin MODE high (5V) and in normal operation if it is tied to GND (see Figure 5-2 on page 23). Delay time Sleep Mode Td_sleep = maximum 15 µs Mode Select window LIN switches directly to recessive mode Td = 3.2 µs LIN VCC NRES TXD EN Sleep Mode

4887D–AUTO–12/06 ATA6621 Figure 3-5. LIN Wake-up Waveform Diagram from Sleep Mode Table 3-1. Table of Modes Mode of Operation Transceiver VCC WD_OSC TEMP RXD LIN Pre Normal Off 5V 2.5V 2V 5V RECESSIVE Normal On 5V 2.5V 2V 5V RECESSIVE Silent Off 5V 0V 0V 5V RECESSIVE Sleep Off 0V 0V 0V 0V RECESSIVE Regulator Wake-up time Off state On state Low Pre Normal Mode Normal Mode High EN High Node ln operation Microcontroller start-up time delay Reset time Low or floating Low or floatingNRES EN VCC Voltage Regulator RXD LIN bus Bus wake-up filtering time Tbus

4887D–AUTO–12/06 ATA6621

3.14 Wake-up Scenarios from Silent or Sleep Mode

3.14.1 Remote Wake-up via Dominant Bus State

A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (TBUS) results in a remote wake-up request. The device switches to Pre Normal Mode. The V CC voltage regulator is activated, and the internal slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to generate an interrupt in the microcontroller. The watchdog needs a trigger signal from PTRIG or NTRIG within the lead time t D to avoid resets at NRES. (Figure 3-2 on page 7)

3.14.2 Local Wake-up via Pin Wake

A falling edge at pin WAKE followed by a low level maintained for a certain time period (T WAKE) results in a local wake-up request. The extra long wake-up time (T WAKE) ensures that no tran- sients as defined in ISO7637 create a wake-up. The device switches to Pre Normal Mode. The internal slave termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to generate an interrupt in the microcontroller. The watchdog needs a trigger signal from PTRIG or NTRIG within the lead time t D to avoid resets at NRES.

3.14.3 Wake-up Source Recognition

The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (dominant LIN bus state). The wake-up source can be read on pin TXD in Pre Normal Mode. A high level indicates a remote wake-up request (weak pull down at pin TXD) and a low level indicates a local wake-up request (strong pull down at pin TXD). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately, if the microcontro ller sets pin EN to high ( Figure 3-2 on page 7 and Figure 3-3 on page 8).

3.15 Fail-safe Features

 During a short circuit at LIN, the output limits the output current to I BUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. During LIN overtemperature switch-off, the VCC regulator works independently.  The reverse current at pin LIN is very low (< 3 µA) during loss of VBAT or GND. This is optimal behavior for bus systems where some slave modes are supplied from battery or ignition.  During a short circuit at V CC, the output limits the output current to IVCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Pre Normal Mode. If the chip temperature exceeds the value T VCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of Pre Normal Mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start its normal operation.  Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.  Pin RXD is connected with 5 k Ω to VCC, if VBatt is disconnected VCC is at GND level  Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.  If the WD_OSC pin has a short circuit to GND or the resistor is disconnected, the watchdog oscillator runs with a high frequency and guarantees a reset in any condition.

4887D–AUTO–12/06 ATA6621  The WD_OSC pin is a constant voltage regulator which supplies 2.5V for the external resistor ROSC to adjust the watchdog timing. This output is short circuit protected. A short circuit to GND causes a reset a pin NRES after typically 4 ms. An open circuit causes a reset at pin NRES after typically 7 ms.

3.16 Voltage Regulator

The voltage regulator needs an external capacitor for compensation and to smooth the distur- bances from the microcontroller. It is recommend to use an tantalum capacitor with C > 10 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. During mode change from Silent to Normal Mode, the voltage regulator ramps up to 6V for only a few microseconds before it drops back to 5V. This behavior depends on the value of the load capacitor. With 4.7 µF, the overshoot voltage has its greatest value. This voltage decreases with higher or lower load capacitors. The main power dissipation of the IC is created from the V CC output current I VCC, which is needed for the application. In Figure 3-7 on page 13 you see the safe operating range of the ATA6621. Figure 3-6. VCC Voltage Regulator: Ramp Up and Undervoltage NRES VCC VS t t t Vthun tres_ftrestvcc 5.5V 12V

4887D–AUTO–12/06 ATA6621 Figure 3-7. Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures

3.17 Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) or the PTRIG (positive edge) input within a period time window of T wd. The trigger signal must exceed a minimum time t trigmin > 3 µs. If a triggering signal is not received, a reset signal will be generated at output NRES. The timi ng basis of the watchdog is pr ovided by the internal oscilla- tor, of which the time period Tosc is adjustable via the external resistor Rwd_osc (10 kΩ to 120 kΩ). In Silent or Sleep Mode, the watchdog is switched off to reduce current consumption. Minimum time for first watchdog pulse is required after the undervoltage reset at NRES disap- pears and is defined as lead time td.

3.17.1 Typical Timing Sequence with R wd_osc = 51 kΩ

The trigger signal Twd is adjustable between 2.9 ms and 33 ms via the external resistor Rwd_osc. For example, with an external resistor of R wd_oscSC =5 1k Ω ±1%, the typical parameters of the watchdog come out as follows: tOSC = 12.5 µs due to 51 kΩ td =3 9 2 2× 12.5 µs = 49 ms t1 =8 0 0× 12.5 µs = 10 ms t2 =8 4 0× 12.5 µs = 10.5 ms tnres =1 5 7× 12.5 µs = 1.96 ms 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 VS (V) IVCC (mA) Tamb = 125˚C Tamb = 105˚C

4887D–AUTO–12/06 ATA6621 After ramping up the battery voltage V S or wake up from Sleep Mode, the 5V regulator is switched on. The reset output NRES stays low for the time t reset (typically 10 ms), then it switches to high and the watchdog waits for t he watchdog sequence from the microcontroller. This lead time t d follows after the reset and is t d = 49 ms. After wake up from Silent Mode the RXD switches to low. The lead time td follows the negative edge of this RXD signal. In this time, the first watchdog pulse from the microcontrolle r is required. If the trigger pulse NTRIG (or PTRIG, as the case may be) occurs during this time, the time t 1 starts immediately. If no trigger signal occurs during the time t d, a watchdog reset with t NRES = 1.96 ms will reset the microcon- troller after td = 49 ms. The times t1 and t2 have a fixed relationship with each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 10.5 ms. To avoid false triggering from glitches, the trigger pulse must be longer than t trigg > 3 µs. This slope serves to restart the watchdog sequence. Should the triggering signal fail in this open window t 2, the NRES output will be drawn to ground after t 2. A triggering signal during the closed window t 1 causes NRES to immediately switch low. Figure 3-8. Timing Sequence with RWD_OSC = 51 kΩ

3.17.2 Worst Case Calculation with R WO_OSC = 51 kΩ

The internal oscillator has a tolerance of ±20%. This means that t1 and t2 can also vary by ±20%. The worst case calculation for the watchdog period Twd the microcontroller has to provide is cal- culated as follows. The ideal watchdog time Twd is between (t1maximum) and (t1 minimum plus t2 minimum). t1,min =0 . 8× t1 =8m s , t1,max =1 . 2× t1 =1 2m s t2,min = 0.8 × t2 = 8.4 ms, t2,max = 1.2 × t2 = 12.6 ms Twdmax =t 1min + t2min = 8 ms + 8.4 ms = 16.4 ms Twdmin =t 1max = 12 ms Twd = 14.2 ms ±2.2 ms (±15%) tnres = 1.9 ms Undervoltage Reset Watchdog Reset treset = 10 ms t1 = 10 ms ttrigg > 3 µs t2 = 10.5 ms t2t1 twd td = 49 ms VCC = 5V PTRIG NTRIG NRES

4887D–AUTO–12/06 ATA6621 A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly within the time period of Twd = 14.2 ms (±15%) in an application with Rwd_osc =5 1k Ω.

3.18 Temperature Monitor at Pin TEMP

In addition to the internal temperature monitoring of the voltage regulator, an additional sensor measures the junction temperature and provides a linearized voltage at the TEMP pin. Together with the analog functions of the microcontroller (for example, the analog comparator and the Analog-to-digital converter (ADC)), this enabl es the application to detect overload conditions and to take corresponding measures in order to prevent damage. An external capacitor buffers the voltage due to the input current of the ADC. The sensor itself is built out of three diodes which are supplied by an internal BIAS current in Pre Normal Mode and Normal Mode. The typical voltage at T = 27°C is V temp = 2.2V with a typical negative temperature coefficient of V TC,TEMP = –5.05 mV/k. In silent and sleep mode the 20 µA current source is switched off. Figure 3-9. Temperature Monitor Table 3-2. Table of Watchdog Timings Rwd_osc kΩ Oscillator Period tosc/µs Lead Time td/ms Closed Window t1/ms Open Window t2/ms Trigger Period from microcontroller twd/ms Reset time tnres/ms TEMP 20 µA VCC

4887D–AUTO–12/06 ATA6621 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min Typ Max Unit Supply voltage V S VS –0.3 +40 V Pulse time ≤ 500 ms T = 25°C Output current IVCC ≤ 50 mA VS +40 V Pulse time ≤ 2m i n T = 25°C Output current I VCC ≤ 50 mA VS 27 V WAKE DC and transient voltage (with 33 kΩ serial resistor) Transient voltage due to ISO7637 (coupling 1 nF) –40 –150 +40 +100 V Logic pins (RXD, TXD, EN, NRES, PTRIG, NTRIG, VCC, PVCC, WD_OSC, TEMP) –0.3 +6.5 V LIN - DC voltage - Transient voltage –40 –150 +60 +100 V VCC DC voltage –0.3 6.5 V ESD (DIN EN 6100-4-2) According LIN EMC Test Specification 1.3 - Pin VS, LIN to GND - Pin WAKE (33 kΩ serial resistor) KV KV ESD HBM - All pins according to ESD S 5.1 ±2 KV CDM ESD STM 5.3.1-1999 - All pins ±1 KV Junction temperature T j –40 +150 °C Storage temperature T s –55 +150 °C Operating ambient temperature T a –40 +125 °C Thermal resistance junction to heat slug R thjc 10 K/W Thermal resistance junction to ambient, where heat slug is soldered to PCB Rthja 35 K/W Thermal shutdown of VCC regulator 150 165 170 °C Thermal shutdown of LIN output 150 165 170 °C Thermal shutdown hysteresis 10 °C

4887D–AUTO–12/06 ATA6621 5. Electrical Characteristics 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions P in Symbol Min Typ Max Unit Type*

1 VS Pin

1.1 Nominal DC voltage

1.2 Supply current in Sleep

Vlin >VBat – 0.5V VBat < 14V (25°C to 125°C) IVSsleep 10 20 µA A

1.3 Supply current in Silent

Bus recessive; VBat < 14V (25°C to 125°C) Without load at VCC IVSsi 40 50 µA A

1.4 Supply current in Normal

Without load at VCC IVSrec 4m A A

1.5 Supply current in Normal

VCC load current 50 mA IVSdom 55 mA A

1.6 VS undervoltage

threshold VSth 4.15 4.5 5 V A

1.7 VS undervoltage

threshold hysteresis VSth_hys 0.2 V A

2 RXD Output Pin

2.1 Low-level input current Normal Mode; VLIN =0 V

VRXD =0 . 4 V IRXD 2 5 8 mA A 2.2 Low-level output voltage I RXD = 1 mA VRXDL 0.3 V A

2.3 Internal 5 kΩ resistor to

VCC RRXD 3 7 k Ω A

3 TXD Input Pin

3.1 Low-level voltage input V TXDL –0.3 +1.5 V A 3.2 High-level voltage input V TXDH 3.5 VCC + 0.3V VA

3.3 Pull-up resistor V TXD = 0V R TXD 125 250 600 k Ω A

3.4 High-level leakage

current VTXD = 5V I TXD –3 +3 µA A

3.5 Low-level input current at

Pre Normal Mode; VLIN = VBattery VWAKE = 0V VTXD = 0.4V ITXDwake 258 m A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4887D–AUTO–12/06 ATA6621 4E N I n p u t P i n 4.1 Low-level voltage input V ENL –0.3 +1.5 V A 4.2 High-level voltage input V ENH 3.5 VCC + 0.3V VA

4.3 Pull-down resistor V EN = 5V R EN 125 250 600 k Ω A

4.4 Low-level input current V EN = 0V I EN –3 +3 µA A

5 NRES Output Pin

5.1 High-level output voltage VS ≥ 5.5V; Inres = –1 mA VNRESH 4.5 V A

5.2 Low-level output voltage

VS ≥ 5.5V; Inres = –1 mA Inres = –250 µA VNRESL 0.2 0.14 V V A A

5.3 Low-level output low 10 kΩ to VCC;

VCC = 0.8V VNRESLL 0.3 V A 5.4 Undervoltage reset time VVS ≥ 5.5V CNRES = 20 pF treset 71 3 m s A

5.5 Reset debounce time for

VVS ≥ 5.5V CNRES =2 0p F tres_f 3µ s A

6 Voltage Regulator VCC Pin in Normal and Pre Normal Mode

6.1 Output voltage VCC 5.5V < VS < 18V (0 mA to 50 mA) VCCnor 4.9 5.1 V A

6.2 Output voltage VCC at

low VS 3.3V < VS < 5.5V VCC low VVS – VD

5.1 V A

6.3 Regulator drop voltage V S > 4.0V, IVCC = –20 mA V D1 250 mV A 6.4 Regulator drop voltage V S > 4.0V, IVCC = –50 mA V D2 500 mV A 6.5 Regulator drop voltage V S > 3.3V, IVCC = –15 mA V D3 200 mV A

6.6 Output current V S > 3V I VCC –50 mA A

6.7 Output current limitation V S > 0V I VCCs –200 –130 mA A

6.8 Load capacity 1 Ω < ESR < 5Ω Cload 1.8 2.2 µF D

6.9 VCC undervoltage

VS > 5.5V VthunN 4.4 4.8 V A

6.10 Hysteresis of

VS > 5.5V Vhysthun 30 mV A 6.11 Ramp up time VS > 5.5V to VCC > 4.9V CVCC = 4.7 µF No load tVCC 300 µs A

7 Voltage Regulator VCC Pin in Silent Mode

7.1 Output voltage VCC 5.5V < VS < 18V (0 mA to 50 mA) VCCnor 4.65 5.35 V A

7.2 Output voltage VCC at

low VS 3.3V < VS <5 . 5 V V C C low VVS – VD 7.3 Regulator drop voltage V S >3 . 3 V , IVCC =– 1 5m A V D 200 mV A 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions P in Symbol Min Typ Max Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4887D–AUTO–12/06 ATA6621 7.4 At VCC undervoltage threshold the state switches back to Pre Normal Mode Referred to VCC V S > 5.5 VthunS 3.9 4.4 V A

7.5 Hysteresis of

VS > 5.5V Vhysthun 40 mV D

7.6 Output current limitation V S > 0V I VCCs –200 –130 mA A

LIN Bus Driver: Bus Load Conditions: Load1 (Small): 1 nF, 1 kΩ; Load2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF 10.5, 10.6 and 10.7 Specify the Timing Parameters for Proper Operation at 20 Kbps

8.1 Driver recessive output

voltage Load1 / Load2 V BUSrec 0.9 VS VS VA

8.2 Driver dominant voltage VVS =7 V

Rload =5 0 0Ω V_LoSUP 1.2 V A

8.3 Driver dominant voltage VVS =1 8 V

Rload =5 0 0Ω V_HiSUP 2V A

8.4 Driver dominant voltage

VBUSdom_DRV_LoSUP VVS = 7V Rload = 1000Ω V_LoSUP_1k 0.6 V A

8.5 Driver dominant voltage VVS = 18V

Rload =1 0 0 0Ω V_HiSUP_1k_ 0.8 V A

8.6 Pull-up resistor to VS The serial diode is mandatory R LIN 20 30 60 k Ω A

8.7 Self-adapting current limitation VBus =V Batt_max Tj = 125°C Tj = 27°C Tj = –40°C IBUS_LIM 100 120 110 170 230 mA mA mA A 8.8 Input leakage current at the receiver including pull-up resistor as specified Input leakage current Driver off V BUS =0 V VBattery =1 2 V IBUS_PAS_dom –1 mA A

8.9 Leakage current LIN

8V < VBattery <1 8 V 8V < VBUS < 18V VBUS ≥ VBatt IBUS_PAS_rec 15 20 µA A 8.10 Leakage current when control unit disconnected from ground. Loss of local ground must not affect communication in the residual network GND Device = VS VBattery = 12V 0V < VBUS < 18V IBUS_NO_gnd –10 0.5 10 µA A 8.11 Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition V Battery disconnected VSUP_Device = GND 0V < VBUS < 18V IBUS 0.5 3 µA A 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions P in Symbol Min Typ Max Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4887D–AUTO–12/06 ATA6621

9 LIN Bus Receiver

9.1 Center of receiver

VBUS_CNT = (Vth_dom + Vth_rec) / 2 VBUS_CNT 0.475 VS 0.5 VS 0.525 – VS VA 9.2 Receiver dominant state V EN = 5V V BUSdom –27 0.4 V S VA 9.3 Receiver recessive state V EN = 5V V BUSrec 0.6 VS 40 V A 9.4 Receiver input hysteresis V HYS = Vth_rec – Vth_dom VBUShys 0.028 VS 0.1 VS 0.175 VS VA

9.5 Wake detection LIN

High-level input voltage VLINH VS –1 V V S + 0.3V V A

9.6 Wake detection LIN

Low-level input voltage Initializes a wake-up signal V LINL –27 V S –3 . 3 V V A

10 Internal Timers

10.1 Dominant time for

wake-up via LIN bus VLIN = 0V T bus 30 90 150 µs A 10.2 Time delay for mode change from Pre Normal to Normal Mode via pin EN VEN = 5V T norm 51 5 2 0 µ s A 10.3 Time delay for mode change from Normal into Sleep Mode via pin EN VEN = 0V T sleep 2 7 15 µs A

10.4 TXD dominant time-out

timer VTXD = 0V T dom 61 0 2 0 m s A

10.5 Duty cycle 1

THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 7.0V to 18V; tBit =5 0µ s D1 = tbus_rec(min) / (2 × tBit) D1 0.396 A

10.6 Duty cycle 2

THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 7.0V to 18V; tBit = 50 µs D2 = tbus_rec(max) / (2 × tBit) D2 0.581 A

10.7 Slope time falling and

TSLOPE_fall TSLOPE_rise 3.5 22.5 µs A

10.8 Time of low pulse for

wake-up via pin WAKE VWAKE = 0V T WAKE 60 130 200 µs A 11 Internal Receiver Electrical AC Parameters of the LI N Physical Layer LIN Receiver, RXD Load Conditions (CRXD): 20 pF 11.1 Propagation delay of receiver (Figure 5-1 on page 22) trec_pd = max(trx_pdr, trx_pdf)t rx_pd 6µ s A 11.2 Symmetry of receiver propagation delay rising edge minus falling edge t rx_sym = trx_pdr – trx_pdf trx_sym –2 2 µs A 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions P in Symbol Min Typ Max Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4887D–AUTO–12/06 ATA6621

12 Watchdog Input PTRIG and NTRIG

12.1 Watchdog input

high-level threshold V_HPTRIG 3.5 V A

12.2 Watchdog input low

threshold V_LPTRIG 1.5 V A

12.3 Internal pull down PTRIG

250 600 k Ω A

13 Watchdog Oscillator

13.1 Voltage at WD_OSC in

Normal Mode IWD_OSC = –250 µA V WD_OSC 2.3 2.5 2.7 V A

13.2 Possible values of

resistor ROSC 10 120 k Ω D 13.3 Oscillator period R OSC = 10 kΩ tOSC 2.1 2.6 3.1 µs A 13.4 Oscillator period R OSC = 51 kΩ tOSC 10 12.5 15 µs A 13.5 Oscillator period R OSC = 91 kΩ tOSC 17.9 22.4 26.8 µs A 13.6 Oscillator period R OSC = 120 kΩ tOSC 23.2 29 34.8 µs A

14 Watchdog Timing Relative to t OSC

14.1 Watchdog lead time after

14.2 Watchdog closed

14.3 Watchdog open window t 2 840 cycles A

14.4 Watchdog reset time

15 Temperature Monitor at Pin TEMP

15.1 Voltage at TEMP in Normal Mode (T = –40°C) I TEMP = ±3 µA V TEMP 2.35 2.7 V A

15.1 Voltage at TEMP in

Normal Mode (T = 27°C) ITEMP = ±3 µA V TEMP 2.0 2.35 V A 15.1 Voltage at TEMP in Normal Mode (T = 125°C) I TEMP = ±3 µA V TEMP 1.4 1.9 V A

15.2 Short current at TEMP VTEMP = 0V I TEMP –30 –15 µA A

15.3 Temperature gradient V TC,TEMP 4.8 5.05 5.3 mV/k C

16 Wake Pin

16.1 High-level input voltage V WAKEH VS – 1V V S + 0.3V V A 16.2 Low-level input voltage Initializes a wake-up signal V WAKEL –27 V S – 3.3V V A

16.3 Wake pull-up current V S < 27V, VWake = 0V I WAKE –30 –10 µA A

16.4 High-level leakage

current VS = 27V; VWake = 27V I WAKEL –5 +5 µA A 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions P in Symbol Min Typ Max Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4887D–AUTO–12/06 ATA6621 Figure 5-1. Definition of Bus Timing Parameters

17 Mode Input Pin

17.1 Low-level voltage input V MODEL –0.3 +0.8V V A 17.2 High-level voltage input V MODEH 2V S + 0.3V V A

17.3 High-level leakage

VMODE = VCC or VMODE = 0V IMODE –3 +3 µA A 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions P in Symbol Min Typ Max Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter TXD (input to transmitting node) VS (Transceiver supply of transmitting node) RXD (output of receiving node1) RXD (output of receiving node2) LIN Bus Signal Thresholds of receiving node1 Thresholds of receiving node2 tBus_rec(max) trx_pdr(1) trx_pdf(2)trx_pdr(2) trx_pdf(1) tBus_dom(min) tBus_dom(max) THRec(max) THDom(max) THRec(min) THDom(min) tBus_rec(min) tBit tBittBit

4887D–AUTO–12/06 ATA6621 Figure 5-2. Application Circuit 67 8 1 0 9 20 19 18 MLP 5 mm × 5 mm 0.65 mm pitch 20 lead ATA6621 TXD NRES LIN sub bus WD_OSC TM MODE Master node pull-up GND TEMP PVCC VCC VS NC RXD NC LIN NC GND WAKE Wake-up switch 10 kΩ 1 kΩ 33 kΩ 10 kΩ NTRIG PTRIG NTRIG PTRIG Microcontroller RESET TXD RXD EN VCC VBattery EN 220 pF 100 nF22 µF + 100 nF 22 µF 1 nF 10 kΩ debug

4887D–AUTO–12/06 ATA6621 Figure 5-3. Application Circuit with External NPN 67 8 1 0 9 20 19 18 MLP 5 mm × 5 mm 0.65 mm pitch 20 lead ATA6621 TXD NRES LIN sub bus WD_OSC TM Master node pull-up GND TEMP PVCC VCC VS NC RXD NC LIN NC GND WAKE Wake-up switch 10 kΩ 1 kΩ 33 kΩ 10 kΩ NTRIG PTRIG NTRIG PTRIG Microcontroller RESET TXD RXD EN VCC VBattery EN 220 pF 100 nF MJD31C 100 µF 2.2 µF 100 nF 22 µF 1 nF MODE 10 kΩ debug

4887D–AUTO–12/06 ATA6621 7. Package Information 6. Ordering Information Extended Type Number Package Remarks ATA6621-PGQW QFN20 Pb-free, taped and reeled ATA6621-PGPW QFN20 Pb-free, taped and reeled

4887D–AUTO–12/06 ATA6621 8. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4887D-AUTO-12/06

• Put datasheet in a new template
• Table 2-1 “Pin Description” on page 3 changed
• Section 3.1 “Supply Pin (VS)” on page 4 changed
• Section 3.7 “TXD Dominant Time-out Function” on page 5 changed
• Section 3.13.3 “Sleep Mode” on page 8 changed
• Section 3.14 in “Wake-up Scenarios from Silent or Sleep Mode” renamed
• Section 3.15 “Fail-safe Features” on page 11 changed
• Section 3.18 “Temperature Monitor at Pin TEMP” changed
• Table “Electrical Characteristics” numbers 10.4, 13.2 and 15.3 on pages 20 to 21 changed
• Table “Electrical Characteristics” numbers 17.1, 17.2 and 17.3 on page 22 added
• Section 6 “Ordering Information” on page 25 changed 4887C-AUTO-03/06
• Features on page 1 changed
• Table 2-1 “Pin Description” on page 3 changed
• Section 3.11 “Mode and TM Input Pins” on page 5 changed
• Figure 3-1 “Modes of Operation” on page 6 changed
• Section 3.12.6 “Debug Mode” on page 9 added
• Section 3.13.3 “Wake-up Source Recognition” on page 11 changed
• Section 3.15 “Voltage Regulator” on page 12 changed
• Table “Absolute Maximum Ratings” on page 16 changed
• Table “Electrical Characteristics” from pages 17 to 21 changed
• Figure 5-2 “Application Circuit” on page 23 changed
• Figure 5-3 “Application Circuit with External NPN” on page 24 changed

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