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- Supply Voltage up to 40V Operating Voltage VS = 5V to 18V Typically 10 µA Supply Current During Sleep Mode Typically 40 µA Supply Current in Silent Mode Linear Low-drop Voltage Regulator: – Normal Mode: V CC = 5V ±2%/50 mA – Silent Mode: V CC = 5V ±7%/50 mA –S l e e p M o d e : VCC is Switched Off VCC Undervoltage Detection with Reset Output NRES (10 ms Reset Time) Voltage Regulator is Short-circuit and Over-temperature Protected LIN Physical Layer According to LIN Specification Revision 2.0 Wake-up Capability via LIN Bus (90 µs Dominant) TXD Time-out Timer (9 ms) 60V Load-dump Protection at LIN Pin Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery High EMC Level 5V CMOS-Compatible I/O Pins to MCU ESD HBM 6kV at Pins LIN and VS Interference and Damage Protection According to ISO/CD7637 Package: SO8 1. Description ATA6620 is a fully integrated LIN transceiver, designed according to the LIN specifica- tion 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6620 is designed to handle the low-speed data com- munication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud with an RC oscillator for the protocol handling. The bus output is designed to withstand high voltage. Sleep mode (voltage regulator switched off) and Silent mode (communication off; V CC voltage on) guarantee minimized current consumption. LIN Bus Transceiver with Integrated Voltage Regulator ATA6620 Preliminary Rev. 4850A–AUTO–02/05
4850A–AUTO–02/05 ATA6620 [Preliminary] Figure 1-1. Block Diagram 2. Pin Configuration Figure 2-1. Pinning SO8 VS NRES7
4 LIN
5V/50 mA/2% Silent Mode Voltage Regulator 5V/50 mA/7% Short Circuit and Overtemperature Protection VS EN GND LIN VCC NRES TXD RXD Table 2-1. Pin Description Pin Symbol Function
1 VS Battery supply
2 EN Enables Normal mode if the input is high
3 GND Ground
4 LIN LIN bus line input/output
5 RXD Receive data output
6 TXD Transmit data input
7 NRES Output undervoltage reset, low at reset
8 VCC Output voltage regulator 5V/50 mA
4850A–AUTO–02/05 ATA6620 [Preliminary] 3. Functional Description
3.1 Supply Pin (VS)
LIN operating voltage is V S = 5V to 18V. An undervoltage detec tion is implemented to disable transmission if V S falls below 5V, in order to avoid false bus messages. After switching on V S, the IC starts with the Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode.
3.2 Ground Pin (GND)
The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift up to 3V for supply voltage above 9V at the VS pin.
3.3 Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the microcontroller and other ICs on the PCB. It is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun.
3.4 Undervoltage Reset Output (NRES)
This push-pull output is supplied from the V CC voltage. If the V CC voltage falls below the under- voltage detection threshold of V thun, NRES switches to low after tres_f ( Figure 4-6 on page 9 ). Even if VCC = 0V the NRES stays low, because it is internally driven from the V S voltage. If V S voltage ramps down, NRES stays low until VS < 1.5V and then becomes highly resistant. The implemented undervoltage delay keeps NRES low for t Reset = 10 ms after V CC reaches its nominal value.
3.5 Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown, as well as an internal pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from –27V to +60V. This pin exhibits no re verse current from the LIN bus to VS, even in the case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN proto- col specification. The fall time (from recessive to dominant) and th e rise time (from dominant to recessive) are slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita- tion; that is, during current limitation, as the chip temperature increases, the current decreases.
3.6 Input Pin (TXD)
This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resis- tor), the LIN output transistor is turned off and the bus is in the recessive state.
4850A–AUTO–02/05 ATA6620 [Preliminary]
3.7 Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than T DOM > 4 ms, the LIN bus driver is switched to the recessive state. To reset this dominant time-out mode, TXD must be switched to high (>10 µs) before normal data transmission can be started.
3.8 Output Pin (RXD)
This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 k Ω to VCC. The AC characteristics are measured with an external load capacitor of 20 pF. The output is short-circuit protected. In unpowered mode (that is, VS = 0V), RXD is switched off.
3.9 Enable Input Pin (EN)
This pin controls the operation mode of the interface. After power up of V S (battery), the IC switches to Pre-normal mode, even if EN is low or unconnected (internal pull-down resistor). If EN is high, the interface is in Normal mode. A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN while TXD is low forces the device to Sleep mode. 4. Mode of Operation Figure 4-1. Mode of Operation Pre-normal Mode VCC: 5V/2%/50 mA with undervoltage reset Communication: OFF ab Silent Mode VCC: 5V/7%/50 mA with undervoltage reset Communication: OFFEN = 1 Go to silent command EN = 0 TXD = 1 Local wake-up event a: VS > 5V b: VS < 4V c: Bus wake-up event b EN = 1 b c Normal Mode VCC: 5V/2%/50 mA with undervoltage reset Communication: ON Unpowered Mode VBatt = 0V Sleep Mode VCC: switched off Communication: OFF Go to sleep command Local wake-up event EN = 0 TXD = 0 EN = 1 bc
4850A–AUTO–02/05 ATA6620 [Preliminary]
4.1 Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.0. The V CC voltage regulator operates with a 5V output voltage, with a low toler- ance of ±2% and a maximum output current of 50 mA. If an undervoltage condition occurs, NRES is switched to low and the ATA6620 changes state to Pre-normal mode. All features are available.
4.2 Silent Mode
A falling edge at EN while TXD is high switches th e IC into Silent mode. The TXD Signal has to be logic high during the Mode Select window (Figure 4-2 on page 6). For EN and TXD either two independent outputs can be used, or two outputs from the same microcontroller port; in the sec- ond case, the mode change is only one command. In Silent mode the transmission path is disabled. Supply current from V Batt is typically IVSsi = 40 µA with no load at the VCC regulator. The overall supply current from V Batt is the result of 40 µA plus the V CC regulator output current IVCCs. The 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. In Silent mode the internal slave termination betw een pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typ- ically 10 µA) between pin LIN and pin VS is present. The Silent mode voltage is sufficient to run an external microcontroller on the ECU, for example in Power Down mode. The undervoltage reset is V CCthS < 4.4V. If an undervoltage condition occurs, NRES is switched to low and the ATA6620 changes state to Pre-normal mode. A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (Tbus) results in a remote wake-up request. The device switches from Silent mode to Pre-normal mode, then the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller. ( Figure 4-5 on page 8) With EN high, ATA6620 switches directly from Silent to Normal mode. Table 4-1. Mode of Operation Mode of Operation Communication V CC RXD LIN Pre-normal OFF 5V 5V Recessive Normal ON 5V 5V Recessive Silent OFF 5V 5V Recessive Sleep OFF 0V 0V Recessive
4850A–AUTO–02/05 ATA6620 [Preliminary]
4.3 Sleep Mode
A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to be logic low during the Mode Select window ( Figure 4-4 on page 8 ). We recommend using the same microcontroller port for EN as for TXD; in this case the mode change is only one command. In Sleep mode the transmission path is disabled. Supply current from V Batt is typically IVSsleep = 10 µA. The V CC regulator is switched off; NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (Tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon- troller. (Figure 4-5 on page 8) With EN high you can switch directly from Silent to Normal mode. In the application where the ATA6620 supplies the microcontroller, the wake -up from Sleep mode is only possible via pin LIN.
4.4 Pre-normal Mode
At system power-up the device automatically switches to Pre-normal mode. The voltage regula- tor is switched on (V CC = 5V/50 mA) (see Figure 4-4 on page 8 ) after typically t VCC = 1 ms. The NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN com- munication is switched off, and the undervoltage detection is active. A power-down of V Batt (VS < 4V) during Silent or Sleep mode switches into Pre-normal mode after powering up the IC.
4.5 Unpowered Mode
If battery voltage is connected to the application circuit (Figure 4-6 on page 9), the voltage at the VS pin increases due to the block capacitor. When VS is higher than the VS undervoltage thresh- old, VSth, the IC-mode changes from Unpowered to Pre-normal mode. The V CC output voltage reaches nominal value after tVCC. This time depends on the VCC capacitor and the load. NRES is low for the reset time delay tReset; no mode change is possible during this time.
4850A–AUTO–02/05 ATA6620 [Preliminary] Figure 4-6. VCC Voltage Regulator: Ramp Up and Undervoltage 5. Fail Safe Features During a short circuit at LIN, the output limits the output current to I BUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. During LIN overtemperature switch-off, the VCC regulator works independently. There are now reverse currents < 3 µA at pin LIN during loss of V Batt or GND. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. During a short circuit at VCC, the output limits the output current to I VCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Pre–normal mode. If the chip temperature exceeds the value T VCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of Pre-normal mode, the VCC voltage will switch on again although EN is switched off from the microcontroller.The microcontroller can then start with normal operation. Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. Pin RXD is set floating if V Batt is disconnected. Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. VS 5.5V 12V VCC NRES Vthun Tres Tes_fTVCC
4850A–AUTO–02/05 ATA6620 [Preliminary] 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Typ. Max. Unit V S - Continuous supply voltage –0.3 +40 V Logic pins (RxD, TxD, EN, NRES) –0.3 +6.5 V LIN - DC voltage - Transient voltage –40 –150 +60 +100 V V V CC - DC voltage –0.3 +6.5 V ESD (DIN EN 6100–4–2) Pin LIN, VS versus GND according to LIN specification EMC Evaluation V 1.3 –6 +6 kV HBM ESD S5.1 – all pins –2 +2 kV CDM ESD STM 5.3.1–1999 - All pins –500 +500 V Junction temperature T j –40 +150 °C Storage temperature T s –55 +150 °C Operating ambient temperature T a –40 +125 °C Thermal resistance junction to ambient (free air) Rthja 145 K/W Special heat sink at GND (pin 3) on PCB R thja 100 K/W Thermal shutdown of VCC regulator T VCCoff 155 165 175 °C Thermal shutdown of LIN output T LINoff 155 165 175 °C Thermal shutdown hysteresis T hys 7° C
4850A–AUTO–02/05 ATA6620 [Preliminary] 8. Electrical Characteristics 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
1 VS Pin
1.1 Nominal DC voltage
range VS V S 51 3 . 5 1 8 V A
1.2 Supply current in Sleep
Vlin > VBatt – 0.5V VBatt < 14V (25°C to 125°C) VS I VSsleep 10 20 µA A
1.3 Supply current in Silent
Bus recessive; VBatt < 14V (25°C to 125°C) Without load at VCC VS I VSsi 40 50 µA A
1.4 Supply current in
1.5 Supply current in
VCC load current 50 mA VS I VSdom 55 mA A
1.6 Power On Reset
threshold VS POR th 33 . 3 V D
1.7 Power On Reset
threshold hysteresis VS POR hys 0.1 V D
1.8 VS undervoltage
threshold VS V Sth 4.0 4.5 5 V A
1.9 VS undervoltage
threshold hysteresis VS V Sth_hys 0.2 V A
2 RXD Output Pin
2.1 Low level input current
Normal mode; VLIN = 0V VRXD = 0.4V RXD I RXD 258 m A A 2.2 Low level output voltage I RXD = 1 mA RXD V RXDL 0.4 V A 2.3 High level output voltage I RXD = –1 mA RXD V RXDH 4.2 V A
2.4 Internal resistor to V CC RXD R RXD 357 k Ω A
3 TXD Input Pin
3.1 Low level voltage input TXD V TXDL –0.3 +1.5 V A 3.2 High level voltage input TXD V TXDH 3.5 VCC + 0.3V VA
3.3 Pull-up resistor V TXD = 0V TXD R TXD 125 250 600 k Ω A
3.4 High level leakage
current VTXD = 5V TXD I TXD –3 +3 µA A 4E N I n p u t P i n 4.1 Low level voltage input EN V ENL –0.3 +1.5 V A 4.2 High level voltage input EN V ENH 3.5 VCC + 0.3V VA
4.3 Pull-down resistor V EN = 5V EN R EN 125 250 600 k Ω A
4.4 Low level input current V EN = 0V EN I EN –3 +3 µA A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4850A–AUTO–02/05 ATA6620 [Preliminary] 5N R E S O u t p u t P i n 5.1 High level output voltage VS ≥ 5.5V; INRES = –1 mA NRES V NRESH 4.2 V A 5.2 Low level output voltage VS ≥ 5.5V; INRES = –1 mA NRES V NRESL 0.4 V A
5.3 Low level output low 10 kΩ to VCC;
VCC = 0.8V NRES V NRESLL 0.2 V A 5.4 Undervoltage reset time VVS ≥ 5.5V CNRES = 20 pF NRES t Reset 71 3 m s A
5.5 Reset debounce time for
VVS ≥ 5.5V CNRES = 20 pF NRES t res_f 5µ sA
6 Voltage Regulator VCC Pin in Normal and Pre-normal Mode
6.1 Output voltage V CC 5.5V < VS < 18V (0 mA – 50 mA) VCC V CCnor 4.9 5.1 V A
6.2 Output voltage VCC at
3.3V < VS < 5.5V (0 mA – 50 mA) VCC V CClow VVS – VD
5.1 V A
6.3 Regulator drop voltage V S > 4.0V, IVCC = 20 mA VCC V D 250 mV A 6.4 Regulator drop voltage V S > 4.0V, IVCC = 50 mA VCC V D 500 mV A 6.5 Regulator drop voltage V S > 3.3V, IVCC = 15 mA VCC V D 200 mV A
6.6 Output current V S > 3V VCC I VCC –50 mA A
6.7 Output current limitation V S > 0V VCC I VCCs –200 –130 mA A
6.8 Load capacity ESR < 5 Ω VCC C load 1.8 2.2 µF A
6.9 VCC undervoltage
VS > 5.5V VCC V thunN 4.4 4.8 V A
6.10 Hysteresis of
VS > 5.5V VCC V hysthun 40 mV A 6.11 Ramp up time VS > 5.5V to VCC > 4.9V CVCC = 2.2 µF Rload at VCC: 100Ω VCC t VCC 12 m s A
7 Voltage Regulator VCC Pin in Silent Mode
7.1 Output voltage V CC 5.5V < VS < 18V (0 mA – 50 mA) VCC V CCnor 4.65 5.35 V A
7.2 Output voltage VCC at
3.3V < VS < 5.5V (0 mA – 50 mA) VCC V CClow VVS – VD 7.3 Regulator drop voltage V S > 3.3V, IVCC = 15 mA VCC V D 200 mV A 7.4 At VCC undervoltage threshold the state switches back to Pre-normal mode Referred to VCC VS > 5.5 VCC V thunS 3.9 4.4 V A 7.5 Hysteresis of undervoltage threshold Referred to VCC VS > 5.5V VCC V hysthun 40 mV D
7.6 Output current limitation V S > 0V VCC I VCCs –200 –130 mA A
- Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4850A–AUTO–02/05 ATA6620 [Preliminary] LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF 10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps
8.1 Driver recessive output
VTXD = 0V; ILIN = 0 mA LIN V BUSrec 0.9 × VS VS VA 8.2 Driver dominant voltage VVS = 7.3V Rload = 500 Ω LIN V _LoSUP 1.2 V A
8.3 Driver dominant voltage VVS = 18V
Rload = 500 Ω LIN V _HiSUP 2VA 8.4 Driver dominant voltage VVS = 7.3V Rload = 1000 Ω LIN V _LoSUP_1k 0.6 V A
8.5 Driver dominant voltage VVS = 18V
Rload = 1000 Ω LIN V _HiSUP_1k 0.8 V A
8.6 Pull–up resistor to V S
mandatory LIN R LIN 20 30 60 k Ω A 8.7 Self-adapting current limitation VBUS = VBatt_max Tj = 125°C Tj = 27°C Tj = –40°C LIN I BUS_LIM 100 150 110 170 230 mA mA mA A 8.8 Input leakage current at the receiver including pull–up resistor as specified Input Leakage current Driver off VBUS = 0V VBatt = 12V LIN I BUS_PAS_dom –1 mA A
8.9 Leakage current LIN
8V < VBatt < 18V 8V < VBUS < 18V VBUS ≥ VBatt LIN I BUS_PAS_rec 15 20 µA A 8.10 Leakage current when control unit disconnected from ground. Loss of local ground must not affect communication in the residual network GND Device = VS VBatt = 12V 0V < VBUS < 18V LIN I BUS_NO_gnd –10 +0.5 +10 µA A 8.11 Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition V Batt disconnected VSUP_Device = GND 0V < VBUS < 18V LIN I BUS 0.5 3 µA A 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4850A–AUTO–02/05 ATA6620 [Preliminary]
9 LIN Bus Receiver
9.1 Center of receiver
VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN V BUS_CNT 0.475 × VS 0.5 × VS 0.525 × VS VA 9.2 Receiver dominant state V EN = 5V LIN V BUSdom –27 0.4 × VS VA 9.3 Receiver recessive state V EN = 5V LIN V BUSrec 0.6 × VS 40 V A
9.4 Receiver input
hysteresis Vhys = Vth_rec – Vth_dom LIN V BUShys 0.028 × VS 0.1 x VS 0.175 × VS VA
9.5 Wake detection LIN
High level input voltage LIN V LINH VS – 1V V S + 0.3V V A
9.6 Wake detection LIN
Low level input voltage ILIN = typically –3 mA LIN V LINL –27 V S – 3V V A
9.7 LIN pull-up current V S < 27V LIN I LIN –30 –10 µA A
10 Internal Timers
10.1 Dominant time for
wake–up via LIN bus VLIN = 0V t bus 30 90 150 µs A 10.2 Time delay for mode change from Pre-normal into Normal mode via pin EN V EN = 5V t norm 15 1 0 µ s A 10.3 Time delay for mode change from Normal mode to Sleep mode via pin EN VEN = 0V t sleep 27 1 2 µ s A
10.4 TXD dominant time out
timer VTXD = 0V t dom 51 0 2 0 m s A
10.5 Duty cycle 1
THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 7.0V to 18V; tBit = 50 ms D1 = tbus_rec(min)/(2 × tBit) D1 0.396 A
10.6 Duty cycle 2
THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 7.0V to 18V; tBit = 50ms D2 = tbus_rec(max)/(2 × tBit) D2 0.581 A
10.7 Slope time falling and
tSLOPE_fall tSLOPE_rise 3.5 22.5 µs A
11 Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions (CRXD): 20 pF; Rpull-up = 2.4 kΩ
11.1 Propagation delay of
trec_pd = max(trx_pdr, trx_pdf) trx_pd 6µ sA 11.2 Symmetry of receiver propagation delay rising edge minus falling edge t rx_sym = trx_pdr – trx_pdf trx_sym –2 +2 µs A 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4850A–AUTO–02/05 ATA6620 [Preliminary] Figure 8-1. Definition of Bus Timing Characteristics VS (Transceiver supply of transmitting node) TXD (Input to transmitting Node) RXD (Output of receiving Node1) LIN Bus Signal tBit tBus_dom(max) tBus_dom(min) tBus_rec(min) tBus_rec(max) RXD (Output of receiving Node2) THRec(max) THDom(max) THDom(min) THRec(min) Thresholds of receiving node 1 Thresholds of receiving node 2 trx_pdf(1) trx_pdr(1) trx_pdr(2) trx_pdf(2) tBit tBit
4850A–AUTO–02/05 ATA6620 [Preliminary] Figure 8-2. Application Circuit Microcontroller VBAT 22 µF 100 nF 100 nF LIN-BUS 220 pF VS NRES7 5V/10% VCC Normal and Pre-normal Mode VCC 22 µF Normal Mode Voltage Regulator 5V/50 mA
4850A–AUTO–02/05 ATA6620 [Preliminary] 10. Package Information 9. Ordering Information Extended Type Number Package Remarks ATA6620-TAQY SO8 LIN System Basis Chip technical drawings according to DIN specifications Dimensions in mm 5.00 4.85 0.4 1.27 3.81 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2
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