ATA5746C

ATA5746C_14 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 42

Technical content

Features

• Transparent RF receiver ICs for 315MHz (Atmel® ATA5746C) and 433.92MHz (Atmel ATA5745C) with high receiving sensitivity
• Fully integrated PLL with low phase noise VCO, PLL, and loop filter
• High FSK/ASK sensitivity:
• –105dBm (Atmel ATA5746C, FSK, 9.6Kbits/s, Manchester, BER 10-3)
• –114dBm (Atmel ATA5746C, ASK, 2.4Kbits/s, Manchester, BER 10-3)
• –104dBm (Atmel ATA5745C, FSK, 9.6Kbits/s, Manchester, BER 10-3)
• –113dBm (Atmel ATA5745C, ASK, 2.4Kbits/s, Manchester, BER 10-3)
• Supply current: 6.5mA in Active Mode (3V, 25°C, ASK Mode)
• Data rate: 1Kbit/s to 10Kbits/s Manchester ASK, 1Kbit/s to 20Kbits/s Manchester FSK with four programmable bit rate ranges
• Switching between modulation types ASK/FSK and different data rates possible in ≤ 1ms typically, without hardware modification on board to allow different modulation schemes for RKE, TPMS
• Low standby current: 50µA at 3V, 25°C
• ASK/FSK receiver uses a Low-IF architecture with high selectivity, blocking, and Low intermodulation (typical 3-dB blocking 68.0dBC at ±3MHz/74.0dBC at ±20.0MHz, system I1dBCP = –31dBm/system IIP3 = –24dBm)
• Telegram pause up to 52ms supported in ASK Mode
• Wide bandwidth AGC to handle large out-of-band blockers above the system I1dBCP
• 440-kHz IF frequency with 30-dB image rejection and 420-kHz IF bandwidth to support PLL transmitters with standard crystals or SAW-based transmitters
• RSSI (Received Signal Strength Indicator) with output signal dynamic range of 65dB
• Low in-band sensitivity change of typically ±2.0dB within ±160-kHz center frequency change in the complete temperature and supply voltage range
• Sophisticated threshold control and quasi-peak detector circuit in the data slicer
• Fast and stable XTO start-up circuit (> –1.4kΩ worst-case start impedance)
• Clock generation for microcontroller ATA5745C/ATA5746C UHF ASK/FSK Receiver DATASHEET

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

• ESD protection at all pins (±4kV HBM, ±200V MM, ±500V FCDM)
• Dual supply voltage range: 2.7V to 3.3V or 4.5V to 5.5V
• Temperature range: –40°C to +105°C
• Small 5mm × 5mm QFN24 package

Applications

• Automotive keyless entry and tire pressure monitoring systems
• Alarm, telemetering and energy metering systems Benefits
• Supports header and blanking periods of protocols common in RKE and TPM systems (up to 52ms in ASK Mode)
• All RF relevant functions are integrated. The single-ended RF input is suited for easy adaptation to λ / 4 or printed-loop antennas
• Allows a low-cost application with only 8 passive components
• Suitable for use in a receiver for joint RKE and TPMS
• Optimal bandwidth maximizes sensitivity while maintaining SAW transmitter compatibility
• Clock output provides an external microcontroller crystal-precision time reference
• Well suited for use with Atmel® PLL transmitter ATA5756/ATA5757

3ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 1. General Description The Atmel® ATA5745C/ATA5746C is a UHF ASK/FSK transparent receiver IC with low power consumption supplied in a small QFN24 package (body 5mm × 5mm, pitch 0.65mm). Atmel ATA5745C is used in the 433MHz to 435MHz band of operation, and Atmel ATA5746C in 313MHz to 317MHz. The IC combines the functionality of remote keyless entry (RKE - typically low bit rate ASK) and tire pressure monitoring (TPM - typically high bit rate FSK) into one receiver under the control of an external microcontroller such as an Atmel ATmega48 (AVR®). For improved image rejection and selectivity, the IF frequency is fixed to 440kHz. The IF block uses an 8th-order band pass yielding a receive bandwidth of 420kHz. This enables the use of the receiver in both SAW- and PLL-based transmitter systems utilizing various types of data-bit encoding such as pulse width modulation, Manchester modulation, variable pulse modulation, pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq® are easily supported due to the receiver’s ability to hold the current data slicer threshold for up to 52ms when incoming RF telegrams contain a blanking interval. This feature eliminates erroneous noise from appearing on the demodulated data output pin, and simplifies software decoding algorithms. The decoding of the data stream must be carried out by a connected microcontroller device. Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching. Atmel ATA5745C and Atmel ATA5746C support Manchester bit rates of 1Kbit/s to 10Kbits/s in ASK and 1Kbit/s to 20Kbits/s an RSSI output to provide an indication of received signal strength and a SENSE input to allow the customer to select a threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are selected by the connected microcontroller device via pins ASK_NFSK, BR0, and BR1. Figure 1-1. System Block Diagram (LNA, Mixer, VCO, PLL, IF Filter, RSSI Amp., Demodulator) RF Receiver ATA5745C/ATA5746C Antenna XTO Microcontroller Microcontroller Interface 4 ... 8 Power Supply Digital Control Logic

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 Figure 1-2. Pinning QFN24 Table 1-1. Pin Description Pin Symbol Function

1 TEST2 Test pin, during operation at GND

2 TEST1 Test pin, during operation at GND

3 CLK_OUT Output to clock a connected microcontroller

4 CLK_OUT_CTRL1 Input to control CLK_OUT (MSB)

5 CLK_OUT_CTRL0 Input to control CLK_OUT (LSB)

6 ENABLE Input to enable the XTO

7 XTAL2 Reference crystal

8 XTAL1 Reference crystal

9 DVCC Digital voltage supply blocking

10 VS5V Power supply input for voltage range 4.5V to 5.5V 11 VS3V_AVCC Power supply input for voltage range 2.7V to 3.3V

12 GND Ground

13 LNA_GND RF ground

14 LNA_IN RF input

15 SENSE Sensitivity control resistor

16 SENSE_CTRL Sensitivity selection

Low: Normal sensitivity, High: Reduced sensitivity

17 RSSI Output of the RSSI amplifier

18 TEST3 Test pin, during operation at GND

19 RX Input to activate the receiver

20 BR0 Bit rate selection, LSB

21 BR1 Bit rate selection, MSB

22 ASK_NFSK FSK/ASK selection

Low: FSK, High: ASK

23 CDEM Capacitor to adjust the lower cut-off frequency data filter

24 DATA_OUT Data output

GND Ground/backplane (exposed die pad) TEST3 DATA_OUT BR1 RX BR0 ASK_NFSK CDEM XTAL2 VS5V GND VS3V_AVCC DVCC XTAL1 RSSI LNA_IN LNA_GND SENSE SENSE_CTRL TEST2 789 1 0 1 1 1 2 23 22 TEST1 CLK_OUT_CTRL0 ENABLE CLK_OUT_CTRL1 CLK_OUT 21 20 19

5ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 Figure 1-3. Block Diagram LPF FSK ASK VS3V_AVCC VS5V SENSE_CTRL SENSE GND DVCC LNA_IN LNA_GND CDEM ASK_NFSK BR0 BR1 RX CLK_OUT_CTRL1 TEST1 TEST3 TEST2 ENABLE RSSI CLK_OUT CLK_OUT_CTRL0 DATA_OUT Standby Logic Control XTO Div. by 3, 6, 12 LPF XTAL2 XTAL1 XTO LNA VCO PLL (/24, /32) IF Amp IF Amp ASK/FSK Demo- dulator Power Supply Data Slicer ASK/FSK Control IF Filter

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 2. RF Receiver As seen in Figure 1-3 on page 5, the RF receiver consists of a low-noise amplifier (LNA), a local oscillator, and the signal processing part with mixer, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter, and data slicer. In receive mode, the LNA pre-amplifies the received signal which is converted down to a 440-kHz intermediate frequency (IF), then filtered and amplified before it is fed into an FSK/ASK demodulator, data filter, and data slicer. The received signal strength indicator (RSSI) signal is available at the pin RSSI.

2.1 Low-IF Receiver

The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking, selectivity, supply voltage, and supply current specification needed to design an automotive integrated receiver for RKE and TPM systems. A benefit of the integrated receive filter is that no external components needed. At 315MHz, the Atmel® ATA5745C receiver (433.92MHz for the Atmel ATA5746C receiver) has a typical system noise figure of 6.0dB (7.0dB), a system I1dBCP of –31dBm (–30dBm), and a system IIP3 of –24dBm (–23dBm). The signal path is linear for out-of-band disturbers up to the I1dBCP and hence there is no AGC or switching of the LNA needed, and a better blocking performance is achieved. This receiver uses an IF (intermediate frequency) of 440kHz, the typical image rejection is 30dB and the typical 3-dB IF filter bandwidth is 420kHz (fIF = 440kHz ± 210kHz, flo_IF = 230kHz and fhi_IF = 650kHz). The demodulator needs a signal-to-noise ratio of 8.5dB for 10Kbits/s Manchester with ±38kHz frequency deviation in FSK mode, thus, the resulting sensitivity at 315MHz (433.92MHz) is typically –105dBm (–104dBm). Due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated IF filter, the receiver has a better selectivity and blocking performance than more complex double superhet receivers, without using external components and without numerous spurious receiving frequencies. A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct conversion receivers where every pulse or amplitude modulated signal (especially the signals from TDMA systems like GSM) demodulates to the receiving signal band at second-order non-linearities.

2.2 Input Matching at LNA_IN

The measured input impedances as well as the values of a parallel equivalent circuit of these impedances can be seen in Table 2-1. The highest sensitivity is achieved with power matching of these impedances to the source impedance. The matching of the LNA input to 50Ω is done using the circuit shown in Figure 2-1 and the values of the matching elements given in Table 2-2. The reflection coefficients were always ≤ –10dB. Note that value changes of C1 and L1 may be necessary to compensate individual board layout parasitics. The measured typical FSK and ASK Manchester-code sensitivities with a bit error rate (BER) of 10–3 are shown in Table 2-3 and Table 2-4 on page 7. These measurements were done with wire-wound inductors having quality factors reported in Table 2-2, resulting in estimated matching losses of 0.8dB at 315MHz and 433.92MHz. These losses can be estimated when calculating the parallel equivalent resistance of the inductor with Rloss =2 ×π× f × L × QL and the matching loss with 10 log(1+RIn_p /R loss). Figure 2-1. Input Matching to 50 Ω Table 2-1. Measured Input Impedances of the LNA_IN Pin fRF [MHz] ZIn(RF_IN) [Ω] RIn_p//CIn_p [pF] 315 (72.4 – j298) 1300Ω//1.60 433.92 (55 – j216) 900Ω//1.60 RFIN LNA_IN ATA5745C/ATA5746C

7ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 Conditions for the sensitivity measurement: The given sensitivity values are valid for Manchester-modulated signals. For the sensitivity measurement the distance from edge to edge must be evaluated. As can be seen in Figure 6-1 on page 22, in a Manchester-modulated data stream, the time segments TEE and 2 × TEE occur. To reach the specified sensitivity for the evaluation of TEE and 2 × TEE in the data stream, the following limits should be used (TEE min, TEE max, 2 × TEE min, 2 × TEE max).

2.3 Sensitivity Versus Supply Voltage, Temperature and Frequency Offset

To calculate the behavior of a transmission system, it is important to know the reduction of the sensitivity due to several influences. The most important are frequency offset due to crystal oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage dependency of the noise figure, and IF-filter bandwidth of the receiver. Figure 2-2 and Figure 2-3 on page 8 show the typical sensitivity at 315MHz, ASK, 2.4Kbits/s and 9.6Kbits/s, Manchester, Figure 2-4 and Figure 2-5 on page 9 show a typical sensitivity at 315MHz, FSK, 2.4Kbits/s and 9.6Kbits/s, ±38kHz, Manchester versus the frequency offset between transmitter and receiver at Tamb = –40°C, +25°C, and +105°C and supply voltage VS = VS3V_AVCC = VS5V = 2.7V, 3.0V and 3.3V. Table 2-2. Input Matching to 50 Ω fRF [MHz] C1 [pF] L1 [nH] QL1 315 2.2 68 20 433.92 2.2 36 15 Table 2-3. Measured Typi cal Sensitivity FSK, ±38 kHz, Manchester, BER = 10–3 RF Frequency BR_Range_0 1.0Kbit/s BR_Range_0 2.5Kbits/s BR_Range_1 5Kbits/s BR_Range_2 10Kbits/s BR_Range_3 10Kbits/s BR_Range_3 20Kbits/s 315MHz –108dBm –108dBm –107dBm –105dBm –104dBm –104dBm 433.92MHz –107dBm –107dBm –106dBm –104dBm –103dBm –103dBm Table 2-4. Measured Typical Sensitivit y 100% ASK, Manchester, BER = 10–3 RF Frequency BR_Range_0 1.0Kbit/s BR_Range_0 2.5Kbits/s BR_Range_1 5Kbits/s BR_Range_2 10Kbits/s BR_Range_3 10Kbits/s 315MHz –114dBm –114dBm –113dBm –111dBm –109dBm 433.92MHz –113dBm –113dBm –112dBm –110dBm –108dBm Table 2-5. Limits for Sensitivity Measurements Bit Rate TEE Min TEE Typ TEE Max 2 × TEE Min 2 × TEE Typ 2 × TEE Max 1.0Kbit/s 260µs 500µs 790µs 800µs 1000µs 1340µs 2.4Kbits/s 110µs 208µs 310µs 320µs 416µs 525µs 5.0Kbits/s 55µs 100µs 155µs 160µs 200µs 260µs 9.6Kbits/s 27µs 52µs 78µs 81µs 104µs 131µs

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 As can be seen in Figure 2-5 on page 9 , the supply voltage has almost no influenc e. The temperature has an influence of about ±1.0dB, and a frequency offset of ±160kHz also influe nces by about ±1dB. All these influences, combined with the sensitivity of a typical IC (–105dB), are then within a range of –103.0dBm and –107.0dBm over temperature, supply voltage, and frequency offset. The integrated IF filter has an additional production tolerance of ±10kHz, hence, a frequency offset between the receiver and the transmitter of ±160kHz can be accepted for XTAL and XTO tolerances. Note: For the demodulator used in the Atmel ATA5745C/ATA5746C, the tolerable frequency offset does not change with the data frequency. Hence, the value of ±160kHz is valid for 1Kbit/s to 10Kbits/s. This small sensitivity change over supply voltage, frequency offset, and temperature is very unusual in such a receiver. It is achieved by an internal, very fast, and automatic frequency correction in the FSK demodulator after the IF filter, which leads to a higher system margin. This frequency correction tracks the input frequency very quickly. If, however, the input frequency makes a larger step (for example, if the system changes between different communication partners), the receiver has to be restarted. This can be done by switching back to Standby mode and then again to Active mode (pin RX 1 −−> 0 → 1) or by generating a positive pulse on pin ASK_NFSK (0 → 1 → 0).

2.4 Frequency Accuracy of the Crystals in a Combined RKE and TPM System

In a tire pressure measurement system working at 315MHz and using an Atmel® ATA5756 as transmitter and an Atmel ATA5746C is receiver, the higher frequency tolerances and the tolerance of the frequency deviation of the transmitter has to be considered. In the TPM transmitter, the crystal has a frequency error over temperature –40°C to 125°C, aging, and tolerance of ±80ppm (±25.2kHz at 315MHz). The tolerances of the XTO, the capacitors used for FSK modulation, and the stray capacitances cause an additional frequency error of ±30 ppm (±9.45kHz at 315MHz). The frequency deviation of such a transmitter varies between ±16kHz and ±24kHz, since a higher frequency deviation is equivalent to a frequency error this has to be considered as an additional ±24kHz – ±19.5kHz = ±4.5kHz frequency tolerance (19.5kHz is constant). All tolerances added, these transmitters have a worst-case frequency offset of ±39.15kHz. For the receiver in the car, a tolerance of ±160kHz –±39.15kHz = ±120.85kHz (±383.6ppm) remains. The needed frequency stability of the crystals over temperature and aging is ±383.6ppm – ±5ppm = ±378.6ppm. The aging of such a crystal is ±10ppm, leaving a reasonable ±368.6 ppm for the temperature dependency of the crystal frequency in the car. Since the receiver in the car is able to receive these TPM transmitter signals with high frequency offsets, the component specification in the key can be largely relaxed. This system calculation is based on worst-case tolerances of all the components; this leads in practice to a system with margin. For a 433.92MHz TPM system using Atmel ATA5757 as transmitter and Atmel ATA5745C as receiver, the same calculation must be done, but since the RF frequency is higher, every ppm of crystal tolerances results in higher frequency offset and either the system must have lower tolerances or a lower margin at this frequency.

2.5 RX Supply Current Versus Temperature and Supply Voltage

Table 2-7 shows the typical supply current of the receiver in Active mode versus supply voltage and temperature with VS = VS3V_AVCC = VS5V. Table 2-6. Measured Current in Active Mode ASK VS = VS3V_AVCC = VS5V 2.7V 3.0V 3.3V Tamb = –40°C 5.4mA 5.5mA 5.6mA Tamb = 25°C 6.4mA 6.5mA 6.6mA Tamb = 105°C 7.4mA 7.5mA 7.6mA Table 2-7. Measured Current in Active Mode FSK VS = VS3V_AVCC = VS5V 2.7V 3.0V 3.3V Tamb = –40°C 5.6mA 5.7mA 5.8mA Tamb = 25°C 6.6mA 6.7mA 6.8mA Tamb = 105°C 7.6mA 7.7mA 7.8mA

11ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

2.6 Blocking, Selectivity

As can be seen in Figure 2-6 on page 11, and Figure 2-7 and Figure 2-8 on page 12, the receiver can receive signals 3dB higher than the sensitivity level in the presence of large blockers of –34.5dBm or –28dBm with small frequency offsets of ±3MHz or ±20MHz. Figure 2-6, and Figure 2-7 on page 11 show the narrow-band blocking, and Figure 2-8 on page 12 shows the wide-band blocking characteristic. The measurements were done with a useful signal of 315MHz, FSK, 10Kbits/s, ±38kHz, Manchester, BR_Range2 with a level of –105dBm + 3dB = –102dBm, which is 3dB above the sensitivity level. The figures show how much larger than –102dBm a continuous wave signal can be, until the BER is higher than 10–3. The measurements were done at the 50Ω input shown in Figure 2-1 on page 6. At 3MHz, for example, the blocker can be 67.5dBC higher than –102dBm, or –102dBm + 67.5dBC = –34.5dBm. Figure 2-6. Close-in 3-dB Blocking Char acteristic and Image Response at 315MHz Figure 2-7. Narrow-band 3-dB Bloc king Characteristic at 315MHz Distance from Interfering to Receiving Signal (MHz) -10 Blocking Level (dBC) - 5 - 4 - 3 - 2 - 101 2345 Distance from Interfering to Receiving Signal (MHz) -10 Blocking Level (dBC)

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 Figure 2-8. Wide-band 3-dB Blocki ng Characteristic at 315MHz Table 2-8 shows the blocking performance measured relative to –102dBm for some frequencies. Note that sometimes the blocking is measured relative to the sensitivity level 104dBm (denoted dBS), instead of the carrier –102dBm (denoted dBC) The Atmel® ATA5745C/ATA5746C can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals at –10dBm. This is often referred to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is 95dB for 10Kbits/s Manchester (FSK). This value is useful if the transmitter and receiver are very close to each other.

2.7 In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer

If a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the performance of a receiver strongly depends on the circuits after the IF filter. Hence, the demodulator, data filter, and data slicer are important. The data filter of the Atmel ATA5745C/ATA5746C functions also as a quasi-peak detector. This results in a good suppression of above mentioned disturbers and exhibits a good carrier-to-noise performance. The required useful-signal-to-disturbing- signal ratio, at a BER of 10–3, is less than 14dB in ASK mode and less than 3dB (BR_Range_0 to BR_Range_2) and 6dB (BR_Range_3) in FSK mode. Due to the many different possible waveforms, these numbers are measured for the signal, as well as for disturbers, with peak amplitude values. Note that these values are worst-case values and are valid for any type of modulation and modulating frequency of the disturbing signal, as well as for the receiving signal. For many combinations, lower carrier-to-disturbing-signal ratios are needed. Table 2-8. Blocking 3 dB Above Sensitivity Level With BER < 10 –3 Frequency Offset Blocking Level Blocking +1.5MHz –44.5dBm 57.5dBC, 60.5dBS –1.5MHz –44.5dBm 57.5dBC, 60.5dBS +2MHz –39.0dBm 63dBC, 66dBS –2MHz –36.0dBm 66dBC, 69dBS +3MHz –34.5dBm 67.5dBC, 70.5dBS –3MHz –34.5dBm 67.5dBC, 70.5dBS +20MHz –28.0dBm 74dBC, 77dBS –20MHz –28.0dBm 74dBC, 77dBS -50 -40 -30 -20 -10 0 10 20 30 40 50 Distance from Interfering to Receiving Signal (MHz) -10 Blocking Level (dBC)

13ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

2.8 RSSI Output

The output voltage of the pin RSSI is an analog voltage, proportional to the input power level. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable dynamic range of the RSSI amplifier is 65 dB, the input power range P(RFIN) is –110dBm to –45dBm, and the gain is 15mV/dB. Figure 2-9 shows the RSSI characteristic of a typical device at 315MHz with VS3V_AVCC = VS5V = 2.7V to 3.3V and Tamb = –40°C to +105°C with a matched input as shown in Table 2-2 and Figure 2-1 on page 6. At 433.92MHz, 1dB more signal level is needed for the same RSSI results. Figure 2-9. Typical RSSI Charac teristic at 315MHz Versus Temperature and Supply Voltage As can be seen in Figure 2-9 on page 13, for single devices there is a variance over temperature and supply voltage range of ±3dB. The total variance over production, temperature, and supply voltage range is ±9dB.

2.9 Frequency Synthesizer

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is divided by the factor 24 (Atmel® ATA5746C) or 32 (Atmel ATA5745C). The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to the fully integrated loop filter, and thereby generates the control voltage for the VCO. By means of that configuration, the VCO is controlled in a way, such that fLO / 24 (fLO / 32) is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO =f LO / 24 (fXTO =f LO / 32). The synthesizer has a phase noise of –130dBC/Hz at 3MHz and spurs of –75dBC. Care must be taken with the harmonics of the CLK output signal, as well as with the harmonics produced by a microprocessor clocked using the signal, as these harmonics can disturb the reception of signals. -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Pin (dBm) 1.5 1.4 1.3 1.6 1.7 1.2 1.1 0.9 0.8 0.7 0.6 0.5 0.4 V_RSSI (V) max; +9dB 2.7V, -40°C 3.0V, -40°C 3.3V, -40°C 2.7V, 27°C 3.0V, 27°C 3.3V, 27°C 2.7V, 105°C 3.0V, 105°C 3.3V, 105°C min; -9dB

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 3. XTO The XTO is an amplitude-regulated Pierce oscillator type with external load capacitances (2 × 16pF). Due to additional internal and board parasitics (CP) of approximately 2pF on each side, the load capacitance amounts to 2 × 18pF (9pF total). The XTO oscillation frequency fXTO is the reference frequency for the integer-N synthesizer. When designing the system in terms of receiving and transmitting frequency offset, the accuracy of the crystal and XTO have to be considered. The XTO’s additional pulling (including the RM tolerance) is only ±5ppm. The XTAL versus temperature, aging, and tolerances is then the main source of frequency error in the local oscillator. The XTO frequency depends on XTAL properties and the load capacitances CL1,2 at pin XTAL1 and XTAL2. The pulling (p) of fXTO from the nominal fXTAL is calculated using the following formula: Cm, the crystal's motional capacitance; C0, the shunt capacitance; and CLN, the nominal load capacitance of the XTAL, are found in the datasheet. CL is the total actual load capacitance of the crystal in the circuit, and consists of CL1 and CL2 connected in series. Figure 3-1. Crystal Equivalent Circuit With Cm ≤ 10fF, C0 ≥ 1.0pF, CLN = 9pF and CL1,2 = 16pF ±1%, the pulling amounts to P ≤ ±1ppm. The C0 of the XTAL has to be lower than CLmin / 2 = 7.9pF for a Pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is risk of an unstable oscillation. To ensure proper start-up behavior, the small signal gain and the negative resistance provided by this XTO at start is very large. For example, oscillation starts up even in the worst case with a crystal series resistance of 1.5kΩ at C0 ≤ 2.2pF with this XTO. The negative resistance is approximately given by with Z1 and Z2 as complex impedances at pins XTAL1 and XTAL2, hence Z1 =– j/( 2 × p × fXTO × CL1)+5 Ω and Z2 =– j/( 2 × p × fXTO × CL2)+5 Ω. Z3 consists of crystal C0 in parallel with an internal 110-kΩ resistor, hence Z3 =– j/( 2 × p × fXTO × C0) / 110kΩ, gm is the internal transconductance between XTAL1 and XTAL2, with typically 20mS at 25°C. With fXTO = 13.5MHz, gm = 20mS, CL = 9pF, and C0 = 2.2pF, this results in a negative resistance of about 2kΩ. The worst case for technology, supply voltage, and temperature variations is then always higher than 1.4kΩ for C0 ≤ 2.2pF. Due to the large gain at start, the XTO is able to meet a very low start-up time. The oscillation start-up time can be estimated with the time constant τ. p Cm CL2CL1 Cm Lm Rm CL = CL1 x CL2/(CL1 + CL2) XTAL Crystal Equivalent Circuit Re Zxtocore{} Re Z1 Z3 Z2 Z3 Z1 Z3 gm××+×+× = τ 2 4 π2 fXTAL

2 Cm Re Zxtocore() Rm+()××××

15ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 After 10τ to 20τ, an amplitude detector detects the oscillation amplitude and sets XTO_OK to High if the amplitude is large enough; this activates the CLK_OUT output if it is enabled via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the DVCC voltage also have to be fulfilled. It is recommended to use a crystal with Cm = 3.0fF to 10fF, CLN =9 p F , Rm < 120Ω and C0 = 1.0pF to 2.2pF. Lower values of Cm can be used, slightly increasing the start-up time. Lower values of C0 or higher values of Cm (up to 15fF) can also be used, with only little influence on pulling. Figure 3-2. XTO Block Diagram The relationship between fXTO and the fRF is shown in Table 3-1. Attention must be paid to the harmonics of the CLK_OUT output signal fCLK_OUT as well as to the harmonics produced by an microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the RF input. If the CLK_OUT signal is used, it must be carefully laid out on the application PCB. The supply voltage of the microcontroller must also be carefully blocked. Table 3-1. Calculation of f RF Frequency [MHz] fXTO [MHz] fRF 433.92 (Atmel ATA5745C) 13.57375 fXTO x 32 – 440kHz 315.0 (Atmel ATA5746C) 13.1433 fXTO x 24 – 440kHz CL2CL1 fDCLK fFXTO CLK_OUT_CTRL1CLK_OUT_CTRL0 XTO_OK XTAL1 XTAL2 CLK_OUT Amplitude Detector Divider /16 Divider /3, /6, /12

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

3.1 Pin CLK_OUT

Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in Standby and Active modes. The frequency fCLK_OUT can be adjusted via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows: The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recommended that CLK_OUT be switched off during Standby mode.

3.2 Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry is derived from one clock. As seen in Figure 3-2 on page 15, this clock cycle, TDCLK, is derived from the crystal oscillator (XTO) in combination with a divider. TDCLK controls the following application relevant parameters: - Debouncing of the data signal stream - Start-up time of the RX signal path The start-up time and the debounce characteristic depend on the selected bit rate range (BR_Range) which is defined by pins BR0 and BR1. The clock cycle T XDCLK is defined by the following formulas for further reference: BR_Range  BR_Range 0: TXDCLK = 8 × TDCLK BR_Range 1: TXDCLK = 4 × TDCLK BR_Range 2: TXDCLK = 2 × TDCLK BR_Range 3: TXDCLK = 1 × TDCLK Table 3-2. Setting of f CLK_OUT CLK_OUT_CTRL1 CLK_OUT_CTRL0 Function 0 0 Clock on pin CLK_OUT is switched off (Low level on pin CLK_OUT) 0 1 fCLK_OUT =f XTO /3 1 0 fCLK_OUT =f XTO /6 1 1 fCLK_OUT =f XTO /1 2 fDCLK fXTO

17ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 4. Sensitivity Reduction The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSense. RSense is connected between the pins SENSE and VS3V_AVCC (see Figure 10-1 on page 26). The output of the comparator is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity. If the level on input pin SENSE_CTRL is low, the receiver operates at full sensitivity. If the level on input pin SENSE_CTRL is high, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSense, the maximum sensitivity by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 2-1 on page 6 and exhibits the best possible sensitivity. If the sensitivity reduction feature is not used, pin SENSE can be left open, pin SENSE_CTRL must be set to GND. To operate with reduced sensitivity, pin SENSE_CTRL must be set to high before the RX signal path will be enabled by setting pin RX to high (see Figure 4-1 on page 17). As long as the RSSI level is lower than VTh_red (defined by the external resistor RSense) no data stream is available on pin DATA_OUT (low level on pin DATA_OUT). An internal RS flip-flop will be set to high the first time the RSSI voltage crosses VTh_red, and from then on the data stream will be available on pin DATA_OUT. From then on the receiver also works with full sensitivity. This makes sure that a telegram will not be interrupted if the RSSI level varies during the transmission. The RS flip-flop can be set back, and thus the receiver switched back to reduced sensitivity, by generating a positive pulse on pin ASK_NFSK (see Figure 4-2 on page 18). In FSK mode, operating with reduced sensitivity follows the same way. Figure 4-1. Reduced Sensitivity Active RSSI RX DATA_OUT SENSE_CTRL ASK_NFSK ENABLE tStartup_PLL VTh_red tStartup_Sig_Proc

19ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

5.1 OFF Mode

A low level on pin RX and ENABLE will set the receiver to OFF mode (low power mode). In this mode, the crystal oscillator is shut down and no clock is available on pin CLK_OUT. The receiver is not sensitive to a transmitter signal in this mode.

5.2 Standby Mode

The receiver activates the Standby mode if pin ENABLE is set to “1”. In Standby mode, the XTO is running and the clock on pin CLK_OUT is available after the start-up time of the XTO has elapsed (dependent on pin CLK_OUT_CTRL0 and CLK_OUT_CTRL1). During Standby mode, the receiver is not sensitive to a transmitter signal. In Standby mode, the RX signal path is disabled and the power consumption IStandby is typically 50µA (CLK_OUT output off, VS3V_AVCC = VS5V = 3V). The exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the section “Electrical Characteristics: General” on page 27 for the appropriate application case. Figure 5-2. Standby Mode (CLK_OUT_CTRL0 or CLK_OUT_CTRL1 = 1)

5.3 Active Mode

The Active mode is enabled by setting the level on pin RX to high. In Active mode, the RX signal path is enabled and if a valid signal is present it will be transferred to the connected microcontroller. During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing circuit starts up (TStartup_Sig_Proc). After the start-up time, all circuits are in stable condition and ready to receive. The duration of the start-up sequence depends on the selected bit rate range. Table 5-1. Standby Mode RX ENABLE Function 0 0 OFF mode Table 5-2. Standby Mode RX ENABLE Function 0 1 Standby mode CLK_OUT ENABLE Standby Mode tXTO_Startup Table 5-3. Active Mode RX ENABLE Function 1 1 Active mode

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 Figure 5-3. Active Mode Table 5-4. Start-up Time BR1 BR0 Atmel ATA5745C (433.92MHz) Atmel ATA5746C (315MHz) TStartup_PLL TStartup_Sig_Proc TStartup_PLL TStartup_Sig_Proc 0 0 261µs 1096µs 269µs 1132µs 0 1 644µs 665µs 1 0 417µs 431µs 1 1 304µs 324µs Table 5-5. Modulation Scheme ASK_NFSK RFIN at Pin LNA_IN Level at Pin DATA_OUT fFSK_H 1 fFSK_L 0 fASK on 1 fASK off 0 DATA_OUT valid tStartup_PLL tStartup_Sig_Proc IStartup_PLL IActive IActiveIStandby Startup CLK_OUT RX DATA_OUT ENABLE Standby Mode Active Mode

21ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 6. Bit Rate Ranges Configuration of the bit rate ranges is carried out via the two pins BR0 and BR1. The microcontroller uses these two interface lines to set the corner frequencies of the band-pass data filter. Switching the bit rate ranges while the RF front end is in Active mode can be done on the fly and will not take longer than 100 µs if done while remaining in either ASK or FSK mode. If the modulation scheme is changed at the same time, the switching time is (T Startup_Sig_Proc, see Figure 7-1 on page 23). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sensitivity of the receiver, edge-to-edge transition times of incoming data should not be less than the minimum for the selected BR_Range. Table 6-1. BR Ranges ASK BR1 BR0 BR_Range Recommended Bit Rate (Manchester)(2) Minimum Edge-to-edge Time Period TEE of the Data Signal(3) Edge-to-edge Time Period TEE of the Data Signal During the Start-up Period(4) 0 0 BR_Range0 1.0Kbit/s to 2.5Kbits/s 200µs 200µs to 500µs 0 1 BR_Range1 2.0Kbits/s to 5.0Kbits/s 100µs 100µs to 250µs 1 0 BR_Range2 4.0Kbits/s to 10.0Kbits/s 50µs 50µs to 125µs 1 1 BR_Range3 8.0Kbits/s to 10.0Kbits/s 50µs 50µs to 62.5µs Table 6-2. BR Ranges FSK BR1 BR0 BR_Range Recommended Bit Rate (Manchester)(2) Minimum Edge-to-edge Time Period TEE of the Data Signal(3) Edge-to-edge Time Period TEE of the Data Signal During the Start-up Period(4) 0 0 BR_Range0 1.0Kbit/s to 2.5Kbits/s 200µs 200µs to 500µs 0 1 BR_Range1 2.0Kbits/s to 5.0Kbits/s 100µs 100µs to 250µs 1 0 BR_Range2 4.0Kbits/s to 10.0Kbits/s 50µs 50µs to 125µs 1 1 BR_Range3 8.0Kbits/s to 20.0Kbits/s 25µs 25µs to 62.5µs Notes: 1. If during the start-up period (T Startup_PLL +T Startup_Sig_Proc) there is no RF signal, the data filter settles to the noise floor, leading to noise on pin DATA_OUT. 2. As can be seen, a bit stream of, for example, 2.5Kbits/s can be received in BR_Range0 and BR_Range1 (overlapping BR_Ranges). To get the full sensitivity, always use the lowest possible BR_Range (here, BR_Range0). The advantage in the next higher BR_Range (BR_Range1) is the shorter start-up period, meaning lower current consumption during Polling mode. Thus, it is a decision between sensitivity and cur- rent consumption. 3. The receiver is also capable of receiving non-Man chester-modulated signals, such as PWM, PPM, VPWM, NRZ. In ASK mode, the header and blanking periods occurring in Keeloq-like protocols (up to 52ms) are supported. 4. To ensure an accurate settling of the data filter during the start-up period (TStartup_PLL + TStartup_Sig_Proc), the edge-to-edge time TEE of the data signal (preamble) must be inside the given limits during this period.

23ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 7. ASK_NFSK The ASK_NFSK pin allows the microcontroller to rapidly switch the RF front end between demodulation modes. A logic 1 on this pin selects ASK mode, and a logic 0 FSK mode. The time to change modes (TStartup_Sig_Proc) depends on the bit rate range being selected (not current bit rate range) and is given in Table 5-4 on page 20. This response time is specified for applications that require an ASK preamble followed by FSK data (for typical TPM applications). During TStartup_Sig_Proc, the level on pin DATA_OUT is low. Figure 7-1. ASK Preamble 2.4Kbits/s followed by FSK Data 9.6Kbits/s RX ASK_NFSK DATA_OUT Data valid BR3Data valid BR0 BR0 BR1 ENABLE TStartup_Sig_Proc

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 8. Polling Current Calculation Figure 8-1. Polling Cycle In an RKE and TPM system, the average chip current in Polling mode, IPolling, is an important parameter. The polling period must be controlled by the connected microcontroller via the pins ENABLE and RX. The polling current can be calculated as follows: IPolling =( TStartup_PLL /T Polling_Period) × IStartup_PLL +( TStartup_Sig_Proc /T Polling_Period) × IActive + (TBitcheck /T Polling_Period) × IActive +( TPolling_Period –T Startup_PLL –T Startup_Sig_Proc –T Bitcheck)/ TPolling_Period × IStandby TStartup_PLL: depends on 315MHz/433.92MHz application. TStartup_Sig_Proc: depends on 315MHz/433.92MHz application and the selected bit rate range. TBitcheck: depends on the signal bit rate (1 / Signal_Bit_Rate). TPolling_Period: depends on the transmitter telegram (preburst). IStartup_PLL: depends on 3V or 5V application and the setting of pin CLK_OUT. IActive: depends on 3V or 5V application, ASK or FSK mode and the setting of pin CLK_OUT. IStandby: depends on 3V or 5V application and the setting of pin CLK_OUT. Example:- 315-MHz application (Atmel ATA5746C), bit rate: 9.6Kbits/s, TPolling_Period =8 m s --> TStartup_PLL = 269µs --> TStartup_Sig_Proc = 324µs (Bit Rate Range 3) --> TBitcheck = 104µs 3V application; ASK mode, CLK_OUT disabled --> IStartup_PLL =4 . 5 m A --> IActive =6 . 5 m A --> IStandby = 0.05mA --> IPolling = 0.545mA IStandby IStandby IActive IStartup_PLL IActive IStartup_PLL RX ISupply ENABLE TBitcheck (= 1 / Signal_Bitrate (average) TStartup_PLL (Startup RF-PLL) TStartup_Sig_Proc (Startup Signal Processing)

25ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 9. 3V Application Figure 9-1. 3V Application Note: Paddle (backplane) must be connected to GND TEST2 TEST1 ENABLE CLK_OUT VS5V GND VS3V_AVCC DVCC XTAL1 XTAL2 BR1 RX BR0 ASK_NFSK CDEM DATA_OUT CLK_OUT_CTRL0 CLK_OUT_CTRL1 output output output output input output VCCVSS TEST3 LNA_IN LNA_GND SENSE SENSE_CTRL RSSI RFIN 18pF Microcontroller ATA5745C/ ATA5746C 18pF 68nF 15nF 2.2pF 68nH/36nH 315MHz/433.92MHz 68nF VCC = 2.7V to 3.3V

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 10. 5V Application Figure 10-1. 5V Application with Reduced/Full Sensitivity Note: Paddle (backplane) must be connected to GND. TEST2 TEST1 ENABLE CLK_OUT VS5V GND VS3V_AVCC DVCC XTAL1 XTAL2 BR1 RX BR0 ASK_NFSK CDEM DATA_OUT CLK_OUT_CTRL0 CLK_OUT_CTRL1 output output output output output input output VCCVSS TEST3 LNA_IN LNA_GND SENSE SENSE_CTRL RSSI RFIN RSense 18pF Microcontroller ATA5745C/ ATA5746C 18pF 68nF 15 nF 2.2pF 2.2µF 68nH/36nH 315MHz/433.92MHz 68nF VCC = 4.5V to 5.5V

27ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 11. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Junction temperature Tj +150 °C Storage temperature Tstg –55 +125 °C Ambient temperature Tamb –40 +105 °C Supply voltage VS5V VS +6 V ESD (Human Body Model ESD S 5.1) every pin HBM –4 +4 kV ESD (Machine Model JEDEC A115A) every pin MM –200 +200 V ESD (Field Induced Charge Device Model ESD STM 5.3.1-1999) every pin FCDM –500 +500 V Maximum input level, input matched to 50Ω Pin_max 0 dBm 12. Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 35 K/W 13. Electrical Characteristics: General Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

1 OFF Mode

1.1 Supply current in OFF

VVS3V_AVCC =V VS5V ≤ 3V VVS5V =5 V CLK_OUT disabled 10, 11

10 ISOFF

µA µA A A

2 Standby Mode

2.1 Supply current

V VS3V_AVCC =V VS5V ≤ 3V CLK_OUT disabled 10, 11 IStandby 50 80 µA A XTO running VVS5V =5 V CLK_OUT disabled 10, 11 IStandby 50 80 µA A

2.2 System start-up time

XTAL: Cm =5 f F , C0 =1 . 8 p F , Rm = 15Ω TXTO_Startup 0.3 0.8 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN).

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

2.3 Active mode start-up

BR_Range_3 Atmel ATA5745C Atmel ATA5746C TStartup_PLL + TStartup_Sig_Proc 565 593 µs µs A

3 Active Mode

3.1 RF operating frequency

Atmel ATA5746C 14 fRF 313 317 MHz A Atmel ATA5745C 14 fRF 433 435 MHz A

3.2 Supply current Active

VVS3V_AVCC =V VS5V =3 V ASK mode CLK_OUT disabled SENSE_CTRL = 0 10, 11 IActive 6.5 9.6 mA A VVS3V_AVCC =V VS5V =3 V FSK mode CLK_OUT disabled SENSE_CTRL = 0 10, 11 IActive 6.7 9.8 mA A VVS5V =5 V ASK mode CLK_OUT disabled SENSE_CTRL = 0 10 IActive 6.7 9.8 mA A VVS5V =5 V FSK mode CLK_OUT disabled SENSE_CTRL = 0 10 IActive 6.9 10 mA A

3.3 Supply current Polling

VVS3V_AVCC =V VS5V =3 V TPolling_Period = 8ms BR_Range_3, ASK mode, CLK_OUT disabled Data rate = 9.6Kbits/s 10, 11 IPolling 545 µA C

3.4 Input sensitivity FSK

fRF = 315MHz FSK deviation f DEV = ±38kHz BER = 10–3 Tamb = 25°C Bit rate 9.6Kbits/s BR2 (14) PREF_FSK –103 –105 –106.5 dBm B Bit rate 2.4Kbits/s BR0 (14) PREF_FSK –106 –108 –109.5 dBm B FSK deviation ±18kHz to ±50kHz Bit rate 9.6Kbits/s BR2 (14) PREF_FSK –101 dBm B Bit rate 2.4Kbits/s BR0 (14) PREF_FSK –104 dBm B 13. Electrical Characteristics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN).

29ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

3.5 Input sensitivity ASK

fRF = 315MHz ASK 100% level of carrier, BER = 10 Tamb = 25°C Bit rate 9.6Kbits/s BR2 (14) PREF_ASK –109 –111 –112.5 dBm B Bit rate 2.4Kbits/s BR0 (14) PREF_ASK –112 –114 –115.5 dBm B 3.6 Sensitivity change at fRF = 433.92MHz compared to fRF = 315MHz fRF = 315MHz to fRF = 433.92MHz P=P REF_ASK + ΔPREF1 P=P REF_FSK + ΔPREF1 (14) ΔPREF1 +1 dB B 3.7 Sensitivity change versus temperature, supply voltage and frequency offset FSK fDEV = ±38kHz ΔfOFFSET ≤ ±160kHz ASK 100% ΔfOFFSET ≤ ±160kHz P = PREF_ASK + ΔPREF1 + ΔPREF2 P = PREF_FSK + ΔPREF1 + ΔPREF2 (14) ΔPREF2 +4.5 –1.5 B 3.8 Reduced sensitivity RSense connected from pin SENSE to pin VS3V_AVCC PRef_Red dBm (peak level) RSense = 62kΩ fin = 433.92MHz –76 dBm C RSense = 82kΩ fin = 433.92MHz –88 dBm C RSense = 62kΩ fin = 315MHz –76 dBm C RSense = 82 kΩ fin = 315 MHz –88 dBm C Reduced sensitivity variation over full operating range RSense = 62kΩ RSense = 82kΩ PRed = PRef_Red + PΔRed ΔPRed –10 +10 dB

3.9 Maximum frequency

in FSK mode (fRF is the center frequency of the FSK signal with f BIT = 10Kbits/s fDEV = ±38kHz (14) ΔfOFFSET –160 +160 kHz B 13. Electrical Characteristics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN).

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

3.10 Supported FSK

loss of sensitivity. Note that the tolerable frequency offset is 12kHz lower for f DEV = ±50kHz than for fDEV = ±38kHz, hence, ΔfOFFSET ≤ ±148kHz (14) fDEV ±18 ±38 ±50 kHz B

3.11 System noise figure

fRF = 315MHz (14) NF 6.0 9 dB B fRF = 433.92MHz (14) NF 7.0 10 dB B

3.12 Intermediate frequency

fRF = 433.92MHz fIF 440 kHz A fRF = 315MHz fIF 440 kHz A

3.13 System bandwidth

information only! Note that for crystal and system frequency offset calculations, Δf OFFSET must be used. (14) SBW 435 kHz A 3.14 System out-band 3rd-order input intercept point Δfmeas1 = 1.8MHz Δfmeas2 = 3.6MHz fRF = 315MHz (14) IIP3 –24 dBm C fRF = 433.92MHz (14) IIP3 –23 dBm C

3.15 System outband input 1-

Δfmeas1 = 1MHz fRF = 315MHz (14) I1dBCP –31 –36 dBm C fRF = 433.92MHz (14) I1dBCP –30 –35 dBm C

3.16 LNA input impedance

fRF = 315MHz 14 Zin_LNA (72.4 – j298) Ω C fRF = 433.92MHz 14 Zin_LNA (55 – j216) Ω C

3.17 Maximum peak RF input

level, ASK and FSK BER < 10–3, ASK: 100% (14) PIN_max +5 –10 dBm C FSK: fDEV = ±38kHz (14) PIN_max +5 –10 dBm C

3.18 LO spurs at LNA_IN

f < 1GHz (14) –57 dBm C f >1GHz (14) –47 dBm C fLO = 315.44MHz 2 × fLO 4 × fLO (14) –90 –94 –68 dBm C fLO = 434.36MHz 2 × fLO 4 × fLO (14) –92 –88 –58 dBm C

3.19 Image rejection

fRF = 315MHz (14) 24 30 dB A fRF = 433.92MHz (14) 24 30 dB A 13. Electrical Characteristics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN).

31ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

3.20 Useful signal to interferer

interferer for BER < 10 with any modulation scheme of interferer FSK BR_Ranges 0, 1, 2 (14) SNRFSK0-2 2 3 dB B FSK BR_Range_3 (14) SNRFSK3 4 6 dB B ASK (PRF < PRFIN_High) (14) SNRASK 10 14 dB B

3.21 RSSI output

Dynamic range (14),17 DRSSI 65 dB A Lower level of range fRF = 315MHz fRF = 433.92MHz (14),17 PRFIN_Low –110 dBm A Upper level of range fRF = 315MHz fRF = 433.92MHz (14),17 PRFIN_High –45 dBm A Gain (14),17 15 mV/dB A Output voltage range (14),17 VRSSI 350 1675 mV A

3.22 Output resistance

RSSI pin 17 RRSSI 8 10 12.5 kΩ C

3.23 Blocking

Sensitivity (BER = 10–3) is reduced by 3dB if a continuous wave blocking signal at ±Δf is ΔP Block higher than the useful signal level (Bit rate = 10Kbits/s, FSK, f DEV ±38kHz, Manchester code, BR_Range2) fRF = 315MHz Δf ±1.5MHz Δf ±2MHz Δf ±3MHz Δf ±10MHz Δf ±20MHz (14) ΔPBlock 57.5 63.0 67.5 72.0 74.0 dBC C fRF = 433.92MHz Δf ±1.5MHz Δf ±2MHz Δf ±3MHz Δf ±10MHz Δf ±20MHz (14) ΔPBlock 56.5 62.0 66.5 71.0 73.0 dBC C

3.24 CDEM Capacitor connected to

pin 23 (CDEM) 23 –5% 15 +5% nF D 13. Electrical Characteristics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN).

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14

4 XTO

4.1 Transconductance XTO

At startup; after startup the amplitude is regulated to VPPXTAL 7, 8 gm, XTO 20 mS B

4.2 XTO start-up time

C0 ≤ 2.2pF Cm < 14fF Rm ≤ 120Ω 7, 8 TXTO_Startup 300 800 µs A 4.3 Maximum C0 of XTAL 7, 8 C0max 3.8 pF D 4.4 Pulling of LO frequency fLO due to XTO, CL1 and CL2 versus temperature and supply changes 1.0pF ≤ C0 ≤ 2.2pF Cm = 4.0fF to 7.0fF Rm ≤ 120Ω 3 ΔfXTO –5 +5 ppm C

4.5 Amplitude XTAL after

Cm =5 f F , C0 =1 . 8 p F Rm = 15Ω V(XTAL1, XTAL2) peak-to-peak value 7, 8 VPPXTAL 700 mVpp C V(XTAL1) peak-to-peak value 7, 8 VPPXTAL 350 mVpp C 4.6 Maximum series resistance R m of XTAL at startup C0 ≤ 2.2pF, small signal start impedance, this value is important for crystal oscillator startup 7, 8 ZXTAL12_START –1400 –2000 Ω B 4.7 Maximum series resistance R m of XTAL after startup C0 ≤ 2.2pF Cm < 14fF 7, 8 Rm_max 15 120 Ω B

4.8 Nominal XTAL load

fRF = 433.92MHz fRF =3 1 5 M H z 7, 8 fXTAL 13.57375

13.1433 MHz D

4.9 External CLK_OUT

CLK_OUT_CRTL1 = 0 CLK_OUT_CTRL0 = 0 --> CLK_OUT disabled 3 fCLK_OUT fCLK disabled (low level on pin CLK_OUT) MHz A CLK_OUT_CRTL1 = 0 CLK_OUT_CTRL0 = 1 --> division ratio = 3 CLK_OUT_CRTL1 = 1 CLK_OUT_CTRL0 = 0 --> division ratio = 6 CLK_OUT_CRTL1 = 1 CLK_OUT_CTRL0 = 1 --> division ratio = 12 13. Electrical Characteristics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN). fCLK fXTO fCLK fXTO fCLK fXTO

33ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 fRF = 433.92MHz CLK_OUT division ratio = 3 = 6 = 12 CLK_OUT has nominal 50% duty cycle 3 fCLK_OUT 4.52458 2.26229 1.13114 MHz D fRF =3 1 5 M H z CLK_OUT division ratio = 3 = 6 = 12 CLK_OUT has nominal 50% duty cycle 3 fCLK_OUT 4.3811 2.190 1.0952 MHz D

4.10 DC voltage after startup

VDC (XTAL1, XTAL2) XTO running (Standby mode, Active mode) 7,8 VDCXTO –250 –45 mV C

5 Synthesizer

5.1 Spurs in Active mode

At ±fCLK_OUT, CLK_OUT enabled (division ratio = 3) f RF =3 1 5 M H z fRF = 433.92MHz SPRX –75 –70 dBC C at ±fXTO fRF =3 1 5 M H z fRF = 433.92MHz SPRX –75 –70 dBC A

5.2 Phase noise at 3MHz

fRF =3 1 5 M H z fRF = 433.92MHz LRX3M –130 –127 dBC/Hz A

5.3 Phase noise at 20MHz

Active mode Noise floor LRX20M –135 –132 dBC/Hz B

6 Microcontroller Interface

6.1 CLK_OUT output rise

fCLK_OUT <4 . 5 M H z CL =1 0 p F CL = Load capacitance on pin CLK_OUT 2.7V ≤ V VS5V ≤ 3.3V or 4.5V ≤ VVS5V ≤ 5.5V 20% to 80% VVS5V trise tfall ns ns C

6.2 Internal equivalent

3 CCLK_OUT 8 pF C

1. Electrical Characteristics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 7 (RFIN).

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 14. Electrical Characteristic: 3V Application Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

7.1 Supply current in OFF

VVS3V_AVCC =V VS5V ≤ 3V CLK_OUT disabled 10, 11 ISOFF 2 µA A

7.2 Current in Standby

mode (XTO is running) VVS3V_AVCC = VVS5V ≤ 3V external load C on pin CLK_OUT = 12pF CLK enabled (division ratio 3) CLK enabled (division ratio 6) CLK enabled (division ratio 12) CLK disabled 10, 11 IStandby 420 290 220 670 460 350 µA C C C A

7.3 Current during

TStartup_PLL VVS3V_AVCC = VVS5V ≤ 3V CLK disabled 10, 11 IStartup_PLL 4.5 mA C

7.4 Current in Active mode

VVS3V_AVCC = VVS5V ≤ 3V CLK disabled SENSE_CTRL = 0 10, 11 IActive 6.5 9.6 mA A

7.5 Current in Active mode

VVS3V_AVCC = VVS5V ≤ 3V CLK disabled SENSE_CTRL = 0 10, 11 IActive 6.7 9.8 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

35ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 15. Electrical Characteristics: 5V Application Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

8.1 Supply current in OFF

VVS5V =5 V CLK_OUT disabled 10 ISOFF 2 µA A

8.2 Current in Standby

mode (XTO is running) VVS5V ≤ 5V external load C on pin CLK_OUT = 12pF CLK enabled (division ratio 3) CLK enabled (division ratio 6) CLK enabled (division ratio 12) CLK disabled

10 IStandby

µA C C C A

8.3 Current during

TStartup_PLL VVS5V =5 V CLK disabled 10 IStartup_PLL 4.7 mA C

8.4 Current in Active mode

VVS5V =5 V CLK disabled SENSE_CTRL = 0 10 IActive 6.7 9.8 mA A

8.5 Current in Active mode

VVS5V =5 V CLK disabled SENSE_CTRL = 0 10 IActive 6.9 10 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 16. Digital Timing Characteristics Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

9 Basic Clock Cycle of the Digital Circuitry

9.1 Basic clock cycle TDCLK 16 / fXTO 16 / fXTO µs A

9.2 Extended basic clock

BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 TXDCLK × T DCLK × T DCLK µs A

10 Active Mode

10.1 Startup PLL TStartup_PLL

15 µs + 208 × TDCLK µs A

10.2 Startup signal

BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 TStartup_Sig_Proc 929.5 545.5 353.5 257.5 × T DCLK 929.5 545.5 353.5 257.5 × TDCLK A

10.3 Bit rate range

BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 FSK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 2.0 4.0 8.0 1.0 2.0 4.0 8.0 2.5 5.0 10.0 10.0 2.5 5.0 10.0 20.0 Kbits/s A 10.4 Minimum time period between edges at pin DATA_OUT BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3

24 TDATA_OUT_min

10 × TXDCLK µs A 10.5 Edge-to-edge time period of the data signal for full sensitivity in Active mode BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 TDATA_OUT 200 100 500 250 125 62.5 µs B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

37ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 17. Digital Port Characteristics Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

11 Digital Ports

11.1 ENABLE input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

6 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 6 VIh 0.8 × VS V A 11.2 RX input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

19 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 19 VIh 0.8 × VS V A 11.3 BR0 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

20 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 20 VIh 0.8 × VS V A 11.4 BR1 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

21 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 21 VIh 0.8 × VS V A 11.5 ASK_NFSK input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

22 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 22 VIh 0.8 × VS V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 11.6 SENSE_CTRL input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

16 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 16 VIh 0.8 × VS V A 11.7 CLK_OUT_CTRL0 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

5 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 5 VIh 0.8 × VS V A 11.8 CLK_OUT_CTRL1 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V

4 VIl

0.2 × VS 0.12 × VS V A - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 4 VIh 0.8 × VS V A

11.9 TEST1 input

11.10 TEST2 output

11.11 TEST3 input

1. Digital Port Characteristics (Continued) Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

39ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 11.12 DATA_OUT output - Saturation voltage low VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = 250µA 24 Vol 0.15 0.4 V B - Saturation voltage high VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = –250µA 24 Voh VVS – 0.4 VVS –

0.15 V B

11.13 CLK_OUT output - Saturation voltage low VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = 100µA 3 Vol 0.15 0.4 V B - Saturation voltage high VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = –100µA 3 Voh VVS – 0.4 VVS –

1. Digital Port Characteristics (Continued) Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 19. Package Information 18. Ordering Information Extended Type Number Package MOQ Remarks ATA5745C-PXQW-1 QFN24 6000pcs 5mm × 5mm, Pb-free, 433.92MHz ATA5746C-PXQW-1 QFN24 6000pcs 5mm × 5mm, Pb-free, 315MHz Package Drawing Contact: packagedrawings@atmel.com GPC DRAWING NO. REV. TITLE 6.543-5132.02-4 1 10/18/13 Package: VQFN_5x5_24L Exposed pad 3.6x3.6 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM NOTE MAXSymbol Dimensions in mm specifications according to DIN technical drawings 0.035 0.050.0A1 55 . 14.9E 0.25 0.30.2b 0.65e 0.4 0.450.35L 3.6 3.73.5E2 3.6 3.73.5D2 55 . 14.9D 0.21 0.260.16A3 0.85 0.90.8A Top View D PIN 1 ID E Side View A b LZ 10:1 Bottom View e 24 19 Z

41ATA5745C/ATA5746C [DATASHEET] 9249C–RKE–10/14 20. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9249C-RKE-10/14

• Section 18 “Ordering Information” on page 40 updated
• Section 19 “Package Information” on page 40 updated 9249B-RKE-08/12
• Section 13 “Electrical Characteristics: General” on pages 27 to 33 changed
• Section 14 “Electrical Characteristic: 3V Application” on page 34 changed
• Section 15 “Electrical Characteristic: 5V Application” on page 35 changed

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