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Document overview
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Technical content
Features
- Transparent RF Receiver ICs for 315 MHz (ATA5746) and 433.92 MHz (ATA5745) With High Receiving Sensitivity Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter High FSK/ASK Sensitivity:–105 dBm (ATA5746, FSK, 9.6 Kbits/s, Manchester, BER 10-3) –114 dBm (ATA5746, ASK, 2.4 Kbits/s, Manchester, BER 10-3) –104 dBm (ATA5745, FSK, 9.6 Kbits/s, Manchester, BER 10-3) –113 dBm (ATA5745, ASK, 2.4 Kbits/s, Manchester, BER 10-3) Supply Current: 6.5 mA in Active Mode (3V, 25°C, ASK Mode) Data Rate: 1 Kbit/s to 10 Kbits/s Manchester ASK, 1 Kbit/s to 20 Kbits/s Manchester FSK With Four Programmable Bit Rate Ranges Switching Between Modulation Types ASK/FSK and Different Data Rates Possible in ≤1 ms Typically, Without Hardware Modification on Board to Allow Different Modulation Schemes for RKE, TPMS Low Standby Current: 50 µA at 3V, 25°C ASK/FSK Receiver Uses a Low-IF Architecture With High Selectivity, Blocking, and Low Intermodulation (Typical 3-dB Blocking 68.0 dBC at ±3 MHz/74.0 dBC at ±20.0 MHz, System I1dBCP = –31d B m / S y s t e m I I P 3 = – 2 4d B m ) Telegram Pause Up to 52 ms Supported in ASK Mode Wide Bandwidth AGC to Handle Large Out-of-band Blockers above the System I1dBCP 440-kHz IF Frequency With 30-dB Image Rejection and 420-kHz IF Bandwidth to Support PLL Transmitters With Standard Crystals or SAW-based Transmitters RSSI (Received Signal Strength Indicator) With Output Signal Dynamic Range of 65 dB Low In-band Sensitivity Change of Typically ±2.0 dB Within ±160-kHz Center Frequency Change in the Complete Temperature and Supply Voltage Range Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer Fast and Stable XTO Start-up Circuit (> –1.4 kΩ Worst-case Start Impedance) Clock Generation for Microcontroller ESD Protection at all Pins (±4 kV HBM, ±200V MM, ±500V FCDM) Dual Supply Voltage Range: 2.7V to 3.3V or 4.5V to 5.5V Temperature Range: –40°C to +105°C Small 5 mm × 5 mm QFN24 Package
Applications
Automotive Keyless Entry and Tire Pressure Monitoring Systems Alarm, Telemetering and Energy Metering Systems Benefits Supports Header and Blanking Periods of Protocols Common in RKE and TPM Systems (Up to 52 ms in ASK Mode) All RF Relevant Functions are Integrated. The Single-ended RF Input is Suited for Easy Adaptation to λ / 4 or Printed-loop Antennas Allows a Low-cost Application With Only 8 Passive Components Suitable for use in a Receiver for Joint RKE and TPMS Optimal Bandwidth Maximizes Sensitivity while Maintaining SAW Transmitter Compatibility Clock Output Provides an External Microcontroller Crystal-precision Time Reference Well Suited for Use With PLL Transmitter ATA5756/ATA5757 UHF ASK/FSK Receiver ATA5745 ATA5746 Preliminary 4596B–RKE–06/07
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 1. General Description The ATA5745/ATA5746 is a UHF ASK/FSK transparent receiver IC with low power consumption supplied in a small QFN24 package (body 5 mm × 5 mm, pitch 0.65 mm). ATA5745 is used in the 433 MHz to 435 MHz band of operation, and ATA5746 in 313 MHz to 317 MHz. The IC com- bines the functionality of remo te keyless entry (RKE - typica lly low bit rate ASK) and tire pressure monitoring (TPM - typically high bit rate FSK) into one receiver under the control of an external microcontroller such as an ATmega48 (AVR®). For improved image rejection and selectivity, the IF frequency is fixed to 440 kHz. The IF block uses an 8th-order band pass yielding a receive bandwidth of 420 kHz. This enables the use of the receiver in both SAW- and PLL-based transmitter systems utilizing various types of data-bit encoding such as pulse width modulation, Manchester modulati on, variable pulse modulation, pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq ® are easily supported due to the receiver’s ability to hold the current data slicer threshold for up to 52 ms when incoming RF telegrams contain a blanking interval. This feature eliminates erroneous noise from appearing on the demodulated data output pin, and simplifies software decoding algorithms. The decoding of the data stream must be carried out by a connected microcontroller device. Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching. ATA5745 and ATA5746 support Manchester bit rates of 1 Kbit/s to 10 Kbits/s in ASK and 1 Kbit/s to 20 Kbits/s in FSK mode. The four discrete bit rate passbands are selectable and cover 10.0 Kbits/s or 20.0 Kbits/s (for ASK or FSK, respectively). The receiver contains an RSSI output to provide an indication of received signal strength and a SENSE input to allow the customer to select a threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are selected by the connected microcontroller device via pins ASK_NFSK, BR0, and BR1. Figure 1-1. System Block Diagram (LNA, Mixer, VCO, PLL, IF Filter, RSSI Amp., Demodulator) RF Receiver ATA5745/ATA5746 Antenna XTO Microcontroller Microcontroller Interface 4 ... 8 Power Supply Digital Control Logic
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Figure 1-2. Pinning QFN24 Table 1-1. Pin Description Pin Symbol Function
1 TEST2 Test pin, during operation at GND
2 TEST1 Test pin, during operation at GND
3 CLK_OUT Output to clock a connected microcontroller
4 CLK_OUT_CTRL1 Input to control CLK_OUT (MSB)
5 CLK_OUT_CTRL0 Input to control CLK_OUT (LSB)
6 ENABLE Input to enable the XTO
7 XTAL2 Reference crystal
8 XTAL1 Reference crystal
9 DVCC Digital voltage supply blocking
10 VS5V Power supply input for voltage range 4.5V to 5.5V 11 VS3V_AVCC Power supply input for voltage range 2.7V to 3.3V
12 GND Ground
13 LNA_GND RF ground
14 LNA_IN RF input
15 SENSE Sensitivity control resistor
16 SENSE_CTRL Sensitivity selection
Low: Normal sensitivity, High: Reduced sensitivity
17 RSSI Output of the RSSI amplifier
18 TEST3 Test pin, during operation at GND
19 RX Input to activate the receiver
20 BR0 Bit rate selection, LSB
21 BR1 Bit rate selection, MSB
22 ASK_NFSK FSK/ASK selection
Low: FSK, High: ASK
23 CDEM Capacitor to adjust the lower cut-off frequency data filter
24 DATA_OUT Data output
GND Ground/backplane (exposed die pad) TEST3 DATA_OUT BR1 RX BR0 ASK_NFSK CDEM XTAL2 VS5V GND VS3V_AVCC DVCC XTAL1 RSSI LNA_IN LNA_GND SENSE SENSE_CTRL TEST2 789 1 0 1 1 1 2 23 22 TEST1 CLK_OUT_CTRL0 ENABLE CLK_OUT_CTRL1 CLK_OUT 21 20 19
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Figure 1-3. Block Diagram LPF FSK ASK VS3V_AVCC VS5V SENSE_CTRL SENSE GND DVCC LNA_IN LNA_GND CDEM ASK_NFSK BR0 BR1 RX CLK_OUT_CTRL1 TEST1 TEST3 TEST2 ENABLE RSSI CLK_OUT CLK_OUT_CTRL0 DATA_OUT Standby Logic Control XTO Div. by 3, 6, 12 LPF XTAL2 XTAL1 XTO LNA VCO PLL (/24, /32) IF Amp IF Amp ASK/FSK Demo- dulator Power Supply Data Slicer ASK/FSK Control IF Filter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 2. RF Receiver As seen in Figure 1-3 on page 4, the RF receiver consists of a low-noise amplifier (LNA), a local oscillator, and the signal processing part with mixe r, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter, and data slicer. In receive mode, the LNA pre-amplifies the received signal which is converted down to a 440-kHz intermediate frequency (IF), then filtered and amplified before it is fed into an FSK/ASK demodulator, data filter, and data slicer. The rece ived signal strength indicator (RSSI) signal is available at the pin RSSI.
2.1 Low-IF Receiver
The receive path consists of a fully integrated low- IF receiver. It fulfills the sensitivity, blocking, selectivity, supply voltage, and supply current specification needed to design an automotive inte- grated receiver for RKE and TPM systems. A benefit of the integrated receive filter is that no external components needed. At 315 MHz, the ATA5745 receiver (433.92 MHz for the ATA5746 receiver) has a typical system noise figure of 6.0 dB (7.0 dB), a system I1 dBCP of –31 dBm (–30 dBm), and a system IIP3 of –24 dBm (–23 dBm). The signal path is linear for out-of-band disturbers up to the I1dBCP and hence there is no AGC or switching of the LNA needed, and a better blocking performance is achieved. This receiver uses an IF (intermediate frequency) of 440 kHz, the typical image rejec- tion is 30 dB and the typical 3-dB IF filter bandwidth is 420 kHz (f IF = 440 kHz ± 210 kHz, flo_IF = 230 kHz and fhi_IF = 650 kHz). The demodulator needs a signal-to-noise ratio of 8.5 dB for
10 Kbits/s Manchester with ±38 kHz frequency deviation in FSK mode, thus, the resulting sensi-
tivity at 315 MHz (433.92 MHz) is typically –105 dBm (–104 dBm). Due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated IF filter, the receiver has a better selectivity and blocking performance than more complex double superhet receivers, without using external components and without numerous spurious receiv- ing frequencies. A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct conversion receivers where every pulse or ampl itude modulated signal (especially the signals from TDMA systems like GSM) demodulates to the receiving signal band at second-order non-linearities.
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary]
2.2 Input Matching at LNA_IN
The measured input impedances as well as the val ues of a parallel equivalent circuit of these impedances can be seen in Table 2-1. The highest sensitivity is achieved with power matching of these impedances to the source impedance. The matching of the LNA input to 50 Ω is done using the circuit shown in Figure 2-1 and the val- ues of the matching elements given in Table 2-2 . The reflection coefficients were always ≤ –10 dB. Note that value changes of C1 and L1 may be necessary to compensate individual board layout parasitics. The measured typical FSK and ASK Manchester-code sensitivities with a bit error rate (BER) of 10–3 are shown in Table 2-3 and Table 2-4 on page 7. These measure- ments were done with wire-wound inductors having quality factors reported in Table 2-2 , resulting in estimated matching losses of 0.8 dB at 315 MHz and 433.92 MHz. These losses can be estimated when calculating the parallel equivalent resistance of the inductor with R loss =2 ×π × f × L × QL and the matching loss with 10 log(1+RIn_p /R loss). Figure 2-1. Input Matching to 50Ω Table 2-1. Measured Input Impedances of the LNA_IN Pin fRF [MHz] Z In(RF_IN) [Ω]R In_p//CIn_p [pF] 315 (72.4 – j298) 1300 Ω//1.60 433.92 (55 – j216) 900 Ω//1.60 Table 2-2. Input Matching to 50Ω fRF [MHz] C 1 [pF] L 1 [nH] Q L1 315 2.2 68 20 433.92 2.2 36 15 RFIN LNA_IN ATA5745/ATA5746
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Conditions for the sensitivity measurement: The given sensitivity values are valid for Manchester-modulated signals. For the sensitivity mea- surement the distance from edge to edge must be evaluated. As can be seen in Figure 6-1 on page 24, in a Manchester-modulated data stream, the time segments TEE and 2 × TEE occur. To reach the specified sensit ivity for the evaluation of T EE and 2 × TEE in the data stream, the following limits should be used (TEE min, TEE max, 2 × TEE min, 2 × TEE max).
2.3 Sensitivity Versus Supply Voltag e, Temperature and Frequency Offset
To calculate the behavior of a transmission system, it is important to know the reduction of the sensitivity due to several influences. The most important are frequency offset due to crystal oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage depen- dency of the noise figure, and IF-filter bandwidth of the receiver. Figure 2-2 and Figure 2-3 on page 8 show the typical sensitivity at 315 MHz, ASK, 2.4 Kbits/s and 9.6 Kbits/s, Manchester, Figure 2-4 and Figure 2-5 on page 9 show a typical sensitivity at 315 MHz, FSK, 2.4 Kbits/s and
9.6 Kbits/s, ±38 kHz, Manchester versus the frequency offset between transmitter and receiver
amb = –40°C, +25°C, and +105°C and supply voltage VS = VS3V_AVCC = VS5V = 2.7V, 3.0V and 3.3V. Table 2-3. Measured Typical Sensitivity FSK, ±38 kHz, Manchester, BER = 10–3 RF Frequency BR_Range_0
1.0 Kbit/s
BR_Range_0
2.5 Kbits/s
BR_Range_1
5 Kbits/s
BR_Range_2
10 Kbits/s
BR_Range_3 BR_Range_3
20 Kbits/s
315 MHz –108 dBm –108 dBm –107 dBm –105 dBm –104 dBm –104 dBm
433.92 MHz –107 dBm –107 dBm –106 dBm –104 dBm –103 dBm –103 dBm
Table 2-4. Measured Typical Sensitivity 100% ASK, Manchester, BER = 10–3 RF Frequency BR_Range_0 BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3
315 MHz –114 dBm –114 dBm –113 dBm –111 dBm –109 dBm
433.92 MHz –113 dBm –113 dBm –112 dBm –110 dBm –108 dBm
Table 2-5. Limits for Sensitivity Measurements Bit Rate T EE Min T EE Typ T EE Max 2 × TEE Min 2 × TEE Typ 2 × TEE Max
1.0 Kbit/s 260 µs 500 µs 790 µs 800 µs 1000 µs 1340 µs
2.4 Kbits/s 110 µs 208 µs 310 µs 320 µs 416 µs 525 µs
5.0 Kbits/s 55 µs 100 µs 155 µs 160 µs 200 µs 260 µs
9.6 Kbits/s 27 µs 52 µs 78 µs 81 µs 104 µs 131 µs
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] As can be seen in Figure 2-5 on page 9 , the supply voltage has almost no influence. The tem- perature has an influence of about ±1.0 dB, and a frequency offset of ±160 kHz also influences by about ±1 dB. All these influences, combined with the sensitivity of a typical IC (–105 dB), are then within a range of –103.0 dBm and –107.0 dBm over temperature, supply voltage, and fre- quency offset. The integrated IF filter has an additional production tolerance of ±10 kHz, hence, a frequency offset between the receiver and the transmitter of ±160 kHz can be accepted for XTAL and XTO tolerances. Note: For the demodulator used in the ATA5745/AT A5746, the tolerable frequency offset does not change with the data frequency. Hence, the value of ±160 kHz is valid for 1 Kbit/s to 10 Kbits/s. This small sensitivity change over supply voltage, frequency offset, and temperature is very unusual in such a receiver. It is achieved by an internal, very fast, and automatic frequency cor- rection in the FSK demodulator after the IF filter, which leads to a higher system margin. This frequency correction tracks the input frequency ve ry quickly. If, however, the input frequency makes a larger step (for example, if the system changes between different communication part- ners), the receiver has to be restarted. This can be done by switching back to Standby mode and then again to Active mode (pin RX 1 → 0 → 1) or by generating a positive pulse on pin ASK_NFSK (0 →1 → 0).
2.4 Frequency Accuracy of the Crystals in a Combined RKE and TPM System
In a tire pressure measurement system working at 315 MHz and using an ATA5756 as transmit- ter and an ATA5746 is receiver, the higher frequency tolerances and the tolerance of the frequency deviation of the transmitter has to be considered. In the TPM transmitter, the crystal has a frequency error over temperature –40°C to 125°C, aging, and tolerance of ±80 ppm (±25.2 kHz at 315 MHz). The tolerances of the XTO, the capacitors used for FSK modulation, and the stray capacitances cause an additional frequency error of ±30 ppm (±9.45 kHz at 315 MHz). The frequency deviation of such a transmitter varies between ±16 kHz and ±24 kHz, since a higher frequen cy deviation is equivalent to a frequency error this has to be considered as an additional ±24 kHz – ±19.5 kHz = ±4.5kHz frequency toler- ance (19.5 kHz is constant). All tolerances added, these transmitters have a worst-case frequency offset of ±39.15 kHz. For the receiver in the car, a tolerance of ±160 kHz – ±39.15 kHz = ±120.85 kHz (±383.6 ppm) remains. The needed frequency stability of the crystals over temperature and aging is ±383.6 ppm – ±5 ppm = ±378.6 ppm. The aging of such a crystal is ±10 ppm, leaving a reason- able ±368.6 ppm for the temperature dependency of the crystal frequency in the car. Since the receiver in the car is able to receive these TPM transmitter signals with high frequency offsets, the component specification in the key can be largely relaxed. This system calculation is based on worst-case tolerances of all the components; this leads in practice to a system with margin. For a 433.92 MHz TPM system using ATA5757 as transmitter and ATA5745 as receiver, the same calculation must be done, but since the RF frequency is higher, every ppm of crystal toler- ances results in higher frequency offset and either the system must have lower tolerances or a lower margin at this frequency.
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary]
2.5 RX Supply Current Versus Te mperature and Supply Voltage
Table 2-7 shows the typical supply curr ent of the receiver in Active mode versus supply voltage and temperature with VS = VS3V_AVCC = VS5V.
2.6 Blocking, Selectivity
As can be seen in Figure 2-6 on page 11 , and Figure 2-7 and Figure 2-8 on page 12 , the receiver can receive signals 3 dB higher than the sensitivity level in the presence of large block- ers of –34.5 dBm or –28 dBm with small frequency offsets of ±3 MHz or ±20 MHz. Figure 2-6, and Figure 2-7 on page 12 show the narrow-band blocking, and Figure 2-8 on page 12 shows the wide-band blocking characteristic. The measurements were done with a useful signal of 315 MHz, FSK, 10 Kbits/s, ±38 kHz, Manchester, BR_Range2 with a level of –105 dBm + 3 dB = –102 dBm, which is 3 dB above the sensitivity level. The figures show how much larger than –102 dBm a continuous wave signal can be, until the BER is higher than 10 –3. The measurements were done at the 50 Ω input shown in Figure 2-1 on page 6 . At 3 MHz, for example, the blocker can be 67.5 dBC higher than –102 dBm, or –102 dBm + 67.5 dBC = –34.5 dBm. Figure 2-6. Close-in 3-dB Blocking Characteristic and Image Response at 315 MHz Table 2-6. Measured Current in Active Mode ASK VS = VS3V_AVCC = VS5V 2.7V 3.0V 3.3V Tamb = –40°C 5.4 mA 5.5 mA 5.6 mA Tamb = 25°C 6.4 mA 6.5 mA 6.6 mA Tamb = 105°C 7.4 mA 7.5 mA 7.6 mA Table 2-7. Measured Current in Active Mode FSK VS = VS3V_AVCC = VS5V 2.7V 3.0V 3.3V Tamb = –40°C 5.6 mA 5.7 mA 5.8 mA Tamb = 25°C 6.6 mA 6.7 mA 6.8 mA Tamb = 105°C 7.6 mA 7.7 mA 7.8 mA -1 0.0 0.0 10 . 0 20.0 30.0 40.0 50.0 60.0 70.0 Distance from Interfering to Receiving Signal (MHz) Blocking Level (dBC)
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] The ATA5745/ATA5746 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals at –10 dBm. This is often referred to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is 95 dB for 10 Kbits/s Manchester (FSK). This value is useful if the transmitter and receiver are very close to each other.
2.7 In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer
If a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the performance of a receiver strongly depends on the circuits after the IF filter. Hence, the demod- ulator, data filter, and data slicer are important. The data filter of the ATA5745/ATA5746 functions also as a quasi-peak detector. This results in a good suppression of above mentioned disturbers and exhibits a good carrier-to-noise perfor- mance. The required useful-signal-to-disturbing-signal ratio, at a BER of 10–3, is less than 14 dB in ASK mode and less than 3 dB (BR_Range_0 to BR_Range_2) and 6 dB (BR_Range_3) in FSK mode. Due to the many different possible waveforms, these numbers are measured for the signal, as well as for disturbers, with peak amplitude values. Note that these values are worst-case values and are valid for any type of modulation and modulating frequency of the dis- turbing signal, as well as for the receiving signal. For many combinations, lower carrier-to-disturbing-signal ratios are needed.
2.8 RSSI Output
The output voltage of the pin RSSI is an analog voltage, proportional to the input power level. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable dynamic range of the RSSI amplifier is 65 dB, the input power range P(RFIN) is –110 dBm to –45 dBm, and the gain is 15 mV/dB. Figure 2-9 shows the RSSI characteristic of a typical device at 315 MHz with VS3V_AVCC = VS5V = 2.7V to 3.3V and T amb = –40°C to +105°C with a matched input as shown in Table 2-2 and Figure 2-1 on page 6 . At 433.92 MHz, 1 dB more signal level is needed for the same RSSI results. Figure 2-9. Typical RSSI Characteristic at 315 MHz Versus Temperature and Supply Voltage 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Pin (dBm) V_RSSI (V) max; +9dB 2.7V, -40˚C 3.0V, -40˚C 3.3V, -40˚C 2.7V, 27˚C 3.0V, 27˚C 3.3V, 27˚C 2.7V, 105˚C 3.0V, 105˚C 3.3V, 105˚C min; -9dB
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] As can be seen in Figure 2-9 on page 13, for single devices there is a variance over temperature and supply voltage range of ±3 dB. The total variance over production, temperature, and supply voltage range is ±9 dB.
2.9 Frequency Synthesizer
The LO generates the carrier frequency for the mixer via a PLL synthesi zer. The XTO (crystal oscillator) generates the reference frequency f XTO. The VCO (voltage-controlled oscillator) gen- erates the drive voltage frequency fLO for the mixer. fLO is divided by the factor 24 (ATA5746) or 32 (ATA5745). The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to the fully integrated loop filter, and thereby generates the control voltage for the VCO. By means of that configuration, the VCO is controlled in a way, such that f LO /2 4 ( fLO / 32) is equal to f XTO. If fLO is determined, fXTO can be calculated using the following formula: f XTO =f LO / 24 (f XTO =f LO / 32). The synthesizer has a phase noise of –130 dBC/Hz at 3 MHz and spurs of –75 dBC. Care must be taken with the harmonics of the CLK output signal, as well as with the harmonics produced by a microprocessor clocked using the signal, as these harmonics can disturb the reception of signals. 3. XTO The XTO is an amplitude-regulated Pierce osci llator type with external load capacitances (2 × 16 pF). Due to additional internal and board parasitics (C P) of approximately 2 pF on each side, the load capacitance amounts to 2 × 18 pF (9 pF total). The XTO oscillati on frequency f XTO is the reference frequency for the integer-N synthesizer. When designing the system in terms of receiving and transmitting frequency offset, the accuracy of the crystal and XTO have to be considered. The XTO’s additional pulling (including the RM tolerance) is only ±5 ppm. The XTAL versus tem- perature, aging, and tolerances is then the main source of frequency error in the local oscillator. The XTO frequency depends on XTAL properties and the load capacitances C L1,2 at pin XTAL1 and XTAL2. The pulling (p) of f XTO from the nominal f XTAL is calculated using the following for- mula: Cm, the crystal's motional capacitance; C 0, the shunt capacitance; and C LN, the nominal load capacitance of the XTAL, are found in the datasheet. C L is the total actual load capacitance of the crystal in the circuit, and consists of CL1 and CL2 connected in series. p Cm
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Figure 3-1. Crystal Equivalent Circuit With C m ≤10 fF, C 0 ≥ 1.0 pF, C LN = 9 pF and C L1,2 = 16 pF ±1%, the pulling amounts to P ≤±1 ppm. The C0 of the XTAL has to be lower than CLmin / 2 = 7.9 pF for a Pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is risk of an unstable oscillation. To ensure proper start-up behavior, the small si gnal gain and the negative resistance provided by this XTO at start is very large. For example, oscillation starts up even in the worst case with a crystal series resistance of 1.5 k Ω at C 0 ≤2.2 pF with this XTO. The negative resistance is approximately given by with Z1 and Z2 as complex impedances at pins XTAL1 and XTAL2, hence Z1 =– j/( 2 × p × fXTO × CL1)+5 Ω and Z2 =– j/( 2 × p × fXTO × CL2)+5 Ω. Z3 consists of crystal C0 in parallel with an internal 110-kΩ resistor, hence Z3 =– j/( 2 × p × fXTO × C0)/1 1 0k Ω, gm is the internal transconductance between XTAL1 and XTAL2, with typically 20 mS at 25°C. With fXTO = 13.5 MHz, gm = 20 mS, C L = 9 pF, and C0 = 2.2 pF, this results in a negative resis- tance of about 2 kΩ. The worst case for technology, supply voltage, and temperature variations is then always higher than 1.4 kΩ for C0 ≤2.2 pF. Due to the large gain at start, the XTO is able to meet a very low start- up time. The oscillation start-up time can be estimated with the time constant τ . After 10τ to 20τ, an amplitude detector detects the oscillation amplitude and sets XTO_OK to High if the amplitude is large enough; this activates the CLK_OUT output if it is enabled via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the DVCC voltage also have to be fulfilled. It is recommended to use a crystal with C m = 3.0 fF to 10 fF, C LN =9p F , Rm <1 2 0Ω and C0 = 1.0 pF to 2.2 pF. CL2CL1 Cm Lm Rm CL = CL1 × CL2/ (CL1 + CL2) XTAL Crystal Equivalent Circuit Re Zxtocore{} Re Z1 Z3 Z2 Z3 Z1 Z3 gm××+×+× ⎧⎫= τ 2 4 π2 fXTAL
2 Cm Re Z xtocore() Rm+()××××
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Lower values of C m can be used, slightly increasing the start-up time. Lower values of C 0 or higher values of Cm (up to 15 fF) can also be used, with only little influence on pulling. Figure 3-2. XTO Block Diagram The relationship between fXTO and the fRF is shown in Table 3-1. Attention must be paid to the harmonics of the CLK_OUT output signal fCLK_OUT as well as to the harmonics produced by an microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the RF input. If the CLK_OUT signal is used, it must be carefully laid out on the application PCB. The supply voltage of the microcontroller must also be carefully blocked. Table 3-1. Calculation of f RF Frequency [MHz] f XTO [MHz] f RF 433.92 (ATA5745) 13.57375 f XTO x 32 – 440 kHz 315.0 (ATA5746) 13.1433 f XTO x 24 – 440 kHz CL2CL1 fDCLK fFXTO CLK_OUT_CTRL1CLK_OUT_CTRL0 XTO_OK XTAL1 XTAL2 CLK_OUT Amplitude Detector Divider /16 Divider /3, /6, /12
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary]
3.1 Pin CLK_OUT
Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in Standby and Active modes. The frequency f CLK_OUT can be adjusted via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows: The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recom- mended that CLK_OUT be switched off during Standby mode.
3.2 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry is derived from one clock. As seen in Figure 3-2 on page 16, this clock cycle, TDCLK, is derived from the crystal oscillator (XTO) in combination with a divider. TDCLK controls the following application relevant parameters: - Debouncing of the data signal stream - Start-up time of the RX signal path The start-up time and the debounce characteristic depend on the selected bit rate range (BR_Range) which is defined by pins BR0 and BR1. The clock cycle T XDCLK is defined by the fol- lowing formulas for further reference: BR_Range ⇒ BR_Range 0: TXDCLK = 8 × TDCLK BR_Range 1: TXDCLK = 4 × TDCLK BR_Range 2: TXDCLK = 2 × TDCLK BR_Range 3: TXDCLK = 1 × TDCLK Table 3-2. Setting of fCLK_OUT CLK_OUT_CTRL1 CLK_OUT_CTRL0 Function
00 Clock on pin CLK_OUT is switched off
(Low level on pin CLK_OUT) 01 f CLK_OUT =f XTO /3 10 f CLK_OUT =f XTO /6 11 f CLK_OUT =f XTO /1 2 fDCLK fXTO
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 4. Sensitivity Reduction The output voltage of the RSSI amplifier is internally compared to a threshold voltage V Th_red. VTh_red is determined by the value of the external resistor R Sense. RSense is connected between the pins SENSE and VS3V_AVCC (see Figure 10-1 on page 28). The output of the comparator is fed into the digital control logic. By this means , it is possible to operate the receiver at a lower sensitivity. If the level on input pin SENSE_CTRL is low, the receiver operates at full sensitivity. If the level on input pin SENSE_CTRL is high, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of R Sense , the maximum sensitivity by the sig- nal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slig htly different values for the LNA gain, the sen- sitivity values given in the electrical characte ristics refer to a specific input matching. This matching is illustrated in Figure 2-1 on page 6 and exhibits the best possible sensitivity. If the sensitivity reduction feature is not used, pin SENSE can be left open, pin SENSE_CTRL must be set to GND. To operate with reduced sensitivity, pin SENSE_CTRL must be set to high before the RX signal path will be enabled by setting pin RX to high (see Figure 4-1 on page 19). As long as the RSSI level is lower than VTh_red (defined by the external resistor RSense) no data stream is available on pin DATA_OUT (low level on pin DATA_OUT). An internal RS flip-flop will be set to high the first time the RSSI voltage crosses VTh_red, and from then on the data stream will be available on pin DATA_OUT. From then on the receiver also works wit h full sensitivity. Th is makes sure that a telegram will not be interrupted if the RSSI level varies during th e transmission. The RS flip-flop can be set back, and thus the receiver switched back to reduced sensitivity, by generating a pos- itive pulse on pin ASK_NFSK (see Figure 4-2 on page 19). In FSK mode, operating with reduced sensitivity follows the same way.
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 5. Power Supply Figure 5-1. Power Supply Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery applications using a single lithiu m 3V cell. Pin VS5V is the voltage input for the range 4.5V to 5.5V (car applications) in this case the volt age regulator V_REG regulates VS3V_AVCC to typi- cally 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2 µF has to be connected to VS3V_AVCC (see Figure 10-1 on page 28). DVCC is the internal operating voltage of the digital control logic and is fed via the switch SW_DVCC by VS3V_AVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 9-1 on page 27 and Figure 10-1 on page 28). Pin RX is the input to activate the RX signal processing and set the receiver to Active mode.
5.1 OFF Mode
A low level on pin RX and ENABLE will set the rece iver to OFF mode (low power mode). In this mode, the crystal oscillator is shut down and no clock is available on pin CLK_OUT. The receiver is not sensitive to a transmitter signal in this mode.
5.2 Standby Mode
The receiver activates the Standby mode if pin ENABLE is set to “1”. In Standby mode, the XTO is running and the clock on pin CLK_OUT is available after the start-up time of the XTO has elapsed (dependent on pin CLK_OUT_CTRL0 and CLK_OUT_CTRL1). During Standby mode, the receiver is not sensitive to a transmitter signal. In Standby mode, the RX signal path is disabled and the power consumption I Standby is typically 50 µA (CLK_OUT output off, VS3V_AVCC = VS5V = 3V). The exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the sec- tion “Electrical Characteristics: General” on page 29 for the appropriate application case. V_REG 3.0V typ. SW_DVCC OUT RX DVCCVS5V VS3V_AVCC IN EN Table 5-1. Standby Mode RX ENABLE Function
00 O F F m o d e
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Figure 5-2. Standby Mode (CLK_OUT_CTRL0 or CLK_OUT_CTRL1 = 1)
5.3 Active Mode
The Active mode is enabled by setting the level on pin RX to high. In Active mode, the RX signal path is enabled and if a valid signal is present it will be transferred to the connected microcontroller. During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing circuit starts up (T Startup_Sig_Proc ). After the start-up time, all circuits are in stable condition and ready to receive. The duration of the start-up sequence depends on the selected bit rate range. Figure 5-3. Active Mode Table 5-2. Standby Mode RX ENABLE Function 0 1 Standby mode CLK_OUT ENABLE Standby Mode tXTO_Startup Table 5-3. Active Mode RX ENABLE Function 1 1 Active mode DATA_OUT valid tStartup_PLL tStartup_Sig_Proc IStartup_PLL IActive IActiveIStandby Startup CLK_OUT RX DATA_OUT ENABLE Standby Mode Active Mode
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Table 5-4. Start-up Time BR1 BR0 ATA5745 (433.92 MHz) ATA5746 (315 MHz) TStartup_PLL TStartup_Sig_Proc TStartup_PLL TStartup_Sig_Proc 261 µs 1096 µs 269 µs 1132 µs 0 1 644 µs 665 µs 1 0 417 µs 431 µs 1 1 304 µs 324 µs Table 5-5. Modulation Scheme ASK_NFSK RF IN at Pin LNA_IN Level at Pin DATA_OUT fFSK_H 1 fFSK_L 0 fASK on 1 fASK off 0
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 6. Bit Rate Ranges Configuration of the bit rate ranges is carried out via the two pins BR0 and BR1. The microcon- troller uses these two interface lines to set th e corner frequencies of the band-pass data filter. Switching the bit rate ranges while the RF front end is in Active mode can be done on the fly and will not take longer than 100 µs if done while remaining in either ASK or FSK mode. If the modu- lation scheme is changed at the same time, the switching time is (T Startup_Sig_Proc, see Figure 7-1 on page 25). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sen- sitivity of the receiver, edge-to-edge transition times of incoming data should not be less than the minimum for the selected BR_Range. Table 6-1. BR Ranges ASK BR1 BR0 BR_Range Recommended Bit Rate (Manchester)(1) Minimum Edge-to-edge Time Period TEE of the Data Signal(2) Edge-to-edge Time Period TEE of the Data Signal During the Start-up Period(3) 0 0 BR_Range0 1.0 Kbit/s to 2.5 Kbits/s 200 µs 200 µs to 500 µs 0 1 BR_Range1 2.0 Kbits/s to 5.0 Kbits/s 100 µs 100 µs to 250 µs 1 0 BR_Range2 4.0 Kbits/s to 10.0 Kbits/s 50 µs 50 µs to 125 µs 1 1 BR_Range3 8.0 Kbits/s to 10.0 Kbits/s 50 µs 50 µs to 62.5 µs Table 6-2. BR Ranges FSK BR1 BR0 BR_Range Recommended Bit Rate (Manchester)(1) Minimum Edge-to-edge Time Period TEE of the Data Signal(2) Edge-to-edge Time Period TEE of the Data Signal During the Start-up Period(3) 0 0 BR_Range0 1.0 Kbit/s to 2.5 Kbits/s 200 µs 200 µs to 500 µs 0 1 BR_Range1 2.0 Kbits/s to 5.0 Kbits/s 100 µs 100 µs to 250 µs 1 0 BR_Range2 4.0 Kbits/s to 10.0 Kbits/s 50 µs 50 µs to 125 µs 1 1 BR_Range3 8.0 Kbits/s to 20.0 Kbits/s 25 µs 25 µs to 62.5 µs Note: If during the start-up period (T Startup_PLL +T Startup_Sig_Proc) there is no RF signal, the data filter settles to the noise floor, leading to noise on pin DATA_OUT. Notes: 1. As can be seen, a bit stream of, for example, 2.5 Kb its/s can be received in BR_Range0 and BR_Range1 (overlapping BR_Ranges). To get the full sensitivity, always use the lowest possible BR_Range (here, BR_Range0). The advantage in the next higher BR_Range (BR_Range1) is the shorter start-up period, meaning lower current consumption during Polling mode. Thus, it is a decision between sensitivity and current consumption. 2. The receiver is also capable of re ceiving non-Manchester-modulated signals, such as PWM, PPM, VPWM, NRZ. In ASK mode, the header and blanking periods occurring in Keeloq-like protocols (up to 52 ms) are supported. 3. To ensure an accurate settling of th e data filter during the start-up period (TStartup_PLL + TStartup_Sig_Proc), the edge-to-edge time TEE of the data signal (preamble) must be inside the given limits during this period.
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 7. ASK_NFSK The ASK_NFSK pin allows the microcontroller to rapidly switch the RF front end between demodulation modes. A logic 1 on this pin selects ASK mode, and a logic 0 FSK mode. The time to change modes (T Startup_Sig_Proc) depends on the bit rate range being selected (not current bit rate range) and is given in Table 5-4 on page 22. This response time is specified for applications that require an ASK preamble followed by FSK data (for typical TPM applications). During TStartup_Sig_Proc, the level on pin DATA_OUT is low. Figure 7-1. ASK Preamble 2.4 Kbits/s followed by FSK Data 9.6 Kbits/s RX ASK_NFSK DATA_OUT Data valid BR3Data valid BR0 BR0 BR1 ENABLE TStartup_Sig_Proc
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 8. Polling Current Calculation Figure 8-1. Polling Cycle In an RKE and TPM system, the averag e chip current in Polling mode, I Polling, is an important parameter. The polling period must be controlled by the connected microcontroller via the pins ENABLE and RX. The polling current can be calculated as follows: IPolling =( TStartup_PLL /T Polling_Period ) × IStartup_PLL +( TStartup_Sig_Proc /T Polling_Period ) × IActive + (TBitcheck /T Polling_Period ) × IActive +( T Polling_Period –T Startup_PLL –T Startup_Sig_Proc –T Bitcheck )/ TPolling_Period × IStandby TStartup_PLL: depends on 315 MHz/433.92 MHz application. TStartup_Sig_Proc: depends on 315 MHz/433.92 MHz application and the selected bit rate range. TBitcheck: depends on the signal bit rate (1 / Signal_Bit_Rate). TPolling_Period: depends on the transmitter telegram (preburst). IStartup_PLL: depends on 3V or 5V application and the setting of pin CLK_OUT. IActive: depends on 3V or 5V application, ASK or FSK mode and the setting of pin CLK_OUT. IStandby: depends on 3V or 5V application and the setting of pin CLK_OUT. Example:- 315-MHz application (ATA5746), bit rate: 9.6 Kbits/s, T Polling_Period =8m s --> TStartup_PLL = 269 µs --> TStartup_Sig_Proc = 324 µs (Bit Rate Range 3) --> TBitcheck = 104 µs 3V application; ASK mode, CLK_OUT disabled --> IStartup_PLL =4 . 5 m A --> IActive =6 . 5 m A --> IStandby =0 . 0 5 m A --> IPolling = 0.545 mA IStandby IStandby IActive IStartup_PLL IActive IStartup_PLL RX ISupply ENABLE TBitcheck (= 1 / Signal_Bitrate (average) TStartup_PLL (Startup RF-PLL) TStartup_Sig_Proc (Startup Signal Processing)
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 9. 3V Application Figure 9-1. 3V Application Note: Paddle (backplane) must be connected to GND TEST2 TEST1 ENABLE CLK_OUT VS5V GND VS3V_AVCC DVCC XTAL1 XTAL2 BR1 RX BR0 ASK_NFSK CDEM DATA_OUT CLK_OUT_CTRL0 CLK_OUT_CTRL1 output output output output input output VCCVSS TEST3 LNA_IN LNA_GND SENSE SENSE_CTRL RSSI RFIN 18 pF Microcontroller ATA5745/ ATA5746 18 pF 68 nF 15 nF 2.2 pF 68 nH/36 nH 315 MHz/433.92 MH z 68 nF VCC = 2.7V to 3.3V
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 10. 5V Application Figure 10-1. 5V Application With Reduced/Full Sensitivity Note: Paddle (backplane) must be connected to GND TEST2 TEST1 ENABLE CLK_OUT VS5V GND VS3V_AVCC DVCC XTAL1 XTAL2 BR1 RX BR0 ASK_NFSK CDEM DATA_OUT CLK_OUT_CTRL0 CLK_OUT_CTRL1 output output output output output input output VCCVSS TEST3 LNA_IN LNA_GND SENSE SENSE_CTRL RSSI RFIN RSense 18 pF Microcontroller ATA5745/ ATA5746 18 pF 68 nF 15 nF 2.2 pF 2.2 µF 68 nH/36 nH 315 MHz/433.92 MHz 68 nF VCC = 4.5V to 5.5V
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 11. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Junction temperature T j +150 °C Storage temperature T stg –55 +125 °C Ambient temperature T amb –40 +105 °C Supply voltage VS5V V S +6 V ESD (Human Body Model ESD S 5.1) every pin HBM –4 +4 kV ESD (Machine Model JEDEC A115A) every pin MM –200 +200 V ESD (Field Induced Charge Device Model ESD STM 5.3.1-1999) every pin FCDM –500 +500 V Maximum input level, input matched to 50Ω Pin_max 0d B m 12. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 25 K/W 13. Electrical Charac teristics: General Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type*
1 OFF Mode
1.1 Supply current in OFF
VVS3V_AVCC =V VS5V ≤ 3V VVS5V =5 V CLK_OUT disabled 10, 11
10 I SOFF
µA µA A A
2 Standby Mode
2.1 RF operating frequency
ATA5745 14 f RF 433 435 MHz A
2.2 Supply current
VVS3V_AVCC =V VS5V ≤ 3V CLK_OUT disabled 10,11 I Standby 50 80 µA A XTO running VVS5V =5 V CLK_OUT disabled 10,11 I Standby 50 80 µA A
2.3 System start-up time
XTAL: Cm = 5 fF , C0 = 1.8 pF , Rm = 15Ω TXTO_Startup 0.3 0.8 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN).
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary]
2.4 Active mode start-up time
BR_Range_3 ATA5745 ATA5746 T Startup_PLL + TStartup_Sig_Proc 565 593 µs µs A
3 Active Mode
3.1 Supply current Active
V VS3V_AVCC =V VS5V =3 V ASK mode CLK_OUT disabled SENSE_CTRL = 0 10,11 I Active 6.5 9.6 mA A VVS3V_AVCC =V VS5V =3 V FSK mode CLK_OUT disabled SENSE_CTRL = 0 10,11 I Active 6.7 9.8 mA A VVS5V =5 V ASK mode CLK_OUT disabled SENSE_CTRL = 0 10 I Active 6.7 9.8 mA A VVS5V =5 V FSK mode CLK_OUT disabled SENSE_CTRL = 0 10 I Active 6.9 10 mA A
3.2 Supply current Polling
VVS3V_AVCC =V VS5V =3 V TPolling_Period = 8 ms BR_Range_3, ASK mode, CLK_OUT disabled Data rate = 9.6 Kbits/s 10,11 I Polling 545 µA C
3.3 Input sensitivity FSK
fRF = 315 MHz FSK deviation fDEV = ±38 kHz BER = 10–3 Tamb = 25°C Bit rate 9.6 Kbits/s BR2 (14) P REF_FSK –103 –105 –106.5 dBm B Bit rate 2.4 Kbits/s BR0 (14) P REF_FSK –106 –108 –109.5 dBm B FSK deviation ±18 kHz to ±50 kHz Bit rate 9.6 Kbits/s BR2 (14) P REF_FSK –101 dBm B Bit rate 2.4 Kbits/s BR0 (14) P REF_FSK –104 dBm B
3.4 Input sensitivity ASK
fRF = 315 MHz ASK 100% level of carrier, BER = 10–3 Tamb = 25°C Bit rate 9.6 Kbits/s BR2 (14) P REF_ASK –109 –111 –112.5 dBm B Bit rate 2.4 Kbits/s BR0 (14) P REF_ASK –112 –114 –115.5 dBm B 13. Electrical Characterist ics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN).
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 3.5 Sensitivity change at fRF =4 3 3 . 9 2M H z compared to f RF =3 1 5M H z fRF = 315 MHz to fRF =4 3 3 . 9 2M H z P=P REF_ASK + ∆PREF1 P=P REF_FSK + ∆PREF1 (14) ∆PREF1 +1 dB B 3.6 Sensitivity change versus temperature, supply voltage and frequency offset FSK f DEV = ±38 kHz ∆fOFFSET ≤ ± 160 kHz ASK 100% ∆fOFFSET ≤ ± 160 kHz P = PREF_ASK + ∆PREF1 + ∆PREF2 P = PREF_FSK + ∆PREF1 + ∆PREF2 3.7 Reduced sensitivity RSense connected from pin SENSE to pin VS3V_AVCC PRef_Red dBm (peak level) RSense = 62 kΩ fin = 433.92 MHz –76 dBm C RSense = 82 kΩ fin = 433.92 MHz –88 dBm C RSense = 62 kΩ fin = 315 MHz –76 dBm C RSense = 82 kΩ fin = 315 MHz –88 dBm C Reduced sensitivity variation over full operating range R Sense = 62 kΩ RSense = 82 kΩ PRed = PRef_Red + P∆Red ∆PRed –10 +10 dB
3.8 Maximum frequency
receiver and transmitter in FSK mode (f RF is the center frequency of the FSK signal with f BIT = 10 Kbits/s fDEV = ±38 kHz (14) ∆fOFFSET –160 +160 kHz B
3.9 Supported FSK
loss of sensitivity. Note that the tolerable frequency offset is 12 kHz lower for f DEV = ±50 kHz than for fDEV = ±38 kHz, hence, ∆fOFFSET ≤ ±148 kHz (14) f DEV ±18 ±38 ±50 kHz B 13. Electrical Characterist ics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN).
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary]
3.10 System noise figure
fRF = 315 MHz (14) NF 6.0 9 dB B fRF = 433.92 MHz (14) NF 7.0 10 dB B
3.11 Intermediate frequency
fRF = 433.92 MHz f IF 440 kHz A fRF = 315 MHz f IF 440 kHz A
3.12 System bandwidth
information only! Note that for crystal and system frequency offset calculations, ∆fOFFSET must be used. (14) SBW 435 kHz A 3.13 System out-band 3rd-order input intercept point ∆fmeas1 = 1.8 MHz ∆fmeas2 = 3.6 MHz fRF = 315 MHz (14) IIP3 –24 dBm C fRF = 433.92 MHz (14) IIP3 –23 dBm C
3.14 System outband input
∆fmeas1 = 1 MHz fRF = 315 MHz (14) I1dBCP –31 –36 dBm C fRF = 433.92 MHz (14) I1dBCP –30 –35 dBm C
3.15 LNA input impedance
fRF = 315 MHz 14 Z in_LNA (72.4 – j298) Ω C fRF = 433.92 MHz 14 Z in_LNA (55 – j216) Ω C
3.16 Maximum peak RF input
level, ASK and FSK BER < 10–3, ASK: 100% (14) P IN_max +5 –10 dBm C FSK: fDEV = ±38 kHz (14) P IN_max +5 –10 dBm C
3.17 LO spurs at LNA_IN
f < 1 GHz (14) –57 dBm C f >1 GHz (14) –47 dBm C f LO = 315.44 MHz 2 × fLO 4 × fLO (14) –90 –94 –68 dBm C f LO = 434.36 MHz 2 × fLO 4 × fLO (14) –92 –88 –58 dBm C
3.18 Image rejection
fRF = 315 MHz (14) 24 30 dB A fRF = 433.92 MHz (14) 24 30 dB A 13. Electrical Characterist ics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN).
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary]
3.19 Useful signal to interferer
Peak level of useful signal to peak level of interferer for BER < 10–3 with any modulation scheme of interferer FSK BR_Ranges 0, 1, 2 (14) SNR FSK0-2 23 d B B FSK BR_Range_3 (14) SNR FSK3 46 d B B ASK (PRF < PRFIN_High)( 1 4 ) S N R ASK 10 14 dB B
3.20 RSSI output
Dynamic range (14),17 D RSSI 65 dB A Lower level of range fRF = 315 MHz fRF = 433.92 MHz (14),17 P RFIN_Low –110 dBm A Upper level of range fRF = 315 MHz fRF = 433.92 MHz (14),17 P RFIN_High –45 dBm A Gain (14),17 15 mV/dB A Output voltage range (14),17 V RSSI 350 1600 mV A
3.21 Output resistance
RSSI pin 17 R RSSI 81 0 1 2 . 5 k Ω C
3.22 Blocking
Sensitivity (BER = 10–3) is reduced by 3 dB if a continuous wave blocking signal at ±∆f is ∆PBlock higher than the useful signal level (Bit rate = 10 Kbits/s, FSK, f DEV ±3 8k H z , Manchester code, BR_Range2) fRF = 315 MHz ∆f ± 1.5 MHz ∆f ± 2 MHz ∆f ± 3 MHz ∆f ± 10 MHz ∆f ± 20 MHz (14) ∆PBlock 57.5 63.0 67.5 72.0 74.0 dBC C f RF = 433.92 MHz ∆f ± 1.5 MHz ∆f ± 2 MHz ∆f ± 3 MHz ∆f ± 10 MHz ∆f ± 20 MHz (14) ∆PBlock 56.5 62.0 66.5 71.0 73.0 dBC C
3.23 CDEM Capacitor connected to
pin 23 (CDEM) 23 –5% 15 +5% nF D 13. Electrical Characterist ics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN).
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 4X T O
4.1 Transconductance XTO at
At startup; after startup the amplitude is regulated to VPPXTAL 7,8 g m, XTO 20 mS B
4.2 XTO start-up time
C0 ≤ 2.2 pF Cm < 14 fF Rm ≤ 120Ω 7,8 T XTO_Startup 300 800 µs A 4.3 Maximum C 0 of XTAL 7,8 C 0max 3.8 pF D 4.4 Pulling of LO frequency fLO due to XTO, CL1 and CL2 versus temperature and supply changes 1.0 pF ≤ C0 ≤ 2.2 pF Cm = 4.0 fF to 7.0 fF Rm ≤ 120Ω 3 ∆fXTO –5 +5 ppm C
4.5 Amplitude XTAL after
Cm =5f F , C0 =1 . 8p F Rm = 15Ω V(XTAL1, XTAL2) peak-to-peak value 7,8 V PPXTAL 700 mVpp C V(XTAL1) peak-to-peak value 7,8 V PPXTAL 350 mVpp C 4.6 Maximum series resistance Rm of XTAL at startup C0 ≤ 2.2 pF , small signal start impedance, this value is important for crystal oscillator startup 7,8 Z XTAL12_START –1400 –2000 Ω B 4.7 Maximum series resistance Rm of XTAL after startup C0 ≤ 2.2 pF Cm < 14 fF 7,8 R m_max 15 120 Ω B
4.8 Nominal XTAL load
fRF = 433.92 MHz fRF =3 1 5M H z 7,8 f XTAL 13.57375
13.1433 MHz D
4.9 External CLK_OUT
CLK_OUT_CRTL1 = 0 CLK_OUT_CTRL0 = 0 --> CLK_OUT disabled 3f CLK_OUT fCLK disabled (low level on pin CLK_OUT) MHz A CLK_OUT_CRTL1 = 0 CLK_OUT_CTRL0 = 1 --> division ratio = 3 CLK_OUT_CRTL1 = 1 CLK_OUT_CTRL0 = 0 --> division ratio = 6 CLK_OUT_CRTL1 = 1 CLK_OUT_CTRL0 = 1 --> division ratio = 12 13. Electrical Characterist ics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN). fCLK fXTO fCLK fXTO fCLK fXTO
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] fRF =4 3 3 . 9 2M H z CLK_OUT division ratio = 3 = 6 = 12 CLK_OUT has nominal 50% duty cycle CLK_OUT 4.52458 2.26229 1.13114 MHz D fRF =3 1 5M H z CLK_OUT division ratio = 3 = 6 = 12 CLK_OUT has nominal 50% duty cycle CLK_OUT 4.3811 2.190 1.0952 MHz D
4.10 DC voltage after startup
VDC (XTAL1, XTAL2) XTO running (Standby mode, Active mode) 7,8 V DCXTO –250 –45 mV C
5 Synthesizer
5.1 Spurs in Active mode
At ±fCLK_OUT, CLK_OUT enabled (division ratio = 3) fRF =3 1 5M H z fRF =4 3 3 . 9 2M H z SPRX –75 –70 dBC C at ±fXTO fRF =3 1 5M H z fRF =4 3 3 . 9 2M H z SPRX –75 –70 dBC A
5.2 Phase noise at 3 MHz
fRF =3 1 5M H z fRF =4 3 3 . 9 2M H z LRX3M –130 –127 dBC/Hz A
5.3 Phase noise at 20 MHz
Active mode Noise floor L RX20M –135 –132 dBC/Hz B
6 Microcontroller Interface
6.1 CLK_OUT output rise and
fCLK_OUT <4 . 5M H z CL =1 0p F CL = Load capacitance on pin CLK_OUT 2.7V ≤ V VS5V ≤ 3.3V or 4.5V ≤ VVS5V ≤ 5.5V 20% to 80% VVS5V trise tfall ns ns B
6.2 Internal equivalent
calculation 3C CLK_OUT 8p F B 13. Electrical Characterist ics: General (Continued) Typical values are given at VVS3V_AVCC =V VS5V =3 V , Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin (1) Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis we re measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo- nent values as in Table 2-2 on page 6 (RFIN).
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 14. Electrical Characteri stic: 3V Application Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
7.1 Supply current in OFF
VVS3V_AVCC =V VS5V ≤ 3V CLK_OUT disabled 10, 11 I SOFF 2µ AA
7.2 Supported voltage
range 3V application 10, 11 VVS3V_AVCC, VVS5V 2.7 3.3 V A
7.3 Current in Standby
mode (XTO is running) VVS3V_AVCC = VVS5V ≤ 3V external load C on pin CLK_OUT = 12 pF CLK enabled (division ratio 3) CLK enabled (division ratio 6) CLK enabled (division ratio 12) CLK disabled 10, 11 I Standby 420 290 220 670 460 350 µA C C C A
7.4 Current during
T Startup_PLL VVS3V_AVCC = VVS5V ≤ 3V CLK disabled 10, 11 I Startup_PLL 4.5 mA C
7.5 Current in Active mode
VVS3V_AVCC = VVS5V ≤ 3V CLK disabled SENSE_CTRL = 0 10, 11 I Active 6.5 9.6 mA A
7.6 Current in Active mode
VVS3V_AVCC = VVS5V ≤ 3V CLK disabled SENSE_CTRL = 0 10, 11 I Active 6.7 9.8 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 15. Electrical Characteri stics: 5V Application Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
85 V A p p l i c a t i o n
8.1 Supply current in OFF
VVS5V =5 V CLK_OUT disabled 10 I SOFF 2µ AA
8.2 Supported voltage
range 5V application 10 V VS5V 4.5 5.5 V A 8.3 Current in Standby mode (XTO is running) VVS5V ≤ 5V external load C on pin CLK_OUT = 12 pF CLK enabled (division ratio 3) CLK enabled (division ratio 6) CLK enabled (division ratio 12) CLK disabled 10 I Standby 700 490 370 1120 780 590 µA C C C A
8.4 Current during
TStartup_PLL VVS5V =5 V CLK disabled 10 I Startup_PLL 4.7 mA C
8.5 Current in Active
VVS5V =5 V CLK disabled SENSE_CTRL = 0 10 I Active 6.7 9.8 mA A
8.6 Current in Active
VVS5V =5 V CLK disabled SENSE_CTRL = 0 10 I Active 6.9 10 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 16. Digital Timing Characteristics Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
9 Basic Clock Cycle of the Digital Circuitry
9.1 Basic clock cycle T DCLK 16 / fXTO 16 / fXTO µs A
9.2 Extended basic clock
BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 TXDCLK × TDCLK × TDCLK µs A
10 Active Mode
10.1 Startup PLL T Startup_PLL
15 µs + 208 × TDCLK µs A
10.2 Startup signal
BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 TStartup_Sig_Proc 929.5 545.5 353.5 257.5 × TDCLK 929.5 545.5 353.5 257.5 × TDCLK A
10.3 Bit rate range
BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 FSK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 2.0 4.0 8.0 1.0 2.0 4.0 8.0 2.5 5.0 10.0 10.0 2.5 5.0 10.0 20.0 Kbits/s A 10.4 Minimum time period between edges at pin DATA_OUT BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 24 T DATA_OUT_min 10 × TXDCLK µs A 10.5 Edge-to-edge time period of the data signal for full sensitivity in Active mode BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 T DATA_OUT 200 100 500 250 125 62.5 µs B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 17. Digital Port Characteristics Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
11 Digital Ports
11.1 ENABLE input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 6V Il 0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 6V Ih 0.8 × VS VA 11.2 RX input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V
19 V Il
0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 19 V Ih 0.8 × VS VA 11.3 BR0 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V
20 V Il
0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 20 V Ih 0.8 × VS VA 11.4 BR1 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V
21 V Il
0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 21 V Ih 0.8 × VS VA 11.5 ASK_NFSK input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V
22 V Il
0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 22 V Ih 0.8 × VS VA *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 11.6 SENSE_CTRL input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V
16 V Il
0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 16 V Ih 0.8 × VS VA 11.7 CLK_OUT_CTRL0 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 5V Il 0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 5V Ih 0.8 × VS VA 11.8 CLK_OUT_CTRL1 input - Low level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 4V Il 0.2 × VS 0.12 × VS VA - High level input voltage VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V 4V Ih 0.8 × VS VA
11.9 TEST1 input
11.10 TEST2 output
11.11 TEST3 input
- Digital Port Characteristics (Continued) Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 11.12 DATA_OUT output - Saturation voltage low VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = 250 µA 24 V ol 0.15 0.4 V B - Saturation voltage high VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = –250 µA 24 V oh VVS – 0.4 VVS – 0.15 VB 11.13 CLK_OUT output - Saturation voltage low VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = 100 µA 3V ol 0.15 0.4 V B - Saturation voltage high VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V VS = VVS5V = 4.5V to 5.5V IDATA_OUT = –100 µA 3V oh VVS – 0.4 VVS – 0.15 VB 17. Digital Port Characteristics (Continued) Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 19. Package Information 18. Ordering Information Extended Type Number Package MOQ Remarks ATA5745-PXPW QFN24 1500 pcs 5 mm × 5 mm, Pb-free, 433.92 MHz ATA5746-PXPW QFN24 1500 pcs 5 mm × 5 mm, Pb-free, 315 MHz ATA5745-PXQW QFN24 6000 pcs 5 mm × 5 mm, Pb-free, 433.92 MHz ATA5746-PXQW QFN24 6000 pcs 5 mm × 5 mm, Pb-free, 315 MHz specifications according to DIN technical drawings 0.3 0.4 0.9±0.1 Not indicated tolerances ±0.05 0.65 nom. 0.05-0.05 12 7 19 24 Issue: 1; 15.11.05 Drawing-No.: 6.543-5122.01-4 3.25 3.6 Dimensions in mm Package: QFN 24 - 5 x 5 Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220)
4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 20. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4596B-RKE-06/07
- Put datasheet in a new template
- Section 13 “Electrical Characteristics: General” numbers 2.1, 2.2 and 3.1 on pages 29 to 30 changed
- Section 14 “Electrical Characteristics: 3V Application” numbers 7.3, 7.5 and 7.6 on page 36 changed
- Section 15 “Electrical Characteristics: 5V Application” numbers 8.3, 8.5 and 8.6 on page 37 changed
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