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Features
- Minimal External Circuitry Requirements, no RF Components on the PC Board Except Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates SSO20 and SO20 package Fully Integrated VCO Supply Voltage 4.5V to 5.5V, Operating Temperature Range –40°C to +105°C Single-ended RF Input for Easy Adaptation to l/4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level Various Types of Protocols Supported (i.e., PWM, Manchester and Bi-phase) Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) ESD Protection According to MIL-STD. 883 (4KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Front-end Filter, up to 40 dB is thereby Achievable with Newer SAWs Power Management (Polling) is Possible by Means of a Separate Pin via the Microcontroller Receiving Bandwidth BIF = 600 kHz 1. Description The ATA5744 is a PLL receiver device for the receiving range of f 0 = 300 MHz to 450 MHz. It is developed for the demands of RF low-cost data communication sys- tems with low data rates and fits for most types of modulation schemes including Manchester, Bi-phase and most PWM protocols. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. Figure 1-1. System Block Diagram Demod. IF Amp LNA VCO PLL XTO Data interface ATA5744 1...3 Micro- controller Power amp. XTO VCO PLL U2741B Antenna Antenna UHF ASK/FSK Remote control transmitter UHF ASK Remote control receiver Encoder ATARx9x
1 Li cell
Rev. 4893A–RKE–11/05
4893A–RKE–11/05 ATA5744 2. Pin Configuration Figure 2-1. Pinning SO20 and SSO20 Table 2-1. Pin Description Pin Symbol Function
1 BR_0 Baud rate select LSB
2 BR_1 Baud rate select MSB
3 CDEM Lower cut-off frequency data filter
4 AVCC Analog power supply
5 AGND Analog ground
6 DGND Digital ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer
9 LNA_IN RF input
10 NC Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator
15 DVCC Digital power supply
16 MODE
Selecting 433.92 MHz /315 MHz Low: 315 MHz (USA) High: 433.92 MHz (Europe)
17 RSSI Output of the RSSI amplifier
18 TEST Test pin, during operation at GND
19 ENABLE
Low: sleep mode High: receiving mode
20 DATA Data output
LNA_IN BR_1 CDEM RSSI MODE XTO LFGND LF ENABLE TEST NC LFVCC DATA DVCC BR_0 ATA5744
4893A–RKE–11/05 ATA5744 Figure 2-2. Block Diagram 3. RF Front End The RF front end of the receiver is a heterodyne co nfiguration that converts the input signal into a 1-MHz IF signal. According to Figure 2-2 , the front end consists of an LNA (Low-Noise Ampli- fier), LO (Local Oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mi xer via a PLL synthesize r. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (Voltage-Controlled Oscillator) gen- erates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by factor 64. The divided frequency is compared to fXTO by the phase frequency detec- tor. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that f LO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to Figure 3-1 , the crystal should be connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When design- ing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. ASK- Demodulator and data filter RSSI IF Amp IF Amp 4. Order LPF
3 MHz
Dem_out RSSI Standby logic VCO XTO f CDEM AVCC RSSI AGND DGND MIXVCC LNAGND LNA_IN DATA ENABLE TEST MODE LFGND LFVCC XTO LF DVCC LNA Data interface Test BR_0 BR_1
4893A–RKE–11/05 ATA5744 Figure 3-1. PLL Peripherals The passive loop filter connected to pin LF is designed for a loop bandwidth of B Loop = 100 kHz. This value for B Loop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth fLO is determined by the RF input frequency f RF and the IF frequency f IF using the following formula: f LO = fRF – fIF To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency f XTO. This means that there is a fixed relation between f IF and fLO that depends on the logic level at pin mode. This is described by the following formulas: MODE = 0 USA fIF = fLO/314 MODE = 1 Europe fIF = fLO/432.92 The relation is designed to achieve the nominal IF frequency of f IF = 1 MHz for most applica- tions. For applications where f RF = 315 MHz, MODE must be set to '0'. In the case of fRF = 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on f RF. Table 3-1 on page 5 summa- rizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para- sitic board inductances and capacitances also in fluence the input matching. The RF receiver ATA5744 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network, is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network a mirror frequency suppression of ∆P Ref = 40 dB can be achieved. There are SAWs ava ilable that exhibit a notch at ∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. DVCC XTO LF LFVCC LFGND V C C10R1 S L VS R1 = 820 Ω C9 = 4.7 nF C10 = 1 nF
4893A–RKE–11/05 ATA5744 Figure 3-2 shows a typical input matching network for f RF = 315 MHz and f RF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates the input matching to 50 Ω without a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks for the parameters given in the electrical characteristics. Figure 3-2. Input Matching Network with SAW Filter Table 3-1. Calculation of LO and IF Frequency Conditions Local Osci llator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 f LO = 314 MHz f IF = 1 MHz fRF = 433.92 MHz, MODE = 1 f LO = 432.92 MHz f IF = 1 MHz
300 MHz < fRF < 365 MHz, MODE = 0
365 MHz < fRF < 450 MHz, MODE = 1
f LO fRF 1 1 fLO IN IN_GND OUT OUT_GND CASE_GND B3555 ATA5744 22p L 25n C16 100p C17 8.2p TOKO LL2012 F27NJ27n 8.2p TOKO LL2012 F33NJ 33n 3, 4 7, 8 RFIN fRF = 433.92 MHz LNAGND LNA_IN IN IN_GND OUT OUT_GND CASE_GND B3551 47p L 25n C16 100p C17 22p TOKO LL2012 F47NJ47n 10p TOKO LL2012 F82NJ 82n 3, 4 7, 8 fRF = 315 MHz LNAGND LNA_IN RFIN ATA5744
4893A–RKE–11/05 ATA5744 Figure 3-3. Input Matching Network without SAW Filter Please note that for all coupling conditions (see Figure 3-2 on page 5 and Figure 3-3 ), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this induc- tor can be easily printed on the PCB. This configur ation improves the sensitivity of the receiver by about 1 dB to 2 dB. 4. Analog Signal Processing
4.1 IF Amplifier
The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is f IF = 1 MHz for applications where f RF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 3-1 on page 5 to deter- mine the center frequency. The receiver ATA5744 employs an IF bandwidth of BIF = 600 kHz and can be used together with the U2741B in ASK mode.
4.2 RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input sig- nal at full sensitivity. ATA5744 15p 25n 100p3.3p TOKO LL2012 F22NJ 22n RFIN fRF = 433.92 MHz LNAGND LNA_IN C3 33p 25n 100p3.3p TOKO LL2012 F39NJ 39n fRF = 315 MHz LNAGND LNA_IN RFIN ATA5744
4893A–RKE–11/05 ATA5744
4.3 Pin RSSI
The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input power range PRef is –100 dBm to –55 dBm. Since different RF input networks may exhibit slig htly different values for the LNA gain, the sen- sitivity values given in the electrical characte ristics refer to a specific input matching. This matching is illustrated in Figure 3-3 and exhibits the best possible sensitivity. Figure 4-1. RSSI Characteristics
4.4 ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is conver ted into the raw data signal by the ASK demodulator. An automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly. The output signal of the demodulator is filtered by t he data filter before it is fed into the digital signal processing circuit. The data filter impr oves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order highpass and a 1st-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baudrate range (BR_Range). BR_Range is defined by the pins BR_0 and BR_1. BR_Range must be set in accordance to the used baudrate. 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 PRef (dBm) VRRSI (V) max. min. 25°C 105°C Tamb = 40°C fcu_DF 1
4893A–RKE–11/05 ATA5744 Each BR_Range is defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.
4.5 Receiving Characteristics
The RF receiver ATA5744 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end f ilter is illustrated in Figure 4-1 on page 7 . Note that the mirror fre- quency is reduced by 40 dB. The plots are printe d relatively to the maxi mum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in te rms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA5744. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA5744 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent. Figure 4-2. Receiving Frequency Response Table 4-1. Definition of BR_Range by the Pins BR_0 and BR_1 BR_1 BR_0 BR_Range 000 011 102 112 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 df (MHz) dP (dB) without SAW with SAW
4893A–RKE–11/05 ATA5744
4.6 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 4-3 , this clock cycle TClk is derived from the crystal oscillator (XTO) in com- bination with a divider. The division factor is controlled by the logical state at pin MODE. According to chapter 'RF Front End', t he frequency of the crystal oscillator (f XTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). Figure 4-3. Generation of the Basic Clock Cycle Pin MODE can now be set in accordance with the desired clock cycle T Clk. TClk controls the fol- lowing application-relevant parameters: Timing of the analog and digital signal processing IF filter center frequency (fIF0) Most applications are dominated by two transmission frequencies: f Send = 315 MHz is mainly used in USA, f Send = 433.92 MHz in Europe. In order to ease the usage of all T Clk-dependent parameters, the electrical characteristics display three conditions for each parameter. Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs) Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs) Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined by the pins BR_0 and BR_1. This clock cycle T XClk is defined by the following formulas for further reference: BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk DVCC XTO MODE TClk fXTO XTO Divider :14/:10 L : USA(:10) H: Europe(:14)
4893A–RKE–11/05 ATA5744 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage V S 6V Power dissipation P tot 450 mW Junction temperature T j 150 °C Storage temperature T stg –55 +125 °C Ambient temperature T amb –40 +105 °C Maximum input level, input matched to 50Ω Pin_max 10 dBm 8. Thermal Resistance Parameters Symbol Value Unit Junction ambient SO20 package R thJA 100 K/W Junction ambient SSO20 package R thJA 100 K/W
4893A–RKE–11/05 ATA5744 1 dB compression point (LNA, mixer, IF amplifier) Input matched according to Figure 3-3 on page 6 , referred to RFin IP1db –40 dBm Maximum input level Input matched according to Figure 3-3 on page 6 , BER ≤ 10-3 Pin_max –20 dBm Local Oscillator Operating frequency range VCO fVCO 299 449 MHz Phase noise VCO/LO fosc = 432.92 MHz at 1 MHz at 10 MHz L (fm) –93 –113 –90 –110 dBC/Hz dBC/Hz Spurious of the VCO at ±f XTO –55 –47 dBC VCO gain K VCO 190 MHz/V Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820Ω C9 = 4.7 nF C10 = 1 nF BLoop 100 kHz Capacitive load at pin LF C LF_tot 10 nF XTO operating frequency XTO crystal frequency, appropriate load capacitance must be connected to XTAL f XTAL = 6.764375 MHz (EU) fXTAL = 4.90625 MHz (US) fXTO 6.764375 –30 ppm 4.90625 –30 ppm 6.764375 4.90625 6.764375 +30 ppm 4.90625 +30 ppm MHz MHz Series resonance resistor of the crystal fXTO = 6.764 MHz
4.906 MHz RS
Ω Ω Static capacitance of the crystal C o 6.5 pF Analog Signal Processing Input sensitivity Input matched according to Figure 3-3 ASK (level of carrier) BER ≤ 10-3 (Manchester), fin = 433.92 MHz/ 315 MHz T = 25°C, VS = 5V, fIF = 1 MHz PRef_ASK BR_Range0 (1 kBd) –107 –110 –112 dBm BR_Range1 (2 kBd) –105 –108 –110 dBm BR_Range2 (4kBd) –103 –106 –108 dBm BR_Range3 (8 kBd) –101 –104 –106 dBm Sensitivity variation for the full operating range compared to T amb = 25°C, VS = 5V fin = 433.92 MHz/315 MHz fIF = 1 MHz PASK = PRef_ASK + ∆PRef ∆PRef +2.5 –1.5 dB 10. Electrical Characteristics (continued) Parameters Test Conditions Symbol Min. Typ. Max. Unit
4893A–RKE–11/05 ATA5744 Sensitivity variation for full operating range including IF filter compared to T amb = 25°C, VS = 5V fin = 433.92 MHz/ 315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + ∆PRef ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB S/N ratio to suppress inband noise signals SNR 10 12 dB Dynamic range RSSI amplifier ∆R RSSI 60 dB RSSI output voltage range V RSSI 1.0 3.0 V RSSI gain G RSSI 20 mV/dB RI of pin CDEM for cut-off frequency calculation R I 28 40 55 k Ω Recommended CDEM for best performance BR_Range0 BR_Range1 BR_Range2 BR_Range3 CDEM 6.8 nF nF nF nF Upper cut-off frequency data filter Upper cut-off frequency BR_Range0 BR_Range1 BR_Range2 BR_Range3 f u 1.75 3.5 7.0 14.0 2.2 4.4 8.8 17.6 2.65 5.3 10.6 21.2 kHz kHz kHz kHz Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor I ol = 1 mA VOI RPup 39 0.08 0.3 V kΩ ENABLE input - Low-level input voltage - High-level input voltage Sleep mode Receiving mode V Il VIh 0.8 × VS 0.2 × VS V V MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 V Il VIh 0.8 × VS 0.2 × VS V V BR_0 input - Low-level input voltage - High-level input voltage VIl VIh 0.8 × VS 0.2 × VS V V BR_1 input - Low-level input voltage - High-level input voltage VIl VIh 0.8 × VS 0.2 × VS V V TEST input - Low-level input voltage Test input must always be set to LOW V Il 0.2 × VS V 10. Electrical Characteristics (continued) Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF 1
4893A–RKE–11/05 ATA5744 12. Package Information 11. Ordering Information Extended Type Number Package Remarks ATA5744N-TKSY SSO20 Tube, Pb-free ATA5744N-TKQY SSO20 Taped and reeled, Pb-free ATA5744N-TGSY SO20 Tube, Pb-free ATA5744N-TGQY SO20 Taped and reeled, Pb-free technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 11 0
4893A–RKE–11/05 ATA5744 technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0
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