ATA5743

ATA5743 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 43

Technical content

Features

• Two Different IF Receiving Bandwidth Versions are Available (BIF = 300 kHz or 600 kHz)  5V to 20V Automotive-Compatible Data Interface  IC Condition Indicator, Sleep or Active Mode  Data Clock Available for Manchester- and Bi-phase-coded Signals  Fully Integrated VCO  Supply Voltage 4.5V to 5.5V, Operating Temperature Range -40°C to +105°C  Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB  ESD Protection According to MIL-STD. 883 (2KV HBM)  High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Front-end Filter; Up to 40 dB is Achievable with State-of-the-art SAWs  Communication to Microcontroller Possible Via a Single, Bi-directional Data Line  Power Management (Polling) is also Possible by Means of a Separate Pin Via the Microcontroller  Programmable Digital Noise Suppression  SSO20 Package Benefits  Low Power Consumption Due to Configurable Self Polling with a Programmable Time frame Check  High Sensitivity, Especially at Low Data Rates  Minimal External Circuitry Requirements, no RF Components on the PC Board Except Matching to the Receiver Antenna  Sensitivity Reduction Possible Even While Receiving  Low-cost Solution Due to High Integration Level 1. Description The ATA5743 is a multi-chip PLL receiv er device supplied in an SSO20 package. It has been especially developed for the demands of RF low-cost data transmission sys- tems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with At mel's PLL RF transmitter U2741B. Its main applications are in the areas of telemeteri ng, security technology, and keyless-entry systems. It can be used in the frequency receiving range of f 0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the statements made below refer to 433.92 MHz and 315 MHz applications. UHF ASK/FSK Receiver ATA5743 Rev. 4839B–RKE–08/05

4839B–RKE–08/05 ATA5743 Table 3-1. Pin Description Pin Symbol Function

1 SENS Sensitivity-control resistor

2I C _ A C T I V E IC condition indicator Low = sleep mode High = active mode

3 CDEM Lower cut-off frequency data filter

4 AVCC Analog power supply

5 TEST Test pin, during operation at GND

6 AGND Analog ground

7 MIXVCC Power supply mixer

8 LNAGND High-frequency ground LNA and mixer

9 LNA_IN RF input

10 NC Not connected

11 LFVCC Power supply VCO

12 LF Loop filter

13 LFGND Ground VCO

14 XTO Crystal oscillator

15 DVCC Digital power supply

16 MODE

Selecting 433.92 MHz/315 MHz Low: f XT0 = 4.90625 MHz (USA) High: fXT0 = 6.76438 MHz (Europe)

17 DATA_CLK Bit clock of data stream

18 DGND Digital ground

19 POLLING/_ON

Selects polling or receiving mode Low: receiving mode High: polling mode

20 DATA Data output/configuration input

4839B–RKE–08/05 ATA5743 Figure 3-2. Block Diagram FSK/ASK Demodulator and data filter IF Amp IF Amp 4. Order LPF

3 MHz

Dem_out Limiter outRSSI Sensitivity reduction Standby logic Polling circuit and control logic FE CLK VCO XTO f CDEM AVCC SENS AGND DGND MIXVCC LNAGND LNA_IN DATA POLLING/_ON TEST DATA_CLK MODE LFGND LFVCC XTO LF DVCC LNA IC_ACTIVE Data Interface

4839B–RKE–08/05 ATA5743 4. RF Front-end The RF front-end of the receiver is a heterodyne configuration that converts the input signal into a 1 MHz IF signal. As seen in Figure 3-2 on page 4, the front-end consists of an LNA (Low-Noise Amplifier), an LO (Local Oscillator), a mixer, and an RF amplifier. The LO generates the carrier frequency for the mi xer via a PLL synthesize r. The XTO (crystal oscillator) generates the reference frequency f XTO. The VCO (voltage-controlled oscillator) gen- erates the drive voltage frequency f LO for the mixer. f LO is dependent on the voltage at pin LF, and is then divided by 64. The divided frequency is compared to f XTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage V LF for the VCO. By means of that configuration, V LF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64. The XTO is a one-pin oscillator t hat operates at the se ries resonance of the quartz crystal. As demonstrated in Figure 4-1 , the crystal should be connected to GND via a capacitor C L. The value of that capacitor is recommended by the crystal supplier. The value of C L should be opti- mized for the individual board layout to achieve the exact value of f XTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. Figure 4-1. PLL Peripherals The passive loop filter connected to pin LF is designed for a loop bandwidth of B Loop = 100 kHz. This value for B Loop exhibits the best possible noise performance of the LO. Figure 4-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo- nents are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longe r be possible since f LO can- not settle in time before the bit check starts to evaluate the incoming data stream. Self polling will also not work in that case. fLO is determined by the RF input frequency f RF and the IF frequency f IF using the following for- mula: fLO = fRF - fIF To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter is tuned by the crystal frequency f XTO. This means that there is a fixed relation between f IF and fLO. This relation is dependent on the logic level at pin MODE. DVCC XTO LF LFVCC LFGND V C C10R1 S L VS R1 = 820 Ω C9 = 4.7 nF C10 = 1 nF

4839B–RKE–08/05 ATA5743 This is described by the following formulas: The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where f RF = 315 MHz, MODE must be set to “0”. In the case of fRF = 433.92 MHz, MODE must be set to “1”. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on f RF. Table 4-1 summarizes the dif- ferent conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para- sitic board inductances and capacitances also in fluence the input matching. The RF receiver ATA5743 exhibits its highest sensitivity at t he best signal-to-noise ratio (SNR) in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef = 40 dB can be achieved. There are SAWs ava ilable that exhibit a notch at ∆f = 2 MHz. These SAWs work best for an intermediate frequency of f IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 4-2 on page 7 shows a typical input matching network, for f RF = 315 MHz and fRF = 433.92 MHz, using a SAW. Figure 4-3 on page 7 illustrates an according input matching to 50Ω without a SAW. The input matching networks shown in Figure 4-3 on page 7 are the refer- ence networks for the parameters given in the table “Electrical Characteristics” on page 33. Table 4-1. Calculation of LO and IF Frequency Conditions Local Osci llator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 f LO = 314 MHz f IF = 1 MHz fRF = 433.92 MHz, MODE = 1 f LO = 432.92 MHz f IF = 1 MHz

300 MHz < fRF < 365 MHz,

MODE = 0

365 MHz < fRF < 450 MHz,

MODE = 1 MODE 0 (USA) : f IF fLO MODE 1 (Europe) : f IF fLO fLO fRF 1 1 fIF fLO fLO fRF 1 1 fLO

4839B–RKE–08/05 ATA5743 5. Analog Signal Processing

5.1 IF Amplifier

The signals coming from the RF front-end are filtered by the fully integrated 4 th-order IF filter. The IF center frequency is f IF = 1 MHz for applications where f RF = 315 MHz or fRF = 433.92 MHz. For other RF input frequencies refer to Table 4-1 on page 6 to determine the center frequency. The ATA5743 is available with two different IF bandwidths. ATA5743P3, the version with BIF = 300 kHz, is well suited for ASK systems w here Atmel’s PLL transmitter U2741B is used. The receiver ATA5743P6 employs an IF bandwidth of BIF = 600 kHz. Both versions can be used together with the U2741B in ASK and FSK mode. If used in ASK applications, higher tolerances for the receiver and PLL transmitter crystals are allowed. SAW transmitters exhibit much higher transmit frequency tolerances compared to PLL trans mitters. Generally, it is necessary to use B IF = 600 kHz together with SAW transmitters.

5.2 RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DR RSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best SNR is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI out- put voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the power of the input si gnal is 60 dB higher than the sensitivity of the receiver. In FSK mode the SNR is not affected by the dynamic range of the RSSI amplifier. The output voltage of the RSSI amplifier is internally compared to a threshold voltage V Th_red. VTh_red is determined by the value of the external resistor R Sense. RSense is connected between pin SENS and GND or V S. The output of the comparator is fed into the digital control logic. By this means it is possible to operate the receiver at a lower sensitivity. If RSense is connected to GND, the receiver operates at full sensitivity. If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of R Sense , the maximum sensitivity by the SNR of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slig htly different values for the LNA gain, the sen- sitivity values given in the electrical characte ristics refer to a specific input matching. This matching is illustrated in Figure 4-3 on page 7 and exhibits the best possible sensitivity. RSense can be connected to V S or GND via a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at an y time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern shown in Figure 5-1 on page 9 is issued at pin DATA to indicate that the receiver is still active (see Figure 6-26 on page 29).

4839B–RKE–08/05 ATA5743 Figure 5-1. Steady L State Limited DATA Output Pattern

5.3 FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode. In ASK mode, an automatic threshold control circuit (ATC) is used to set the detection reference voltage to a value where a good SNR is achieved. This circuit effectively suppresses any kind of inband noise signals or competing transmitters. If the SNR (ratio to suppress inband noise sig- nals) exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of 10 kHz ≤ ∆f ≤ 100 kHz. In FSK mode the data signal can be detected if the SNR (ratio to suppress inband noise signals) exceeds 2 dB. This value is guaranteed for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by t he data filter before it is fed into the digital signal processing ci rcuit. The data filter improves the SNR as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1 st-order high-pass and a 2nd-order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the low-pass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to section “Configuration of the Receiver” on page 24). The BR_Range must be set in accordance to the used baud rate. The ATA5743 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V DC_min = 33% and VDC_max = 66%. Even then, the sensitivity will be reduced by up to 2 dB. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). These limits are defined in the electrical charac teristics; to maintain full sensitivity of the receiver, they should not be exceeded. DATA tDATA_L_maxtDATA_min fcu_DF 1

4839B–RKE–08/05 ATA5743

5.4 Receiving Characteristics

The RF receiver ATA5743 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 5-2. This example relates to ASK mode and the 300-kHz bandwidth version of the ATA5743. FSK mode and the 600-kHz bandwidth version of the receiver exhibit similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relative to the maximum sensitivit y. If a SAW filter is used, an insertion loss of about 4 dB must be considered. Figure 5-2. Receiving Frequency Response When designing the system in te rms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA5743. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA5743 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode, but not in FSK mode. 6. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is ac hieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected will the receiver remain active and trans- fer the data to the connected microcontroller. If there is no valid signal present, the receiver remains in sleep mode most of the time, resulting in low current consumption; this condition is called polling mode. A connected microcontroller is disabled during this time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate, etc. Regarding the number of connection wires to the micr ocontroller, the receiver is very flexible. It can be either operated by a single bi-directional line (to save ports to the connected microcon- troller), or it can be operated by up to five uni-directional ports. -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 df (MHz) dP (dB) with SAW without SAW

4839B–RKE–08/05 ATA5743

6.1 Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and th e analog filtering is derived from one clock. As seen in Figure 6-1, this clock cycle T Clk is derived from the crystal oscillator (XTO) in combina- tion with a divider. The division factor is cont rolled by the logical state at pin MODE. As described in section “RF Front-end” on page 5, the frequency of the crystal oscillator (f XTO) is defined by the RF input signal (f RFin) which also defines the operating frequency of the local oscillator (fLO). Figure 6-1. Generation of the Basic Clock Cycle Pin MODE can now be set in accordan ce with the desired clock cycle T Clk, which controls the following application relevant parameters:  Timing of the polling circuit including bit check  Timing of the analog and digital signal processing  Timing of the register programming  Frequency of the reset marker  IF filter center frequency (f IF0) Most applications are dominated by two transmission frequencies: f Send = 315 MHz is mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters on these electrical characteristics, here are displayed the three conditions for each parameter.  Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)  Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)  Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T XClk is defined by the following for- mulas for further reference: BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk DVCC XTO MODE TCLK fXTO 14XTO Divider :14/:10 L : USA(:10) H: Europe(:14)

4839B–RKE–08/05 ATA5743

6.2 Polling Mode

As shown in Figure 6-2 on page 13, the receiver’s polling mode consists of a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of I S = ISoff. During the start-up period, T Startup, all sig- nal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit-by-bit, looking for a valid transmitter signal . If no valid signal is present, the receiver is set back to sleep mode after the period T Bit-check . This period varies check-by-check as it is a statistical process. An average value for TBit-check is given in the electri- cal characteristics. During T Startup and T Bit-check , the current consumption is I S = I Son . The condition of the receiver is indicated on pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitt er must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters T Sleep, TStartup, TBit-check, and the start-up time of a connected microcontroller (TStart, µC). Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. The following formula indicates how to calculate the preburst length. T Preburst ≥ TSleep + TStartup + TBit-check + TStart_µC

6.3 Sleep Mode

The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the exten- sion factor X Sleep (see Table 6-8 on page 26 ), and the basic clock cycle T Clk. It is calculated to be: TSleep = Sleep × XSleep × 1024 × TClk In US and European applications, the maximum value of T Sleep is about 60 ms if X Sleep is set to “1”; the time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by setting bit XSleepStd to “1”. As seen in Table 6-7 on page 26 , the highest register value of sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This func tion is desirable where several devices share a single data line and may also be used for microcontroller polling – via pin POLLING/_ON, the receiver can be switched on and off. I Spoll ISoff TSleep ISon TStartup TBit-check+()×+×

4839B–RKE–08/05 ATA5743 Figure 6-2. Polling Mode Flow Chart Bit-check OK? Sleep: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register NO YES Sleep Mode: All circuits for signal processing are disabled. Only XTO and polling logic are enabled. Output level on pin IC_ACTIVE => low I S = ISoff TSleep = Sleep × XSleep × 1024 × TClk Start-up Mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in a stable condition and ready to receive. Output level on pin IC_ACTIVE => high I S = ISon TStartup Bit-check Mode: The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receive mode. Otherwise it is set to Sleep mode. Output level on pin IC_ACTIVE => high I S = ISon TBit-check Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or POLLING/_ON. Output level on pin IC_ACTIVE => high I S = ISon OFF command XSleep: Extension factor defined by X SleepStd according to Table 9 TClk: Basic clock cycle defined by f XTO and pin MODE TStartup: Defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register TBit-check: Depends on the result of the bit check If the bit check is ok, TBit-check depends on the number of bits to be checked Bit-check), and on the utilized data rate If the bit check fails, the average time period for that check depends on the selected baud-rate range on T Clk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register

4839B–RKE–08/05 ATA5743 Figure 6-3. Timing Diagram for Complete Successful Bit Check

6.3.1 Bit-check Mode

In bit-check mode the incoming data stream is ex amined to distinguish between a valid signal from a corresponding transmitter, and signals d ue to noise. This is done by subsequent time frame checks where the distances between two signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge test before the receiver switches to receiving mode is also programmable.

6.3.2 Configuring the Bit Check

Assuming a modulation scheme that contains two edges per bit, two time frame checks verify one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maxi- mum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N Bit-check in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks, respectively. If NBit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if N Bit-check is set to a lower value. In polling mode, the bit-check time is not dependent on N Bit-check . Figure 6-3 shows an example where 3 bits are tested successfully and the data signal is transferred to pin DATA. As demonstrated in Figure 6-4, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time t ee is between the lower bit-check limit, T Lim_min, and the upper bit-check limit, TLim_max, the check will be continued. If t ee is smaller than TLim_min, or tee exceeds TLim_max, the bit check will be terminated and the receiver will switch to sleep mode. Figure 6-4. Valid Time Window for Bit Check For best noise immunity it is recommended to use a low span between T Lim_min and T Lim_max . This is achieved by using a fixed frequency at a 50% duty cycle for the transmitter preburst. For good compromise between receiver sensitivity an d susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge time t ee. Using preburst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. Bit check IC_ACTIVE Data_out (DATA) 1/2 Bit Start-up mode (Number of checked Bits: 3) Bit check ok 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Receiving mode Dem_out Bit-check mode TStart-up TBit-check Dem_out tee TLim_min TLim_max 1/fSig

4839B–RKE–08/05 ATA5743 Figure 6-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

6.3.3 Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for T Bit-check is given in the electrical characteristics. T Bit-check depends on the selected baud-rate range and on T Clk. A higher baud-rate range causes a lower value for TBit-check, resulting in lower current consumption in polling mode. In the presence of a valid transmitter signal, T Bit-check is dependent on the frequency of that sig- nal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in a longer period for TBit-check, requiring a higher value for the transmitter preburst, TPreburst.

6.3.4 Receiving Mode

If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. As shown in Figure 6-3 on page 14, the internal data signal is then switched to pin DATA, and the data clock is available after the start bit has been detected ( Figure 6-14 on page 20). A connected microcontroller can be woken up by the negative edge at pin DATA or by the data clock at pin DATA_CLK. The receiv er stays in that condition until it is switched back to polling mode explicitly.

6.3.5 Digital Signal Processing

The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 6-8 on page 17 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only after T XClk has elapsed. The edge-to-edge time period t ee of the Data signal, as a result, is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to t ee ≥ TDATA_min (see Figure 6-9 on page 17 ). This implies an efficient suppression of spikes at the DATA output during data reception. At the same time, it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay Low is limited to T DATA_L_max . This function is employed to ensure a finite response time in programming or switching off the receiver via pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 6-10 on page 17 shows an example where Dem_out remains Low after the receiver has switched to receiving mode. Bit check IC_ACTIVE Bit-check- counter 0 2345 6 24 51 7 36 7 8 9 11 1210 1/2 Bit Start-up mode (Lim_min = 14, Lim_max = 24) Sleep mode Bit check failed ( CV_Lim ≥ Lim_max ) 13 14 15 16 17 18 19 21 22 23 24 01 Dem_out Bit-check mode TStart-up TBit-check TSleep

4839B–RKE–08/05 ATA5743

6.3.6 Switching the Receiver Back to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON. When using pin DATA, this pin must be pulled to Low by the connected microcontroller for the period t1. Figure 6-11 illustrates the timing of the OFF command (see also Figure 6-26 on page 29). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not lim- ited, but it is recommended not to exceed the specified value to prevent erasing the reset marker. (see section “Programming the Configuration Register” on page 28 ) Note also that an internal reset for the OPMODE and the LIMIT register will be gener ated if t1 exceeds the speci- fied values. This item is explained in more detail in the section “Configuration of the Receiver” on page 24. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to be “1” during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command the sleep time TSleep elapses. Note that the capacitive load at pin DATA is limited (see section “Data Interface” on page 30). Figure 6-11. Timing Diagram of the OFF command via Pin DATA Figure 6-12. Timing Diagram of the OFF command via Pin POLLING/_ON Data_out (DATA) Serial bi-directional data line X Bit 1 ("1") X t1 t2 t3 (Start bit) Start-up mode OFF command TSleep Receiving mode t10 Sleep mode TStart-up IC_ACTIVE Out1 (microcontroller) POLLING/_ON Data_out (DATA) Serial bi-directional data line Receiving mode X Sleep mode Start-up mode Bit-check mode Receiving mode X Bit check ok X X ton2 ton3 IC_ACTIVE

4839B–RKE–08/05 ATA5743 Figure 6-13. Activating the Receiving Mode via Pin POLLING/_ON Figure 6-12 on page 18 illustrates how to set the receiver back to polling mode via pin POLLING/_ON. The pin POLLING/_ON must be held to low for the time period t on2. After the positive edge on pin POLLING/_ON and the delay t on3, the polling mode is active and the sleep time TSleep elapses. This command is faster than using pin DATA, but at the cost of an additional connection to the microcontroller. Figure 6-13 illustrates how to set the receiver to receive mode via the pin POLLING/_ON. The pin POLLING/_ON must be held to Low. After the delay t on1, the receiver changes from sleep mode to start-up mode regardless of the programmed values for T Sleep and NBit-check. As long as POLLING/_ON is held to Low, the values for T Sleep and NBit-check will be ignored, but not deleted (see section “Digital Noise Suppression” on page 22). If the receiver is polled exclusively by a microcontroller, T Sleep must be programmed to 31 (permanent sleep mode). In this case, the receiver remains in sleep mode as long as POLL- ING/_ON is held to High.

6.4 Data Clock

The pin DATA_CLK makes a data shift clock avail able to sample the data stream into a shift register. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester- and Bi-phase-coded signals.

6.4.1 Generation of the Data Clock

After a successful bit check, the receiver switc hes from polling mode to receiving mode and the data stream is available at pin DATA. In receiv ing mode, the data clock control logic (Manches- ter/Bi-phase demodulator) is active and examines the incoming data stream. This is done, as in the bit check, by subsequent time frame chec ks where the distance between two edges is con- tinuously compared to a programmable time win dow. As illustrated in Figure 6-14 on page 20 , only two distances between two edges in Manchester- and Bi-phase-coded signals are valid (T and 2T). The limits for T are the same as used for the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see Table 6-10 on page 27 and Table 6-11 on page 27). POLLING/_ON Data_out (DATA) Serial bi-directional data line Sleep mode Receiving mode X X ton1 Start-up mode IC_ACTIVE

4839B–RKE–08/05 ATA5743 Figure 6-18. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) Figure 6-19. Timing Characteristic of the Data Clock (Falling Edge on Pin DATA)

6.5 Digital Noise Suppression

After a data transmission, digital noise appears on the data output (see Figure 6-20 on page 23). To prevent digital noise from keeping the connec ted microcontroller busy, it can be suppressed in two different ways.

6.5.1 Automatic Noise Suppression

The automatic noise suppression is illustrated in Figure 6-21 on page 23 . If the bit Noise_Disable ( Table 6-9 on page 26 ) in the OPMODE register is set to “1” (default), the receiver changes to bit-check mode at the end of a valid data stream. The digital noise is sup- pressed and the level at pin DATA is High in that case. The receiver changes back to receiving mode, if the bit check was successful. This way of suppressing the noise is recommended if the data stream is Manchester or Bi-phase coded and is active after power on. Figure 6-22 on page 23 illustrates the behavior of the data output at t he end of a data stream. Note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range. VIh = 0.65 × VS VX DATA_CLK Serial bi-directional data line tDelay1 tP_Data_Clk Data_Out Data_In tDelay2 tDelay VII = 0.35 × VS VIh = 0.65 × VS VX DATA_CLK Serial bi-directional data line tDelay1 tP_Data_Clk Data_Out Data_In tDelay2 tDelay VII = 0.35 × VS

4839B–RKE–08/05 ATA5743 Figure 6-20. Output of Digital Noise at the End of the Data Stream Figure 6-21. Automatic Noise Suppression Figure 6-22. Occurrence of a Pulse at the End of the Data Stream

6.5.2 Controlled Noise Suppression by the Microcontroller

The controlled noise suppressionis illustrated in Figure 6-23 on page 24. If the bit Noise_Disable (see Table 6-9 on page 26) in the OPMODE register is set to “0”, digital noise appears at the end of a valid data stream. To suppress the noise, the pin POLLING/_ON must be set to Low. The receiver remains in receiving mode. Then, the OFF command causes the change to the start-up mode. The programmed sleep time (see Table 6-7 on page 26) will not be executed because the level at pin POLLING/_ON is Low, but the bit check is active. The OFF command activates the bit check also if the pin POLLING/_ON is held to Low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data trans- mission, the pin POLLING/_ON must be set to High. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded. Data_out (DATA) DATA_CLK Preburst Data Digital Noise Preburst Data Digital NoiseDigital Noise Bit check ok Bit-check mode Bit check ok Receiving mode, bit check aktive Receiving mode, bit check aktive Receiving mode, data clock control logic active Receiving mode, data clock control logic active Data_out (DATA) DATA_CLK Preburst Data Preburst Data Bit check ok Bit check ok Bit-check mode Bit-check mode Bit-check mode Receiving mode, data clock control logic active Receiving mode, data clock control logic active Dem_out Data_out (DATA) DATA_CLK 1 11 Timing error Tee Bit-check modeReceiving mode, data clock control logic active Data stream Digital noise TPulse (Tee < TLim_min or TLim_max < Tee < TLim_min_2T or T ee > TLim_max_2T )

4839B–RKE–08/05 ATA5743 Figure 6-23. Controlled Noise Suppression

6.6 Configuration of the Receiver

The ATA5743 receiver is configured via two 12 -bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register con- tents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 6-3 on page 25 shows the structure of the regis- ters. As seen in Table 6-1, bit 1 defines if the receiver is set back to polling mode via the OFF command (see section “Receiving Mode” on page 16) or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. To get a high program- ming reliability, bit 15 (Stop bit), at the end of the programming operation, must be set to “0”. Serial bi-directional data line (DATA_CLK) Preburst Data Digital Noise Preburst Data Digital Noise Bit check ok Bit check ok Receiving mode POLLING/_ON OFF command Receiving modeStart-up mode Bit-check mode Sleep mode Bit-check mode Table 6-1. Effect of Bit 1 and Bit 2 on Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 6-2. Effect of Bit 15 on Programming the Register Bit 15 Action

0 The values will be written into the register (OPMODE or LIMIT)

1 The values will not be written into the register

4839B–RKE–08/05 ATA5743 Table 6-4 on page 25 to Table 6-11 on page 27 illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T Lim_min and TLim_max as shown in Table 6-10 on page 27 and Table 6-11 on page 27. Table 6-3. Effect of the Configuration Words Within the Registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF command OPMODE register BR_Range N Bit-check Modu-lat ion Sleep X Sleep Noise Suppression Baud1 Baud0 BitChk1 BitChk0 ASK/_ FSK Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X SleepStd Noise_ Disable Default values of bits 3 to 14 0 0 010001100 1 LIMIT register Lim_min Lim_max 0Lim_ min5 Lim_ min4 Lim_ min3 Lim_ min2 Lim_ min1 Lim_ min0 Lim_ max5 Lim_ max4 Lim_ max3 Lim_ max2 Lim_ max1 Lim_max0 Default values of bits 3 to 14 0 1 010110100 1 Table 6-4. Effect of the Configuration Word BR_Range BR_Range Baud-Rate Range/Extension Factor for Bit-Check Limits (XLim)Baud1 Baud0 00 BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) XLim = 8 (default) 01 BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 10 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 11 BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 6-5. Effect of the Configuration Word NBit-check NBit-check Number of Bits to be CheckedBitChk1 BitChk0 00 0 0 1 3 (default) 10 6 11 9

4839B–RKE–08/05 ATA5743 Table 6-6. Effect of the Configuration Bit Modulation Modulation Selected Modulation ASK/_FSK

0 FSK (default)

1 ASK

Table 6-7. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 00000 0 (Receiver is continuously polling until a valid signal occurs) 00001 1 (TSleep ≈ 2 ms for XSleep = 1 in US-/European applications) 00010 2 00011 3 00110 6 (USA: T Sleep = 12.52 ms, Europe: TSleep = 12.72 ms) (default) 11101 2 9 11110 3 0 11111 3 1 ( P e r m a n e n t s l eep mode) Table 6-8. Effect of the Configuration Bit XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk)XSleepStd 0 1 (default) Table 6-9. Effect of the Configuration Bit Noise Suppression Noise Suppression Suppression of the Digital Noise at Pin DATANoise_Disable

0 Noise suppression is inactive

1 Noise suppression is active (default)

4839B–RKE–08/05 ATA5743 Note: 1. Lim_min is also used to determine the margins of the data clock control logic (see section “Data Clock” on page 19). Note: 1. Lim_max is also used to determine the marg ins of the data clock control logic (see section “Data Clock” on page 19).

6.6.1 Conservation of the Register Information

The ATA5743 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. As seen in Figure 6-24 on page 28, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage V ThReset . The default parameters are programmed into the configuration registers in that condition. Once VS exceeds VThReset the POR is cancelled after the minimum reset period t Rst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency fRM at a 50% duty-cycle. RM can be cancelled via a Low pulse t1 at pin DATA. Table 6-10. Effect of the Configuration Word Lim_min Lim_min(1) (Lim_min < 10 Is Not Applicable) Lower Limit Value for Bit Check Lim_min5 Lim_min4 Lim_min3 Li m_min2 Lim_min1 Lim_min0 (T Lim_min = Lim_min × Lim × TClk) 001010 1 0 001011 1 1 001100 1 2 010101 21 (default) USA: T Lim_min = 342 µs, Europe: TLim_min = 348 µs) 111101 6 1 111110 6 2 111111 6 3 Table 6-11. Effect of the Configuration Word Lim_max Lim_max(1) (Lim_max < 12 Is Not Applicable) Upper Limit Value for Bit Check Lim_max Lim_max Lim_max Lim_max Lim_max Lim_max 0( T Lim_max = (Lim_max - 1) × XLim × TClk) 001100 1 2 001101 1 3 001110 1 4 101001 41 (default) USA: T Lim_max = 652 µs, Europe: TLim_max = 662 µs) 111101 6 1 111110 6 2 111111 6 3

4839B–RKE–08/05 ATA5743 The RM implies the following characteristics: f RM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected microcontroller.  If the receiver is set back to polling mode via pin DATA, RM cannot be cancelled by accident if t1 is applied according to the proposal in the section “Programming the Configuration Register” on page 28. By means of that mechanism the receiver cannot lose its register information without communi- cating that condition via the reset marker RM. Figure 6-24. Generation of the Power-on Reset

6.6.2 Programming the C onfiguration Register

Figure 6-25. Timing of the Register Programming VS POR Data_out (DATA) 1/fRM tRst VThReset X Out1 (µC) Data_out (DATA) Serial bi-directional data line X Bit 1 (0) Bit 2 (1) Bit 14 (0) Bit 15 (0) X t1 t2 t3 Programming frame (Start bit) (Register- select) (Poll8) (Stop bit) Receiving mode Start-up mode IC_ACTIVE TSleep TStart-up Sleep mode

4839B–RKE–08/05 ATA5743 Figure 6-26. Data Interface The configuration registers are programmed serial ly via the bi-directional data line as demon- strated in Figure 6-25 on page 28 and Figure 6-26. To start programming, the microcontroller pulls the serial data line DATA to Low for the time period t1. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it em its 15 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the program- ming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the appropriate bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 15 bits are subsequently programmed this way. The time frame to program a bit is defined by t6. Bit 15 is followed by the equivalent time window t9. During this window, the equivalent acknowl- edge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register; in order to do this, the register must be programmed twice. Programming of a register is possible with the receiver in either sleep mode or in active mode. During programming, th e LNA, LO, low-pass filter IF-amp lifier, and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to “1”, it represents the OFF command to set the receiver back to polling mode immediately. For the length of the programming start pulse t1, the following convention should be considered:  t1(min) < t1 < 5632 × T Clk: t1(min) is the minimum specified value for the relevant BR_Range Similarly, programming the OFF command is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming the OFF command is not initiated and the reset marker (RM) is still present at pin DATA. This period is generally used to switch the rece iver to polling mode or to start the programming of a register. In reset condition, RM can not be cancelled by accident.  t1 > 7936 × T Clk Programming registers or the OFF command is initiated in any case. The registers OPMODE and LIMIT are set to the default values. RM is cancelled if present. Data_In Data_out Input - Interface DATA0 to 20 V0 V/5 V VX = 5 V to 20 V Rpup CL VS = 4.5 V to 5.5 V I/O Serial bi-directional data line ATA5743 Microcontroller Out1 microcontroller ID

4839B–RKE–08/05 ATA5743 This period is used if the connected microcontroller detected RM. If the receiver operates in default mode, this time period for t1 can generally be used. Note that the capacitive load at pin DATA is limited.

6.6.3 Data Interface

The data interface (see Figure 6-26 on page 29) is designed for automotive requirements. It can be connected via the pull-up resistor Rpup up to 20 V and is short-circuit protected. The applicable pull-up resistor R pup depends on the load capacity C L at pin DATA and the selected BR_range (see Table 6-12 ). More detailed information about the calculation of the maximum load capacity at pin DATA is given in the separate document “Application Note RKE Design Kit (U2741B, U3741BM)”. The internal circuitry with respect to the pin DATA is similar in ATA5743 and U3741BM. Figure 6-27. Application Circuit: fRF = 433.92 MHz without SAW Filter Table 6-12. Applicable Rpup BR_range Applicable R pup CL ≤ 1 nF B0 1.6 k Ω to 47 kΩ B1 1.6 k Ω to 22 kΩ B2 1.6 k Ω to 12 kΩ B3 1.6 k Ω to 5.6 kΩ CL ≤ 100 pF B0 1.6 k Ω to 470 kΩ B1 1.6 k Ω to 220 kΩ B2 1.6 k Ω to 120 kΩ B3 1.6 k Ω to 56 kΩ 10 nF 10% C13 C14 10 nF 10% 10% C8 150 pF np0 1 nF C9 C10 4.7 nF X7RX7R 10% 56 kΩ to 150 kΩ IC_ACTIVE POLLING /_ON SENS CDEM DATA DGND DATA_CLK MODEAVCC TEST MIXVCC XTO AGND LFGND LFVCC LF LNAGND NC LNA_IN DVCC X7R X7R C15150 pF np0 C11 10% ATA5743 12 pF5% np0C3 25 nH 33 nH 6.7643 MHz 15 pF 33 nF5% C12 X7R 10nF 10% 1.6 kΩ≥ V = 5 V to 20 VX POLLING/_ON DATA_CLK DATA IC_ACTIVE Sensitivity reduction 2.2 µF 20% COAX GND VS C16C17 100 pF np0 1.5 pF np0 L2 820Ω np0

4839B–RKE–08/05 ATA5743 Figure 6-30. Application Circuit: fRF = 315 MHz with SAW Filter 10 nF 10% C13 C14 10 nF 10% 10% C8 150 pF np0 1 nF C9 C10 4.7 nF X7RX7R 10% 56 kΩ to 150 kΩ IC_ACTIVE POLLING /_ON SENS CDEM DATA DGND DATA_CLK MODEAVCC TEST MIXVCC XTO AGND LFGND LFVCC LF LNAGND NC LNA_IN DVCC X7R X7R C15 150 pF np0 C11 10% ATA5743 15 pF5% np0C3 25nH 120 nF 4.906 MHz 27 pF 33 nF5% C12 X7R 10nF 10% 1.6 kΩ≥ V = 5 V to 20 VX POLLING/_ON DATA_CLK DATA IC_ACTIVE Sensitivity reduction 2.2 µF 20% COAX GND VS C16 100 pF np0 820 Ω np0 47 nH IN B3761 GND OUT2 1, 3, 4 6, 7, 8 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage V S 6V Power dissipation P tot 1000 mW Junction temperature T j 150 °C Storage temperature T stg -55 +125 °C Ambient temperature T amb -40 +105 °C Maximum input level, input matched to 50Ω Pin_max 10 dBm 8. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 100 K/W

4839B–RKE–08/05 ATA5743 Maximum Low period at pin DATA (see Figure 5-1 and Figure 6-10) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDATA_L_max 2152 1076 538 270 2152 1076 538 270 2120 1060 530 265 2120 1060 530 265 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk µs µs µs µs Delay to activate the start-up mode (see Figure 6-13) T OFF command at pin POLLING/_ON (see Figure 6-12) Ton2 16.6 16.4 8 × TClk µs Delay to activate the sleep mode (see Figure 6-12) Pulse on pin DATA at the end of a data stream (see Figure 6-22) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 TPulse 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 × TClk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs Configuration of the Receiver Frequency of the reset marker (see Figure 6-23)f RM 117.9 117.9 119.8 119.8 Hz Programming start pulse (see Figure 6-11 and Figure 6-25) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 3367 2277 1735 1464 16.43 11650 11650 11650 11650 3311 2243 1709 1442 16.18 11470 11470 11470 11470 1624 × TClk 1100 × TClk 838 × TClk 707 × TClk 7936 × TClk 5632 × TClk 5632 × TClk 5632 × TClk 5632 × TClk µs µs µs µs µms Programming delay period (see Figure 6-11 and Figure 6-25) t2 795 798 783 786 384.5 × TClk 385.5 × TClk µs Synchronization pulse t3 265 265 261 261 128 × TClk 128 × TClk µs Delay until the programming window starts t4 131 131 129 129 63.5 × TClk 63.5 × TClk µs Programming window t5 530 530 522 522 256 × TClk 256 × TClk µs 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) Parameter Test Conditions Symbol 6.76438 MHz Osc. (MODE: 1) 4.90625 MHz Osc. (MODE: 0) Variable Oscillator

4839B–RKE–08/05 ATA5743 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit Current consumption Sleep mode (XTO and polling logic active) ISoff 170 276 µA IC active (start-up-, bit check-, receiving mode) pin DATA = H FSK ASK ISon 7.5 7.1 9.1 8.7 mA mA LNA Mixer (Input Matched According to Figure 4-3) Third-order intercept point LNA /mixer/IF amplifier IIP3 -28 dBm LO spurious emission at RFIn Required according to I-ETS 300220 IS LORF -73 -57 dBm Noise figure LNA and mixer (DSB) NF 7 dB LNA_IN input impedance at 433.92 MHz at 315 MHz ZiLNA_IN 1.0 || 1.56 1.3 || 1.0 kΩ || pF kΩ || pF 1 dB compression point (LNA, mixer, IF amplifier) Referred to RFin IP1db -40 dBm Maximum input level BER ≤ 10-3 FSK mode ASK mode Pin_max -22 -20 dBm dBm Local Oscillator Operating frequency range VCO f VCO 299 449 MHz Phase noise VCO/LO fosc = 432.92 MHz At 1 MHz At 10 MHz L(fm) -93 -113 -90 -110 dBC/Hz dBC/Hz Spurs of the VCO At ±f XTO -55 -47 dBC VCO gain K VCO 190 MHz/V Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820Ω C9 = 4.7 nF C10 = 1 nF BLoop 100 kHz Capacitive load at pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self-polling. C LF_tot 10 nF XTO operating frequency XTO crystal frequency appropriate load capacitance must be connected to XTAL f XTAL = 6.764375 MHz (EU) fXTAL = 4.90625 MHz (US) fXTO -30 ppm f XTAL +30 ppm MHz Series resonance resistor of the crystal fXTO = 6.764 MHz fXTO = 4.906 MHz RS 150 220 Ω Ω Static capacitance at pin XTO to GND C0 6.5 pF

4839B–RKE–08/05 ATA5743 Sensitivity variation FSK for the full operating range including IF-filter compared to Tamb = 25°C, VS = 5V 300 kHz version fin = 433.92 MHz/ 315 MHz fIF = 0.89 MHz to 1.11 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +11 dB dB dB 600 kHz version f in = 433.92 MHz/ 315 MHz fIF = 0.85 MHz to 1.15 MHz fIF = 0.80 MHz to 1.20 MHz fIF = 0.74 MHz to 1.26 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +11 dB dB dB SNR to suppress inband noise signals. Noise signals may have any modulation scheme ASK mode FSK mode SNRASK SNRFSK dB dB Dynamic range RSSI ampl. DR RSSI 60 dB Lower cut-off frequency of the data filter CDEM = 33 nF fcu_DF 0.11 0.16 0.20 kHz Recommended CDEM for best performance BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF Edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 t ee_sig 270 156 1000 560 320 180 µs µs µs µs Upper cut-off frequency data filter Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 fu 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 kHz kHz kHz kHz Reduced sensitivity RSense connected from pin SENS to VS, input matched according to Figure 4-3 dBm (peak level) RSense = 56 kΩ, fin = 433.92 MHz, at BW = 300 kHz at BW = 600 kHz PRef_Red -71 -67 -76 -72 -81 -77 dBm dBm RSense = 100 kΩ, fin = 433.92 MHz, at BW = 300 kHz at BW = 600 kHz -80 -76 -85 -81 -90 -86 dBm dBm RSense = 56 kΩ, fin = 315 MHz, at BW = 300 kHz at BW = 600 kHz -72 -68 -77 -73 -82 -78 dBm dBm RSense = 100 kΩ, fin = 315 MHz, at BW = 300 kHz at BW = 600 kHz -81 -77 -86 -82 -91 -87 dBm dBm 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF

4839B–RKE–08/05 ATA5743 Reduced sensitivity variation over full operating range RSense = 56 kΩ RSense = 100 kΩ PRed = PRef_Red + ∆PRed ∆PRed dB dB Reduced sensitivity variation for different values of RSense Values relative to RSense = 56 kΩ R Sense = 56 kΩ RSense = 68 kΩ RSense = 82 kΩ RSense = 100 kΩ RSense = 120 kΩ RSense = 150 kΩ PRed = PRef_Red + ∆PRed ∆PRed ∆PRed ∆PRed ∆PRed ∆PRed ∆PRed -3.5 -6.0 -9.0 -11.0 -13.5 dB dB dB dB dB dB Threshold voltage for reset V ThRESET 1.95 2.8 3.75 V Digital Ports Data output - Saturation voltage Low - maximum voltage at pin DATA - quiescent current - short-circuit current - ambient temperature in case of permanent short-circuit Data input - Input voltage Low - Input voltage High I ol ≤ 12 mA Iol = 2 mA Voh = 20V Vol = 0.8V to 20V Voh = 0V to 20V Vol Vol Voh Iqu Iol_lim tamb_sc VIl Vich 0.65 × VS 0.35 0.08 0.8 0.3 0.35 × V S V V V µA mA V V DATA_CLK output - Saturation voltage Low - Saturation voltage High IDATA_CLK = 1 mA IDATA_CLK = -1 mA V ol Voh VS - 0.4 V 0.1 VS - 0.15 V 0.4 V V IC_ACTIVE output - Saturation voltage Low - Saturation voltage High IIC_ACTIVE = 1 mA IIC_ACTIVE = -1 mA Vol Voh VS-0.4 V 0.1 VS - 0.15 V 0.4 V V POLLING/_ON input - Low level input voltage - High level input voltage Receiving mode Polling mode VIl VIh 0.8 × VS 0.2 × VS V V MODE input - Low level input voltage - High level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 × VS 0.2 × VS V V TEST input - Low level input voltage Test input must always be set to Low V Il 0.2 × VS V 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4839B–RKE–08/05 ATA5743 11. Package Information 10. Ordering Information Extended Type Number Package Remarks ATA5743P3-TKQY SSO20 Taped and reeled, Pb-free, 300 kHz bandwidth ATA5743P3-TKSY SSO20 Tube, Pb-free, 300 kHz bandwidth ATA5743P6-TKQY SSO20 Taped and reeled, Pb-free, 600 kHz bandwidth ATA5743P6-TKSY SSO20 Tube, Pb-free, 600 kHz bandwidth ATA5743P3-TGQY SO20 Taped and reeled, Pb-free, 300 kHz bandwidth ATA5743P3-TGSY SO20 Tube, Pb-free, 300 kHz bandwidth ATA5743P6-TGQY SO20 Taped and reeled, Pb-free, 600 kHz bandwidth ATA5743P6-TGSY SO20 Tube, Pb-free, 600 kHz bandwidth

4839B–RKE–08/05 ATA5743 12. Revision History technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 11 0 Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4839B-RKE-08/05

• Put datasheet in a new template
• First page: Pb-free logo added
• Page 41: Ordering Information changed
• Page 42: Drawing SO20 added

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