ATA5723C

ATA5723C_14 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 44

Technical content

Features

• Frequency receiving range of (3 versions)
• f0 = 312.5MHz to 317.5MHz or
• f0 = 431.5MHz to 436.5MHz or
• f0 = 868MHz to 870MHz
• 30dB image rejection
• Receiving bandwidth
• BIF = 300kHz for 315MHz/433MHz version
• BIF = 600kHz for 868MHz version
• Fully integrated LC-VCO and PLL loop filter
• Very high sensitivity with power matched LNA
• Atmel® ATA5723C/ATA5724C:
• –107dBm, FSK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
• –113dBm, ASK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
• Atmel ATA5728C:
• –105dBm, FSK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
• –111dBm, ASK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
• High system IIP3
• –18dBm at 868MHz
• –23dBm at 433MHz
• –24dBm at 315MHz
• System 1-dB compression point
• –27.7dBm at 868MHz
• –32.7dBm at 433MHz
• –33.7dBm at 315MHz
• High large-signal capability at GSM band (blocking –33dBm at +10MHz, IIP3 = –24dBm at +20MHz)
• Logarithmic RSSI output
• XTO start-up with negative resistor of 1.5kΩ
• 5V to 20V automotive compatible data interface
• Data clock available for Manchester and bi-phase-coded signals
• Programmable digital noise suppression ATA5723C/ATA5724C/ATA5728C UHF ASK/FSK Receiver DATASHEET

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

• Low power consumption due to configurable polling
• Temperature range –40°C to +105°C
• ESD protection 2kV HBM, all pins
• Communication to microcontroller possible using a single bi-directional data line
• Low-cost solution due to high integration level with minimum external circuitry requirements
• Supply voltage range 4.5V to 5.5V Benefits
• Low BOM list due to high integration
• Use of low-cost 13MHz crystal
• Lowest average current consumption for application due to self polling feature
• Reuse of Atmel® ATA5743 software
• World-wide coverage with one PCB due to 3 versions are pin compatible

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 2. Pin Configuration Figure 2-1. Pinning SSO20 Table 2-1. Pin Description Pin Symbol Function

1 SENS Sensitivity-control resistor

2 IC_ACTIVE IC condition indicator: Low = sleep mode, High = active mode

3 CDEM Lower cut-off frequency data filter

4 AVCC Analog power supply

5 TEST 1 Test pin, during operation at GND

6 RSSI RSSI output

7 AGND Analog ground

8 LNAREF High-frequency reference node LNA and mixer

9 LNA_IN RF input

10 LNAGND DC ground LNA and mixer

11 TEST 2 Do not connect during operating

12 TEST 3 Test pin, during operation at GND

13 XTAL1 Crystal oscillator XTAL connection 1

14 XTAL2 Crystal oscillator XTAL connection 2

15 DVCC Digital power supply

16 MODE

Selecting 315MHz/other versions Low: 315MHz version (Atmel ATA5723C) High: 433MHz/868MHz versions (Atmel ATA5724C/ATA5728C)

17 DATA_CLK Bit clock of data stream

18 DGND Digital ground

19 POLLING/_ON Selects polling or receiving mode; Low: receiving mode, High: polling mode

20 DATA Data output/configuration input

LNA_IN LNAGND AGND LNAREF SENS IC_ACTIVE CDEM AVCC ATA5723C/ ATA5724C/ ATA5728C MODE DVCC TEST3 TEST2 XTAL2 XTAL1 DATA POLLING/_ON DGND DATA_CLK

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 4. Analog Signal Processing

4.1 IF Filter

The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is: fIF = 987kHz for the 315MHz and BIF = 300kHz (Atmel® ATA5723C) fIF = 987kHz for the 433.92MHz and BIF = 300kHz (Atmel ATA5724C) fIF = 947.9kHz for the 868.3MHz and BIF = 600kHz (Atmel ATA5728C) The nominal bandwidth is 300kHz for Atmel ATA5723C and Atmel ATA5724C and 600kHz for Atmel ATA5728C.

4.2 Limiting RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is ΔRRSSI = 60dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is approximately 60dB higher compared to the RF input signal at full sensitivity. The S/N ratio is not affected by the dynamic range of the RSSI amplifier in FSK mode because only the hard limited signal from a high-gain limiting amplifier is used by the demodulator. The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input power range PRef is –100dBm to –55dBm. Figure 4-1. RSSI Characteristics Atmel ATA5724C The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSens. RSens is connected between pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity. If RSens is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the pin SENS directly to GND to get the maximum sensitivity. If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSens, and the maximum sensitivity is defined by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is described and illustrated in Section 14. “Data Interface” on page 29. 5.5V -40°C 4.5V -40°C 5V 25°C 5.5V 25°C 5V 105°C 5.5V 105°C 4.5V 105°C 4.5V 85°C 5.5V 85°C 5V 85°C 4.5V 25°C 5V -40°C 3.5 2.5 1.5 -120 -110 -100 -90 PIN (dBm) V_RSSI (V) RSSI Characteristics

7ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 RSens can be connected to VS or GND using a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver does not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA disappears when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 4-2 “Steady L State Limited DATA Output Pattern” is issued at pin DATA to indicate that the receiver is still active (see Figure 13-2 on page 27). Figure 4-2. Steady L State Li mited DATA Output Pattern

4.3 FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set using the bit ASK/_FSK in the OPMODE register. Logic L sets the demodulator to FSK, applying H to ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also implements the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10dB the data signal can be detected properly. However, better values are found for many modulation schemes of the competing transmitter. The FSK demodulator is intended to be used for an FSK deviation of 10kHz≤ Δf ≤ 100kHz. The data signal in FSK mode can be detected if the S/N (ratio to suppress in-band noise signals) exceeds about 2dB. This value is valid for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its pass-band can be adopted to the characteristics of the data signal. The data filter consists of a 1st order high-pass and a 2nd order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: In self-polling mode the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the low-pass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to Section 11. “Configuring the Receiver” on page 22). The BR_Range must be set in accordance to the baud-rate used. The Atmel® ATA5723C/ATA5724C/ATA5728C is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver. tDATA_L_maxtDATA_min DATA fcu_DF 1

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 5. Receiving Characteristics The Atmel® RF receiver ATA5723C/ATA5724C/ATA5728C can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in Figure 5-1. This example relates to ASK mode. FSK mode exhibits a similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3dB must be considered, but the overall selectivity is much better. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated, to be the sum of the deviation of the crystal and the XTO deviation of the Atmel ATA5723C/ATA5724C/ATA5728C. Low-cost crystals are specified to be within ±90ppm over tolerance, temperature, and aging. The XTO deviation of the Atmel ATA5723C/ATA5724C/ATA5728C is an additional deviation due to the XTO circuit. This deviation is specified to be ±10ppm worst case for a crystal with CM = 7fF. If a crystal of ±90ppm is used, the total deviation is ±100ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Figure 5-1. Narrow Band Receiving Frequency Response Atmel ATA5724C 6. Polling Circuit and Control Logic The receiver is designed to consume less than 1mA while being sensitive to signals from a corresponding transmitter. This is achieved using the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit- check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. The receiver is very flexible with regards to the number of connection wires to the microcontroller. It can be either operated by a single bi-directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional ports. -10 -20 -30 -40 -50 -60 -70 (dB) 5.5V -40°C 4.5V -40°C 5V 25°C 5.5V 25°C 4.5V 105°C 5.5V 105°C 5V 105°C 4.5V 25°C 5V -40°C 430 431 432 433 (MHz) Image Rejection versus RF Frequency 434 435 436 437 438

9ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 7. Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divide by 28 or 30 circuit. According to Section 3. “RF Front-end” on page 5, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). The basic clock cycle for Atmel® ATA5724C and Atmel ATA5728C is TClk 28/fXTO giving TClk =3 0 / fREF giving TClk = 2.0382µs for fRF = 315MHz. TClk controls the following application-relevant parameters:

• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0) Most applications are dominated by three transmission frequencies: fTransmit = 315MHz is mainly used in USA, fTransmit = 868.3MHz and 433.92MHz in Europe. All timings are based on TClk. For the aforementioned frequencies, TClk is given as:
• Application 315MHz band (fXTO = 14.71875MHz, fLO = 314.13MHz, TClk = 2.0382µs)
• Application 868.3MHz band (fXTO = 13.55234MHz, fLO = 867.35MHz, TClk = 2.066µs)
• Application 433.92MHz band (fXTO = 13.52875MHz, fLO = 432.93MHz, TClk = 2.0696µs) For calculation of TClk for applications using other frequency bands, see table in Section 18. “Electrical Characteristics Atmel ATA5724C, ATA5728C” on page 34. The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range), which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas: BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 8. Polling Mode According to Figure 8-1 on page 11, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS =I Soff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit-by-bit and compared with a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBit-check. This period varies according to each check as it is a statistical process. An average value for TBitcheck is given in the electrical characteristics. During TStartup and TBit-check, the current consumption is IS =I Son. The condition of the receiver is indicated on pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters TSleep, TStartup, TBit-check and the start-up time of a connected microcontroller, TStart_microcontroller. Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. The following formula indicates how to calculate the preburst length. T Preburst ≥ TSleep + TStartup + TBit-check + TStart_microcontroller

8.1 Sleep Mode

The length of period TSleep is defined by the 5-bit word sleep of the OPMODE register, the extension factor XSleep (according to Table 11-8 on page 24), and the basic clock cycle TClk. It is calculated to be: TSleep =S l e e p× XSleep × 1024 × TClk The maximum value of TSleep is about 60ms if XSleep is set to 1. The time resolution is about 2ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to “1”. Setting the configuration word sleep to its maximal value puts the receiver into a permanent sleep mode. The receiver remains in this state until another value for Sleep is programmed into the OPMODE register. This is particularly useful when several devices share a single data line. (It can also be used for microcontroller polling: using pin POLLING/_ON, the receiver can be switched on and off.) ISpoll ISoff TSleep ISon TStartup TBit-check+()×+×

11ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 Figure 8-1. Polling Mode Flow Chart

8.2 Bit-check Mode

In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum number of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable. Bit-check Mode: The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE = > high TBit-check IS = ISon Start-up Mode: The signal processing circuits are enabled. After the start-up time (T Startup) all circuits are in stable condition and ready to receive. Output level on Pin IC_ACTIVE = > high TStartup IS = ISon Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via Pin DATA or Polling/_ON. Output level on Pin IC_ACTIVE = > high I S = ISon Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on Pin IC_ACTIVE = > low T Sleep = Sleep x XSleep x 1024 x TClk IS = ISoff Bit Check OK ? 5-bit word defined by Sleep 0 to Sleep 4 in OPMODE register Sleep: Is defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud 0 and Baud 1 in the OPMODE register. T Startup: Basic clock cycle defined by f XTO and Pin MODE TClk: If the bit check fails, the average time period for that check depends on the selected baud-rate range and on T Clk. The baud-rate range is defined by Baud 0 and Baud 1 in the OPMODE register. If the bit check is ok, T Bit-check depends on the number of bits to be checked (NBit-check) and on the data rate used. Depends on the result of the bit checkTBit-check: Extension factor defined by XSleepStd according to Table 11-8 XSleep: OFF Command YES NO

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

8.3 Configuring the Bit Check

Assuming a modulation scheme that contains two edges per bit, two time frame checks verify one bit. This is valid for Manchester, bi-phase, and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6, or 9 bits using the variable NBit-check in the OPMODE register. This implies 0, 6, 12, and 18 edge-to-edge checks respectively. If NBit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 8-2 shows an example where three bits are tested successfully and the data signal is transferred to pin DATA. Figure 8-2. Timing Diagram for Complete Successful Bit Check According to Figure 8-3, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check limit TLim_max, the check continues. If tee is smaller than TLim_min or tee exceeds TLim_max, the bit check is terminated and the receiver switches to sleep mode. Figure 8-3. Valid Time Window for Bit Check For best noise immunity using a low span between TLim_min and TLim_max is recommended. This is achieved using a fixed is suitable for this. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±30% regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. The bit-check limits are determined by means of the formula below. TLim_min = Lim_min × TXClk TLim_max = (Lim_max – 1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the Section 8.6 “Digital Signal Processing” on page 14. The lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (NBit-check) to prevent switching to receiving mode due to noise. IC_ACTIVE Data_out (DATA) Dem_out Bit Check TBit-check Start-up Mode (Number of checked Bits: 3) Bit Check ok 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit1/2 Bit1/2 Bit Start-check Mode Receiving Mode TStart-up 1/fSig tee TLim_max TLim_min Dem_out

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

8.4 Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a lower value for TBit-check resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in a longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst.

8.5 Receiving Mode

If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. According to Figure 8-2 on page 12, the internal data signal is switched to pin DATA in that case, and the data clock is available after the start bit has been detected (see Figure 9-1 on page 17). A connected microcontroller can be woken up by the negative edge at pin DATA or by the data clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly.

8.6 Digital Signal Processing

The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 8-7 illustrates how Dem_out is synchronized by the extended clock cycle T XClk. This clock is also used for the bit-check counter. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee ≥TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay low is limited to TDATA_L_max. This function is employed to ensure a finite response time in programming or switching off the receiver via pin DATA. TDATA_L_max is therefore longer than the maximum time period indicated by the transmitter data stream. Figure 8-9 on page 15 gives an example where Dem_out remains Low after the receiver has switched to receiving mode. Figure 8-7. Synchronization of the Demodulator Output Figure 8-8. Debouncing of the Demodulator Output Data_out (DATA) Clock bit-check counter Dem_out TXClk tee Data_out (DATA) Dem_out teeteetee tDATA_min tDATA_min tDATA_min

15ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 Figure 8-9. Steady L State Limited DATA Output Pattern after Transmission After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise pulses appear at pin DATA (see Section 10. “Digital Noise Suppression” on page 20). The edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than TDATA_min.

8.7 Switching the Receiver Back to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON. When using pin DATA, this pin must be pulled to low by the connected microcontroller for the period t1. Figure 8-10 on page 15 illustrates the timing of the OFF command (see Figure 13-2 on page 27). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not limited; however, exceeding the specified value to prevent erasing the reset marker is not recommended. Note also that an internal reset for the OPMODE and the LIMIT register is generated if t1 exceeds the specified values. This item is explained in more detail in the Section 11. “Configuring the Receiver” on page 22. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time TSleep elapses after the OFF command. Note that the capacitive load at pin DATA is limited (see Section 14. “Data Interface” on page 29). Figure 8-10. Timing Diagram of the OFF Command using Pin DATA IC_ACTIVE Data_out (DATA) Dem_out Bit Check tDATA_L_maxtDATA_min Receiving ModeStart-up Mode Bit-check Mode IC_ACTIVE Serial bi-directional Data Line Out1 (Microcontroller) Data_out (DATA) TSleep TStart-up t5t3t2t1 t10 Bit 1 ("1") (Start Bit) OFF-command X X Receiving Mode Sleep Mode Start-up Mode

17ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 9. Data Clock The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and bi-phase coded signals.

9.1 Generation of the Data Clock

After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at pin DATA. In receiving mode, the data clock control logic (Manchester/bi-phase demodulator) is active and examines the incoming data stream. This is done, as with the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page 17, only two distances between two edges in Manchester and bi-phase coded signals are valid (T and 2T). The limits for T are the same as used with the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see Table 11-10 on page 25 and Table 11-11 on page 25). The limits for 2T are calculated as follows: Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2 Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2 (If the result for ‘Lim_min_2T’ or ‘Lim_max_2T’ is not an integer value, it is rounded up.) The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the delay t Delay after the edge on pin DATA (see Figure 9-1 on page 17). If the data clock control logic detects a timing or logical error (Manchester code violation), as illustrated in Figure 9-2 on page 18 and Figure 9-3 on page 18, it stops the output of the data clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see Figure 9-4 on page 18). Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recommended. If the bit check is set to 0 or the receiver is set to receiving mode using the pin POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit). Note that for bi-phase-coded signals, the data clock is issued at the end of the bit. Figure 9-1. Timing Diagram of the Data Clock Data_out (DATA) DATA_CLK Dem_out tDelay DataPreburst Start bitBit-check Mode Receiving Mode, data clock control logic active Bit Check ok T '1''1''1' tP_Data_Clk

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 10. Digital Noise Suppression After a data transmission, digital noise appears on the data output (see Figure 10-1). To prevent digital noise keeping the connected microcontroller busy, it can be suppressed in two different ways:

• Automatic noise suppression
• Controlled noise suppression by the microcontroller

10.1 Automatic Noise Suppression

The receiver changes to bit-check mode at the end of a valid data stream if the bit Noise_Disable (Table 11-9 on page 24) in the OPMODE register is set to 1 (default). The digital noise is suppressed, and the level at pin DATA is high. The receiver changes back to receiving mode, if the bit check was successful. This method of noise suppression is recommended if the data stream is Manchester or bi-phase coded and is active after power on. Figure 10-3 illustrates the behavior of the data output at the end of a data stream. If the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud- rate range. Figure 10-1. Output of Digital Noise at the End of the Data Stream Figure 10-2. Automatic Noise Suppression Figure 10-3. Occurrence of a Pulse at the End of the Data Stream DATA_CLK Data_out (DATA) DataPreburst Receiving Mode, data clock control logic active Receiving Mode, data clock control logic active Bit-check mode Bit Check ok Receiving Mode, bit check active Receiving Mode, bit check active Data Digital Noise Digital NoiseDigital NoisePreburst Bit Check ok DATA_CLK Data_out (DATA) DataPreburst Receiving Mode, data clock control logic active Receiving Mode, data clock control logic active Bit-check Mode Bit-check Mode Bit-check Mode Bit Check ok DataPreburst Bit Check ok Data_out (DATA) DATA_CLK Dem_out '1' '1' Digital NoiseData Stream Receiving Mode, data clock control logic active Bit-check Mode '1' tee < TLim_min or TLim_max < tee < tLim_min_2T or tee > TLim_max_2T Timing error Tpulse Tee

21ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

10.2 Controlled Noise Suppression by the Microcontroller

Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see Table 11-9 on page 24) in the OPMODE register is set to 0. To suppress the noise, the pin POLLING/_ON must be set to low. The receiver remains in receiving mode. The OFF command then causes a change to start-up mode. The programmed sleep time (see Table 11-7 on page 24) is not executed because the level at pin POLLING/_ON is low; however, the bit check is active in this case. The OFF command also activates the bit check if the pin POLLING/_ON is held to low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the pin POLLING/_ON must be set to high. This way of suppressing the noise is recommended if the data stream is not Manchester or bi-phase coded. Figure 10-4. Controlled Noise Suppression POLLING/_ON (DATA_CLK) Serial bi-directional Data Line DataPreburst Receiving ModeReceiving Mode Start-up Mode Sleep Mode Bit-check Mode Bit-check Mode Bit Check ok Data Digital NoiseDigital NoisePreburst OFF-command Bit Check ok

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 11. Configuring the Receiver The Atmel® ATA5723C/ATA5724C/ATA5728C receiver is configured using two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register content has changed due to a voltage drop, this condition is indicated by a the output pattern called reset marker (RM). If this occurs, the receiver must be reprogrammed. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 11-3 on page 22 shows the structure of the registers. According to Table 11-1, bit 1 defines whether the receiver is set back to polling mode using the OFF command (see “Receiving Mode” on page 14) or whether it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. For high programming reliability, bit 15 (Stop bit), at the end of the programming operation, must be set to 0. Table 11-1. Effect of Bit 1 and Bi t 2 on Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 11-2. Effect of Bit 15 on Programming the Register Bit 15 Action

0 The values are written into the register (OPMODE or LIMIT)

1 The values are not written into the register

Table 11-3. Effect of the Configur ation Words within the Registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF command – OPMODE register – 0 1 BR_Range NBit-check Modu- lation Sleep XSleep Noise Suppression Baud1 Baud0 BitChk1 BitChk0 ASK/ _FSK Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 XSleepStd Noise_ Disable Default values of Bit 3...14 0 0 0 1 0 0 0 1 1 0 0 1 – – LIMIT register – 0 0 Lim_min Lim_max – Lim_ min5 Lim_ min4 Lim_ min3 Lim_ min2 Lim_ min1 Lim_ min0 Lim_ max5 Lim_ max4 Lim_ max3 Lim_ max2 Lim_ max1 Lim_ max0 0 Default values of Bit 3...14 0 1 0 1 0 1 1 0 1 0 0 1 –

23ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 The following tables illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits TLim_min and TLim_max as shown in Table 11-10 on page 25 and Table 11-11 on page 25. Table 11-4. Effect of the configuration word BR_Range BR_Range Baud-rate Range/Extension Factor for Bit-check Limits (XLim)Baud1 Baud0 0 0 BR_Range0 (BR_Range0 = 1.0Kbit/s to 1.8Kbit/s) XLim = 8 (default) 0 1 BR_Range1 (BR_Range1 = 1.8Kbit/s to 3.2Kbit/s) XLim = 4 1 0 BR_Range2 (BR_Range2 = 3.2Kbit/s to 5.6Kbit/s) XLim = 2 1 1 BR_Range3 (BR_Range3 = 5.6Kbit/s to 10Kbit/s) XLim = 1 Table 11-5. Effect of the Configuration word N Bit-check NBit-check Number of Bits to be CheckedBitChk1 BitChk0 0 0 0 0 1 3 (default) 1 0 6 1 1 9 Table 11-6. Effect of the Co nfiguration Bit Modulation Modulation Selected Modulation ASK/_FSK –

0 FSK (default)

1 ASK

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 Table 11-7. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 0 0 0 0 0 0 (Receiver polls continuously until a valid signal occurs) 0 0 0 0 1 If XSleep = 1 TSleep = 2.11ms for fRF = 868.3MHz, TSleep = 2.12ms for fRF = 433.92MHz TSleep = 2.08ms for fRF = 315MHz 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 1 0 If XSleep = 1 TSleep = 12.69ms for fRF = 868.3MHz, TSleep = 12.71ms for fRF = 433.92MHz TSleep = 12.52ms for fRF = 315MHz 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 (permanent sleep mode) Table 11-8. Effect of the Configuration Bit XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk)XSleepStd 0 1 (default) 1 8 Table 11-9. Effect of the Configuration Bit Noise Suppression Noise Suppression Suppression of the Digital Noise at Pin DATANoise_Disable

0 Noise suppression is inactive

1 Noise suppression is active (default)

25ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 Note: 1. Lim_min is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 17). Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 17). Table 11-10. Effect of the Configuration Word Lim_min Lim_min(1) (Lim_min < 10 is not Applicable) Lower Limit Value for Bit Check Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 (TLim_min = Lim_min × XLim × TClk) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 0 1 0 1 0 1 21 (default, BR_Range0) (TLim_min = 347µs for fRF = 868.3MHz TLim_min = 347µs for fRF = 433.92MHz TLim_min = 342µs for fRF = 315MHz) 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Table 11-11. Effect of the Configuration Word Lim_max Lim_max(1) (Lim_max < 12 is not applicable) Upper Limit Value for Bit Check Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (TLim_max = (Lim_max – 1) × XLim × TClk) 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 1 0 1 0 0 1 41 (default, BR_Range0) (TLim_max = 661µs for fRF = 868.3MHz TLim_max = 662µs for fRF = 433.92MHz TLim_max = 652µs for fRF = 315MHz) 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 12. Conservation of the Register Information The Atmel® ATA5723C/ATA5724C uses an integrated power-on reset and brown-out detection circuitry as a mechanism to preserve the RAM register information. According to Figure 12-1, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. The POR is cancelled after the minimum reset period tRst when VS exceeds VThReset. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency fRM at a 50% duty-cycle. RM can be cancelled using a low pulse t1 at pin DATA. The RM has the following characteristics:

• fRM is lower than the lowest feasible frequency of a data signal. Due to this, RM cannot be misinterpreted by the connected microcontroller.
• If the receiver is set back to polling mode using pin DATA, RM cannot be cancelled accidentally if t1 is applied as described in the proposal in Section 13. “Programming the Configuration Register” on page 27. Using this conservation mechanism, the receiver cannot lose its register information without communicating this condition using the reset marker RM. Figure 12-1. Generation of the Power-on Reset POR Data_out (DATA) X tRst VThresetVS 1/fRM

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. A register can be programmed when the receiver is in both sleep-mode and active mode. During programming, the LNA, LO, low-pass filter, IF-amplifier, and the FSK/MSK demodulator are disabled. The t1 pulse is used to start the programming or to switch the receiver back to polling mode (OFF command). (The receiver is switched back to polling mode with the OFF command if bit 1 is set to “1”.) The following convention should be considered for the length of the programming start pulse t1: Using a t1 value of t1 (min) < t1 < 5632 TClk (where t1 (min) is the minimum specified value for the relevant BR_Range) when the receiver is active i.e., not in reset mode initiates the programming or OFF command. However, if this t1 value is used when the receiver is in reset mode, programming or OFF command is NOT initiated and RM remains present at pin DATA. Note, the RM cannot be deleted when using this t1 value. Using a t1 value of t1 > 7936× TClk, programming or OFF command is initiated when the receiver is in both reset mode and active mode. The registers PMODE and LIMIT are set to the default values and the RM is deleted, if present. This t1 values can be used if the connected microcontroller detects an RM. Additionally, this t1 value can generally be used if the receiver operates in default mode. Note that the capacitive load at pin DATA is limited.

29ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 14. Data Interface The data interface (see Figure 13-2 on page 27) is designed for automotive requirements. It can be connected using the pull- up resistor Rpup up to 20V and is short-circuit-protected. The applicable pull-up resistor Rpup depends on the load capacity CL at pin DATA and the selected BR_range (see Table 14-1). Figure 14-1. Application Circuit: fRF = 315MHz(1), 433.92MHz or without SAW Filter Note: For 315MHz application pin MODE must be connected to GND. Table 14-1. Applicable R pup - BR_range Applicable Rpup CL ≤ 1nF B0 1.6kΩ to 47kΩ B1 1.6kΩ to 22kΩ B2 1.6kΩ to 12kΩ B3 1.6kΩ to 5.6kΩ CL ≤ 100pF B0 1.6kΩ to 470kΩ B1 1.6kΩ to 220kΩ B2 1.6kΩ to 120kΩ B3 1.6kΩ to 56kΩ Table 14-2. Input Matching to 50Ω RF Frequency (MHz) LNA Matching Crystal Frequency fXTAL (MHz)C16 (pF) C17 (pF) L1 (nH) 315 Not connected 3 39 14.71875 433.92 Not connected 3 20 13.52875 868.3 1 3 6.8 13.55234 LNAGND LNA_IN LNAREF AGND RSSI TEST1 AVCC CDEM IC_ACTIVE SENS TEST2 TEST3 XTAL1 XTAL2 DVCC MODE DATA_CLK DGND POLLING/_ON DATA F crystal CL2 GND C16 C17RF_IN VS 1.6kΩ 56kΩ to 150kΩ CL1 DATA_CLK Sensitivity Reduction POLLING/_ON DATA C12 10nF 10% C13 10nF 10% C14 39nF 4.7μF 10% VX = 5V to 20V IC_ACTIVE RSSI ATA5723C ATA5724C ATA5728C

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 15. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage VS 6 V Power dissipation Ptot 1000 mW Junction temperature Tj 150 °C Storage temperature Tstg –55 +125 °C Ambient temperature Tamb –40 +105 °C Maximum input level, input matched to 50Ω Pin_max 10 dBm 16. Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 100 K/W

31ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 17. Electrical Characteristics Atmel ATA5723C All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 315MHz 14.71875MHz Oscillator Variable Oscillator

1 Basic Clock Cycle of the Digital Circuitry

1.1 Basic clock

TClk 2.0382 2.0382 30/fXTO 30/fXTO µs A 1.2 Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 TXClk 16.3057 8.1528 4.0764 2.0382 16.3057 8.1528 4.0764 2.0382 8 × TClk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs A

2 Polling Mode

2.1 Sleep time (see Figure 8-1, Figure 8-10 and Figure 13-1) Sleep and XSleep are defined in the OPMODE register TSleep Sleep × XSleep × 1024 × 2.0382 Sleep × XSleep × 1024 × 2.0382 Sleep × XSleep × 1024 × TClk Sleep × XSleep × 1024 × TClk ms A 2.2 Start-up time (see Figure 8-1 and Figure 8-4) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TStartup 1827 1044 1044 653 1827 1044 1044 653 896.5 512.5 512.5 320.5 × T Clk 896.5 512.5 512.5 320.5 × T Clk µs µs µs µs µs A 2.3 Time for bit check (see Figure 8-1 Average bit- check time while polling, no RF applied (see Figure 8-5 and Figure 8-6) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TBit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms C 2.4 Time for bit check (see Figure 8-1 Bit-check time for a valid input signal f Sig (see Figure 8-5) NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 TBit-check 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TXClk 3.5/fSig 6.5/fSig 9.5/fSig 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms C

3 Receiving Mode

3.1 Intermediate

fIF 987 fIF = fLO/318 kHz A

3.2 Baud-rate

BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 µs/TClk BR_Range1 × 2 µs/TClk BR_Range2 × 2 µs/TClk BR_Range3 × 2 µs/TClk Kbit/s Kbit/s Kbit/s Kbit/s A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

33ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

4 Configuration of the Receiver (see Figure 12-1 and Figure 13-1)

4.1 Frequency of the reset marker Frequency is stable within 50ms after POR fRM 119.78 119.78 (4096 × TClk) (4096 × TClk) Hz A

4.2 Programming

BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 3310 2242 1708 1441 16175 11479 11479 11479 11479 1624 × TClk 1100 × TClk 838 × TClk 707 × TClk 7936 × TClk 5632 × TClk 5632 × TClk 5632 × TClk 5632 × TClk µs µs µs µs µs A

4.3 Programming

t2 783 785 384.5 × TClk 385.5 × TClk µs A

4.4 Synchroniza-

t3 261 261 128 × TClk 128 × TClk µs A 4.5 Delay until of the program window starts t4 129 129 63.5 × TClk 63.5 × TClk µs A

4.6 Programming

window t5 522 522 256 × TClk 256 × TClk µs A

4.7 Time frame

of a bit t6 1044 1044 512 × TClk 512 × TClk µs A

4.8 Programming

pulse t7 130.5 522 64 × TClk 256 × TClk µs C 4.9 Equivalent acknowledge pulse: E_Ack t8 261 261 128 × TClk 128 × TClk µs A

4.10 Equivalent

time window t9 526 526 258 × TClk 258 × TClk µs A 4.11 OFF-bit programming window t10 916 916 449.5 × TClk 449.5 × TClk µs A

5 Data Clock (see Figure 9-1 and Figure 9-6)

5.1 Minimum delay time between edge at DATA and DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDelay2 16.3057 8.1528 4.0764 2.0382 1 × TXClk 1 × TXClk 1 × TXClk 1 × TXClk µs µs µs µs C 5.2 Pulse width of negative pulse at pin DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tP_DATA_CLK 65.2 32.6 16.3 8.15 65.2 32.6 16.3 8.15 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk µs µs µs µs A 17. Electrical Characteristics Atmel ATA5723C (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 315MHz 14.71875MHz Oscillator Variable Oscillator *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 18. Electrical Characteristic s Atmel ATA5724C, ATA5728C All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92MHz and f0 = 868.3MHz unless otherwise specified (for typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 433.92MHz 13.52875MHz Oscillator fRF = 868.3MHz, 13.55234MHz Oscillator Variable Oscillator

6 Basic Clock Cycle of the Digital Circuitry

6.1 Basic clock

TClk 2.0696 2.0696 2.066 2.066 28/fXTO 28/fXTO µs A 6.2 Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 TXClk 16.557 8.278 4.139 2.069 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 16.528 8.264 4.132 2.066 8 × TClk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs A

7 Polling Mode

7.1 Sleep time (see Figure 8-1, Figure 8-10 and Figure 13-1) Sleep and XSleep are defined in the OPMODE register TSleep Sleep × XSleep × 1024 × 2.0696 Sleep × XSleep × 1024 × 2.0696 Sleep × XSleep × 1024 × 2.066 Sleep × XSleep × 1024 × 2.066 Sleep × XSleep × 1024 × TClk Sleep × XSleep × 1024 × TClk ms A 7.2 Start-up time (see Figure 8-1 and Figure 8-4) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TStartup 1855 1060 1060 663 1855 1060 1060 663 1852 1058 1058 662 1852 1058 1058 662 896.5 512.5 512.5 320.5 × T Clk 896.5 512.5 512.5 320.5 × T Clk µs µs µs µs µs A 7.3 Time for bit check (see Figure 8-1 Average bit- check time while polling, no RF applied (see Figure 8- 8 on page 14 and Figure 8-9 on page 15) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TBit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms C 7.4 Time for bit check (see Figure 8-1 Bit-check time for a valid input signal f Sig (see Figure 8- 5 on page 13) NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 TBit-check 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TXClk 3.5/fSig 6.5/fSig 9.5/fSig 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TXClk 3.5/fSig 6.5/fSig 9.5/fSig 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms C

8 Receiving Mode

8.1 Intermediate

fIF 987 947.9 fIF = fLO/438 for the 433.92MHz band (Atmel ATA5724C) fIF = fLO/915 for the 868.3MHz band (Atmel ATA5728C) kHz A

8.2 Baud-rate

BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Rang e 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 µs/TClk BR_Range1 × 2 µs/TClk BR_Range2 × 2 µs/TClk BR_Range3 × 2 µs/TClk Kbit/s Kbit/s Kbit/s Kbit/s A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

9 Configuration of the Receiver (see Figure 12-1 and Figure 13-1)

9.1 Frequency of the reset marker Frequency is stable within 50ms after POR fRM 117.9 117.9 118.2 118.2 (4096 × TClk) (4096 × TClk) Hz A

9.2 Programming

BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 3361 2276 1734 1463 16425 11656 11656 11656 11656 3355 2272 1731 1460 11636 11636 11636 11636 1624 × TClk 1100 × TClk 838 × TClk 707 × TClk 7936 × TClk 5632 × TClk 5632 × TClk 5632 × TClk 5632 × TClk µs µs µs µs µs A

9.3 Programming

t2 796 798 794 796 384.5 × TClk 385.5 × TClk µs A

9.4 Synchroniza-

t3 265 265 264 264 128 × TClk 128 × TClk µs A 9.5 Delay until of the program window starts t4 131 131 131 131 63.5 × TClk 63.5 × TClk µs A

9.6 Programming

window t5 530 530 529 529 256 × TClk 256 × TClk µs A

9.7 Time frame

of a bit t6 1060 1060 1058 1058 512 × TClk 512 × TClk µs A

9.8 Programming

pulse t7 132 530 132 529 64 × TClk 256 × TClk µs C 9.9 Equivalent acknowledge pulse: E_Ack t8 265 265 264 264 128 × TClk 128 × TClk µs A

9.10 Equivalent

time window t9 534 534 533 533 258 × TClk 258 × TClk µs A 9.11 OFF-bit programming window t10 930 930 929 929 449.5 × TClk 449.5 × TClk µs A

10 Data Clock (see Figure 9-1 and Figure 9-6)

10.1 Minimum delay time between edge at DATA and DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDelay2 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 1 × TXClk 1 × TXClk 1 × TXClk 1 × TXClk µs µs µs µs C 10.2 Pulse width of negative pulse at pin DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tP_DATA_CLK 66.2 33.1 16.5 8.3 62.2 33.1 16.5 8.3 66.1 33.0 16.5 8.25 66.1 33.0 16.5 8.25 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk µs µs µs µs A 18. Electrical Characteristics Atme l ATA5724C, ATA5728C (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92MHz and f0 = 868.3MHz unless otherwise specified (for typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 433.92MHz 13.52875MHz Oscillator fRF = 868.3MHz, 13.55234MHz Oscillator Variable Oscillator *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

37ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 19. Electrical Characterist ics Atmel ATA5723C/24C/28C All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type*

11 Current Consumption

11.1 Current consumption

(XTO and polling logic active) ISoff 170 290 µA A IC active (start-up-, bit-check-, receiving mode) Pin DATA = H FSK ASK ISon 8.5 8.0 11.0 10.4 mA mA A 12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to Figure 14-1 on page 29 Referred to RFIN)

12.1 Third-order intercept point

IIP3 –18 –23 –24 dBm C

12.2 LO spurious emission Required according to I-ETS 300220 ISLORF –70 –57 dBm A

12.3 System noise figure With power matching |S11| < –10dB NF 5 dB B

12.4 LNA_IN input impedance

At 868.3MHz AT 433.92MHz At 315MHz ZiLNA_IN (14.15 – j73.53) (19.3 – j113.3) (26.97 – j158.7) Ω Ω Ω C 12.5 1 dB compression point At 868.3MHz AT 433.92MHz At 315MHz IP1db –27.7 –32.7 –33.7 dBm C

12.6 Image rejection Within the complete image band 20 30 dB A

12.7 Maximum input level

BER ≤ 10-3, FSK mode ASK mode Pin_max –10 –10 dBm dBm C

13 Local Oscillator

13.1 Operating frequency range

431.5 312.5 870 436.5 317.5 MHz MHz MHz A

13.2 Phase noise local oscillator

fosc = 868.3MHz at 10MHz fosc = 433.92MHz at 10MHz fosc = 315MHz at 10MHz L (fm) –140 –143 –143 –130 –133 –133 dBC/Hz B

13.3 Spurious of the VCO At ±fXTO –55 –45 dBC B

13.4 XTO pulling

XTO pulling, appropriate load capacitance must be connected to XTAL, crystal CL1 and CL2 f XTAL = 14.71875MHz (315MHz band) fXTAL = 13.52875MHz (433MHz band) fXTAL = 13.55234MHz (868MHz band) fXTO –10ppm fXTAL +10ppm MHz B

13.5 Series resonance resistor of

Parameter of the supplied crystal RS 120 Ω B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

13.6 Static capacitance at pin

Parameter of the supplied crystal and board parasitics CL1 –5% 18 +5% pF B

13.7 Static capacitance at pin

Parameter of the supplied crystal and board parasitics CL2 –5% 18 +5% pF B

13.8 Crystal series resistor Rm at

C0 < 1.8pF, CL =9 p F fXTAL = 14.71875MHz 1.5 kΩ B C0 < 2.0pF, CL =9 p F fXTAL = 13.52875MHz fXTAL = 13.55234MHz 1.5 kΩ B

14 Analog Signal Processing (Input Matched According to Figure 14-1 on page 29 Referred to RFIN)

14.1 Input sensitivity ASK 300kHz IF Filter (Atmel ATA5723C/ATA5724C) ASK (level of carrier) BER ≤ 10 -3, 100% Mod fin = 315MHz/433.92MHz VS = 5V, Tamb = 25°C fIF = 987kHz PRef_ASKBR_Range0 –111 –113 –115 dBm B BR_Range1 –109.5 –111.5 –113.5 dBm B BR_Range2 –109 –111 –113 dBm B BR_Range3 –107 –109 –111 dBm B 14.2 Input sensitivity ASK 600kHz IF Filter (Atmel ATA5728C) ASK (level of carrier) BER ≤ 10-3, 100% Mod fin = 868.3MHz VS = 5V, Tamb = 25°C fIF = 948kHz PRef_ASKBR_Range0 –109 –111 –113 dBm B BR_Range1 –107.5 –109.5 –111.5 dBm B BR_Range2 –107 –109 –111 dBm B BR_Range3 –105 –107 –109 dBm B 14.3 Sensitivity variation ASK for the full operating range compared to Tamb = 25°C, VS = 5V (Atmel ATA5723C/ ATA5724C/ATA5728C) 300kHz and 600kHz fin = 315MHz/433.92MHz/868.3MHz PASK = PRef_ASK + ΔPRef ΔPRef +2.5 –1.5 dB B 14.4 Sensitivity variation ASK for full operating range including IF filter compared to T amb = 25°C, VS = 5V 300kHz version (Atmel ATA5723C/ATA5724C) fin = 315MHz/433.92MHz fIF = 987kHz fIF = –110kHz to +110kHz fIF = –140kHz to +140kHz PASK = PRef_ASK + ΔPRef ΔPRef +5.5 +7.5 –1.5 –1.5 dB dB B 600kHz version (Atmel ATA5728C) fin = 868.3MHz fIF = 948kHz fIF = –210kHz to +210kHz fIF = –270kHz to +270kHz PASK = PRef_ASK + ΔPRef ΔPRef +5.5 +7.5 –1.5 –1.5 dB dB B 19. Electrical Characteristics At mel ATA5723C/24C/28C (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

39ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 14.5 Input sensitivity FSK 300kHz IF filter (Atmel ATA5723C/ATA5724C) BER ≤ 10-3 fin = 315MHz/433.92MHz VS = 5V, Tamb = 25°C fIF = 987kHz BR_Range0 df = ±16kHz df = ±10kHz to ±30kHz PRef_FSK –104 –102 –107 –108.5 –108.5 dBm dBm B BR_Range1 df = ±16kHz df = ±10kHz to ±30kHz PRef_FSK –102 –100 –105 –106.5 –106.5 dBm dBm B BR_Range2 df = ±16kHz df = ±10kHz to ±30kHz PRef_FSK –100.5 –98.5 –103.5 –105 –105 dBm dBm B BR_Range3 df = ±16kHz df = ±10kHz to ±30kHz PRef_FSK –98.5 –96.5 –101.5 –103 –103 dBm dBm B 14.6 Input sensitivity FSK 600kHz IF filter (Atmel ATA5728C) BER ≤ 10 -3 fin = 868.3MHz VS = 5V, Tamb = 25°C fIF = 948kHz BR_Range0 df = ±16kHz to ±28kHz df = ±10kHz to ±100kHz PRef_FSK –102 –100 –105 –106.5 –106.5 dBm dBm B BR_Range1 df = ±16kHz ±28kHz df = ±10kHz to ±100kHz PRef_FSK –100 –98 –103 –104.5 –104.5 dBm dBm B BR_Range2 df = ±18kHz ±31kHz df = ±13kHz to ±100kHz PRef_FSK –98.5 –96.5 –101.5 –103 –103 dBm dBm B BR_Range3 df = ±25kHz ±44kHz df = ±20kHz to ±100kHz PRef_FSK –96.5 –94.5 –99.5 –101 –101 dBm dBm B 14.7 Sensitivity variation FSK for the full operating range compared to T amb = 25°C, VS = 5V (Atmel ATA5723C/ ATA5724C/ATA5728C) 300 kHz and 600 kHz versions f in = 315MHz/433.92MHz/868.3MHz PFSK = PRef_FSK + ΔPRef ΔPRef +3 –1.5 dB B 19. Electrical Characteristics At mel ATA5723C/24C/28C (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 14.8 Sensitivity variation FSK for the full operating range including IF filter compared to T amb = 25°C, VS = 5V 300kHz version (ATA5723C/ATA5724C) fin = 315MHz/433.92MHz fIF = 987kHz fIF = –110kHz to +110kHz fIF = –140kHz to +140kHz fIF = –180kHz to +180kHz PFSK = PRef_FSK + ΔPRef ΔPRef +6 +11 dB dB dB B 600kHz version (Atmel ATA5728C) fin = 868.3MHz fIF = 948kHz fIF = –150kHz to +150kHz fIF = –200kHz to +200kHz fIF = –260kHz to +150kHz PFSK = PRef_FSK + ΔPRef ΔPRef +6 +11 dB dB dB B 14.9 S/N ratio to suppress in- band noise signals. Noise signals may have any modulation scheme ASK mode FSK mode SNRASK SNRFSK dB dB C

14.10 Dynamic range RSSI

ΔRRSSI 60 dB A 14.11 RSSI output voltage range VRSSI 1 3.5 V A

14.12 RSSI gain GRSSI 20 mV/dB A

14.13 Lower cut-off frequency of

CDEM = 33nF fcu_DF 0.11 0.16 0.20 kHz B

14.14 Recommended CDEM for

BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF C 14.15 Edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 tee_sig 270 156 1000 560 320 180 µs µs µs µs C

14.16 Upper cut-off frequency data

Upper cut-off frequency programmable in 4 ranges using a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 fu 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 kHz kHz kHz kHz B

14.17 Reduced sensitivity

300kHz version (ATA5723C/ATA5724C) R Sense connected from pin SENS to VS, input matched according to Figure 14-1 “Application Circuit”, fin = 315MHz/433.92MHz, VS = 5V, Tamb = +25°C dBm (peak level) RSense = 56kΩ PRef_Red –74 –79 –83 dBm B RSense = 100kΩ PRef_Red –83 –88 –93 dBm B 19. Electrical Characteristics At mel ATA5723C/24C/28C (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter fcu_DF

41ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14

14.18 Reduced sensitivity

600kHz version (Atmel ATA5728C) RSense connected from pin SENS to VS, input matched according to Figure 14-1 “Application Circuit”, fin = 868.3MHz, VS = 5V, Tamb = +25°C dBm (peak level) RSense = 56kΩ PRef_Red –63 –68 –73 dBm B RSense = 100kΩ PRef_Red –72 –77 –82 dBm B

14.19 Reduced sensitivity variation

RSense = 56kΩ RSense = 100kΩ PRed = PRef_Red + ΔPRed ΔPRed dB dB C

14.20 Reduced sensitivity variation

Values relative to RSense = 56kΩ RSense = 56kΩ RSense = 68kΩ RSense = 82kΩ RSense = 100kΩ ΔPRed –3.5 –6.0 –9.0 dB dB dB dB C 14.21 Threshold voltage for reset VThRESET 1.95 2.8 3.75 V A

15 Digital Ports

15.1 Data output - Saturation voltage Low - max voltage at pin DATA - quiescent current - short-circuit current - ambient temp. in case of permanent short-circuit Data input - Input voltage Low - Input voltage High Iol ≤ 12mA Iol = 2mA Voh = 20V Vol = 0.8V to 20V Voh = 0V to 20V Vol Vol Voh Iqu Iol_lim tamb_sc VIl Vich 0.65 × VS 0.35 0.08 0.8 0.3 0.35 × V S V V V µA mA V V A 15.2 DATA_CLK output - Saturation voltage Low - Saturation voltage High IDATA_CLK = 1mA IDATA_CLK = –1mA Vol Voh VS – 0.4V 0.1 VS – 0.15V 0.4 V V A 15.3 IC_ACTIVE output - Saturation voltage Low - Saturation voltage High IIC_ACTIVE = 1mA IIC_ACTIVE = –1mA Vol Voh VS – 0.4V 0.1 VS – 0.15V 0.4 V V A 15.4 POLLING/_ON input - Low level input voltage - High level input voltage Receiving mode Polling mode VIl VIh 0.8 × VS 0.2 × VS V V A

15.5 MODE pin

• High level input voltage Test input must always be set to high VIh 0.8 × VS V A

15.6 TEST 1 pin

• Low level input voltage Test input must always be set to low VIl 0.2 × VS V A 19. Electrical Characteristics At mel ATA5723C/24C/28C (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 21. Package Information 20. Ordering Information Extended Type Number Package MOQ Remarks ATA5723P3C-TKQW SSO20 4,000 315MHz version ATA5724P3C-TKQW SSO20 4,000 433MHz version ATA5728P6C-TKQW SSO20 4,000 868MHz version Package Drawing Contact: packagedrawings@atmel.com GPC DRAWING NO. REV. TITLE 6.543-5182.01-4 1 04/16/14 4.4mm COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM NOTE MAXSymbol Dimensions in mm specifications according to DIN technical drawings 0.1 0.150.05A1 4.4 4.54.3E1 0.25 0.30.2b

0.65 BSCe

0.15 0.20.1C 0.6 0.70.5L 6.4 6.56.3E 6.5 6.66.4D 0.9 0.950.85A2 1.0 1.10.9A 20 11 11 0 D b e A A2 C E L

43ATA5723C/ATA5724C/ATA5728C [DATASHEET] 9248D–RKE–10/14 22. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9248D-RKE-10/14

• Section 20 “Ordering Information” on page 42 updated
• Section 21 “Package Information” on page 42 updated 9248C-RKE-08/14 • Put datasheet in the latest template

Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: 9248D–RKE–10/14 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in c onnection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDIT IONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WH ATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS P RODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PU NITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMI TATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. Atmel d oes not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atme l products are not suitable for, and shall not be used in, automo tive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIM ER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (“Safety-Critical A pplications”) without an Atmel officer's specific written consent. Safety-Critical Applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by Atmel as automotive-grade.