ATA5282

ATA5282 ATMEL

Document overview

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• PDF pages: 23

Technical content

Features

 Three Input Channels for 3D Antennas  2.8 mVPP Sensitivity Typically  Ultra Low Current Operation Consumption  2 µA Standby Current Typically  4 µA Active Current Typically  P o w e r S u p p l y 2V t o 4 . 2V  Carrier Frequency Range from 100 kHz to 150 kHz  Wake-up Function for a Microcontroller  Header Detection  Baud Rate up to 4 kbps (ASK Modulation)  Bi-directional Two-wire Interface  ESD According to Automotive Requirements Benefits  Digital RSSI for Field Strength Measurement  Coils Input Range from 2.8 mVPP to 2.8 VPP Typically  High Sensitivity

Applications

 Passive Entry Go (PEG)/Car Access  Position Indicator  Home Access Control  RFID Systems

Description

The ATA5282 is a 125-kHz ultra low power receiver IC with three input channels for Passive Entry Go applications. It includes all circuits for an LF wake-up channel. The three sensitive input stages of the IC amplifier demodulate and measure the input sig- nal from the antenna coils. The microcontroller interface of the IC outputs the data signal as well as the measured RSSI values. During standby mode, the header detec- tion unit monitors the incoming signal and generates a wake-up signal for the microcontroller if the IC receives a valid 125-kHz carrier signal. By combining the IC with an antenna coil, a microcontroller, an RF transmitter/trans- ceiver and a battery, it is possible to design a complete hands-free key for Passive Entry Go applications. Ultra Low Power 125 kHz 3D - Wake-up Receiver with RSSI ATA5282 Preliminary

2 ATA5282 [Preliminary]

Figure 1. Block Diagram Figure 2. Pinning TSSOP 8L

3 Channel Amplifier

1 COIL1 Input: Coil channel X

2 COIL2 Input: Coil channel Y

3 COIL3 Input: Coil channel Z

4 VSS Circuit ground

5 TC Output: Current output for oscillator adjustment

6 NSCL Input: Clock for serial interface (default high)

8 VDD Battery voltage

ATA5282 [Preliminary] 4694B–AUTO–06/04 Functional The ATA5282 is a 3-channel ASK receiver fo r 125-kHz carrier signals. Its three active input stages with very low power consumption and high input sensitivity allow to connect up to 3 antennas for direction-independent wake-up function and data transfer. Without a carrier signal the ATA5282 operates in standby listen mode. In this mode, it monitors the 3 Coil inputs with a very low current consumption. To activate the IC and the connected control unit, the transmitting end must send a preamble carrier burst and the header code. When a preamble has been detected, the IC activates the internal oscillator and the header check. The last gap at the end of a valid header enables the NDATA output. During data transfer, the NDATA pin outputs the demodulated and merged signal of the 3 input stages. To achieve data rates up to 4 kbps for input signals from 2.8 mV PP to 3.1 VPP it is neces- sary to control the gain of the amplifiers. Each of the 3 input stages contain an amplifier with Automatic Gain Control (AGC). It is used to adapt the gain to the incoming signal strength, and is also used as RSSI for field strength measurements. The integrated synchronous serial interface uses the NSCL together with the NDATA pin as clock and data line. It allows to control several functions as well as read out the received signal field strength. Enabling only single coil inputs, freezing the actual status of the automatic gain control or resetting the complete circuit to the initial state at any time are built-in features. When communication is finished or a time out event occurs, the internal watchdog timer or reset command via the serial interface sets the IC to standby listen mode.

4 ATA5282 [Preliminary]

header check and data transfer is not shown here. Figure 3. ATA5282 State Diagram

ATA5282 [Preliminary] 4694B–AUTO–06/04 AGC Amplifier Each of the three input stages contain an AGC amplifier to amplify the input signal from the Coil. The gain is adjusted by the automatic gain control circuit if a preamble signal is detected. The high dynamic range of the AGC amplifier enables the IC to work with input signals from 2.8 mV PP to 3.1 VPP. After the AGC settling time has elapsed, the amplifier output delivers a 125-kHz signal with an amplitude adjusted for the following evaluation circuits (preamble detection, signal conditioner, wake-up). Automatic Gain Control For correct demodulation, the signal conditioner needs an appropriate internal signal amplitude. To control the input signal, the ATA5282 has a built-in digital AGC for each input channel. This gain control circuit regulates the internal signal amplitude to the ref- erence level (Ref2, Figure 4 on page 6). The gain control uses the signal of the input channel with the highest amplitude for the r egulation as well as signal for the signal conditioner. During the preamble, each period of the carrier signal decreases the gain if the internal signal exceeds the reference level. If the signal does not achieve the reference level, each period increases the gain. After 192 pr eamble periods, the standard gain control mode is activated. In this mode, the gain is decreased every two periods if the internal signal exceeds the reference level and increased every eight periods if the reference level is not achieved. These measures assure that the input signal’s envelope deforma- tion will be minimized. During the gaps between signal bursts, the gain control is frozen to avoid that the gain be modified by noise signals. The tuning range of the AGC is subdivided into 256 regulator steps. The settling time for the full tuning range requires 320 periods (192 + (2 × 64) periods) during a preamble phase. To accelerate the settling time, fast gain control mode can be activated via the serial interface. In this mode, the tuning range is subdivided into 128 steps and the set- tling time is two times faster. In standby listen mode, the gain is reset to the maximum value. A proper carrier signal activates the automatic gain control. The preamble (Figure 9 on page 10) with up to 320 periods of the 125 kHz magnetic field is used to control the gain of the input amplifiers. To detect the starting point of the header, the start gap should not exceed 256 µs (32 periods of 125 kHz).

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Figure 4. Automatic Gain Control

8 ATA5282 [Preliminary]

Signal Conditioner The signal conditioner operates on the demodulated output signal of all three channels. Figure 7. Function of Signal Conditioner signal amplitudes which results in the suppression of further process of these channels. nal with the highest input amplitude. steps for full range tuning of amplifiers.

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Figure 9. Wake-up Protocol for 125-kHz ASK Modulation

(pulse distance, Manchester, bi-phase...) is used. Figure 10. Output Timing Conditons Table 1. Typical Output Timing versus Signal Strength at 3.2 V Supply Voltage

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fast as possible back to the initial value. header has been detected within 2 ms, the circuit switches back to the initial state. unconditional after a fixed time. received data are corrupted. signal received) also leads to the reset state. a fixed time of 360 ms at the latest. Figure 11. Current Profile and Reset Timing

internal shift register. The interface starts working with the first falling edge of NSCL. the command mode that only requires an 8-bit input and does not prepare a data output. another 8 shift clocks to clock out the information. Figure 12. Serial Interface

14 ATA5282 [Preliminary]

Note: These commands, except FREEZE- and READ_FS, cause a reset of AGC to initial state. Note: The content of the data register is updated every time a READ_FS command is given via the interface. Table 2. Command Register

0 Application mode active

1 Test mode active

0 Standard gain control active (AGC full range: 256 steps)

1 Fast gain control active (AGC full range: 128 steps)

1 Reset circuit to initial state

1 Read AGC-counter (field strength)

0 Automatic Gain Control (AGC) active

1 AGC stopped with actual value

Table 3. Data Register

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Figure 14. Read Field Strength of Channel 1 Figure 15. Reset Interface resynchronizing the interface.

Figure 16. Application Circuit

433 MHz

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Figure 17. Pin Connection and Pin Protection

ATA5282 [Preliminary] 4694B–AUTO–06/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Power supply V DD -0.3 to +6.5 V Input voltage (except coil inputs) V IN VSS - 0.3 < VIN < VDD + 0.3 V Input current coil I CI ±10 mA Input voltage coil V CI VDD - 3.5 < VCI < VDD + 3.5 V ESD protection (human body) V ESD 4k V Operating temperature range T amb -40 to +85 °C Storage temperature range T stg -40 to +130 °C Soldering temperatur T sld 260 °C Thermal resistance (TSSOP 8L) R thJA 240 k/W Thermal Resistance Parameters Symbol Value Unit Thermal resistance junction-case R thJC 260 °C Thermal resistance junction-ambient R thJC 240 °C Operating Range Parameters Symbol Value Unit Power supply range V DD 2 to 4.2 V Operating temperature range T OP -40 to +85 °C

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4694B–AUTO–06/04

Electrical Characteristics

VSS = 0 V , VDD = 3.2 V , Tamb = 25°C unless otherwise specified No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Power Supply and Coil Limiter

1.1 Power supply 8 V DD 23 . 2 4 . 2VA

1.2 Supply current

(initial state, AGC off) 8I DD 24 µ A A

1.3 Supply current (AGC active) 8 I DD 46 µ A A

1.4 Power on reset threshold V POR 11 . 5 1 . 9VA

1.5 Power up time Switch on VDD to

circuit active VPON 100 ms C

1.6 RESET reactivation caused by

tBDN = 500 ns 7 t RST 10 100 µs C 1.71 1.72 1.73 Coil input voltage refered to VDD (Input Coil limiter for channels X, Y , Z) ICI = ±1 mA VDD = 2.0 V VDD = 3.2 V VDD = 4.2 V 1, 2, 3 V CI ±1.2 ±1.4 ±1.55 VP VP VP A

1.8 TC low current output V O_TC at 500 mV 5 I TC 230 250 270 nA A

1.9 Carrier frequency range 1, 2, 3 f CF 100 150 kHz D

2 Amplifiers

2.1 Wake-up sensitivity 125-kHz input signal 7 V SENS 2.8 3.6 mV PP A

2.2 Bandwith Without Coil B W 200 kHz C

2.3 Upper corner frequency Without Coil f u 230 kHz C

2.4 Lower corner frequency Without Coil f o 30 kHz C

2.5 Gain difference Channel to channel 1, 2, 3 G DIFF ±20 % A

2.6 Input impedance VIN ≥ 2.8 mVPP at 125 kHz 1, 2, 3 R IN 143 k Ω A

2.7 Input capacitance 1, 2, 3 C IN 10 pF C

2.8 Coils Input Range VCI = 2.8 mVPP VCI = 2.8 VPP 1, 2, 3 60 dB A 3D i g i t a l

3.1 Oscillator frequency REXT = 2 MΩ and

CEXT maximum 10 pF fOSC 80 90 100 kHz A 3.2 Preamble periods (not FGC) V CI ≥ 3.2VPP 1, 2, 3 n PAM 320 A 3.3 Header detection windows (L = long, S = short) see Figure 8 on page 9 Tolerance included oscillator tolerance tST ART_L 160 182 205 µs A 3.4 t END_L 315 357 400 µs A 3.5 t ST ART_S 40 50 60 µs A 3.6 t END_S 200 225 255 µs A

3.7 Shift clock period 6 t NSCL 10 µs C

3.8 Data access time t ACC 50 µs A

3.9 Data rate (Q < 20) 125 kHz ASK D RATE 4k b p s A

3.10 Delay time RF signal to data 125 kHz ASK t ON 40 µs A

3.11 Delay time RF signal to data 125 kHz ASK t OFF 40 µs A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA5282 [Preliminary] 4694B–AUTO–06/04

4 Interface

4.1 NSCL input level LOW 6 V IL_NSCL VSS 0.2 × VDD VA 4.2 NSCL input level HIGH 6 V IH_NSCL 0.8 × VDD VDD VA

4.3 NSCL input leakage current

VNSCL = VSS 6I IL_NSCL -200 0 nA A

4.4 NSCL input leakage current

VNSCL = VDD 6I IH_NSCL 0+ 2 0 0 n A A 4.5 NDAT A input level LOW V NSCL = VSS 7V IL_NDAT VSS 0.2 × VDD VA 4.6 NDAT A input level HIGH V NSCL = VSS 7V IH_NDAT 0.8 × VDD VDD VA

4.7 NDATA input leakage current

VNDAT = VSS VNSCL = VSS 7I IL_NDAT -200 0 nA A

4.8 NDATA input leakage current

VNDAT = VDD VNSCL = VSS 7I IH_NDAT 0+ 2 0 0 n A A

4.9 NDAT A output level LOW INDAT = +100 µA

VNSCL = VDD 7V OL_NDAT VSS 0.2 × VDD VA

4.10 NDAT A output level HIGH INDAT = -100 µA

VNSCL = VDD 7V OL_NDAT 0.8× VDD VDD VA Electrical Characteristics (Continued) VSS = 0 V , VDD = 3.2 V , Tamb = 25°C unless otherwise specified No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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4694B–AUTO–06/04

Ordering Information

Package Information

Figure 18. Package TSSOP 8L

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