ATA3742P3-TGSY

ATA3742_07 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 34

Technical content

Features

• IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) Output  Minimal External Circuitry Requirements, No RF Components on the PC Board Except Matching to the Receiver Antenna  High Sensitivity, Especially at Low Data Rates  Sensitivity Reduction Possible Even While Receiving  Fully Integrated VCO  Low Power Consumption Due to Configurable Self-polling With a Programmable Time Frame Check  Supply Voltage 4.5V to 5.5V  Operating Temperature Range –40°C to +105°C  Single-ended RF Input for Easy Adaptation to λ /4 A n t e n n a o r P r i nted Antenna on PCB  Low-cost Solution Due to High Integration Level  ESD Protection According to MIL-STD. 883 (4 KV HBM)  High Image Frequency Suppression Due to 1 MHz IF in Conjunction With a SAW Front-end Filter (Up to 40 dB Achievable With Newer SAWs)  Communication to Microcontroller Possible via a Single, Bi-directional Data Line  Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller 1. Description The ATA3742 is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel ®’s PLL RF transmitter IC U2741B. Its main applications in the area of wireless control are telemetering, security technology, tire-p ressure monitoring and keyless-entry sys- tems. It can be used in the frequency receiving range of f 0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the statements made in this datasheet refer both to 433.92 MHz and 315 MHz applications. UHF ASK/FSK Receiver ATA3742 4900B–RKE–11/07

4900B–RKE–11/07 ATA3742 Figure 1-1. System Block Diagram Figure 1-2. Block Diagram Micro- controller PLL

1 Li cell

Remote control transmitter U2741B ATA3742 LNA VCO PLL XTO Power amp. VCO Antenna Demod Control 1 to 3 XTO Antenna 4th Order Polling circuit and control logic Standby Logic Sensitivity reduction f :64 IF Amp IF Amp FSK/ASK Demodulator and Data Filter RSSI Limiter out Dem_out LNA CLK ENABLE DVCC MODE TEST DATA VS FE LPF

3 MHz

LNA_IN MIXVCC DGND AGND AVCC SENS RSSI CDEM LFVCC XTO LF LFGND VCO XTO 50 kΩ

4900B–RKE–11/07 ATA3742 2. Pin Configuration Figure 2-1. Pinning SO20 SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC NC LNAGND LNA_IN DATA ENABLE TEST RSSI MODE DVCC XTO LFVCC LFGND LF Table 2-1. Pin Description Pin Symbol Function

1 SENS Sensitivity-control resistor

2 FSK/ASK Selecting FSK/ASK

Low: FSK, High: ASK

3 CDEM Lower cut-off frequency of the data filter

4 AVCC Analog power supply

5 AGND Analog ground

6 DGND Digital ground

7 MIXVCC Power supply mixer

8 LNAGND High-frequency ground LNA and mixer

9 LNA_IN RF input

10 NC Not connected

11 LFVCC Power supply VCO

12 LF Loop filter

13 LFGND Ground VCO

14 XTO Crystal oscillator

15 DVCC Digital power supply

16 MODE

Selecting 433.92 MHz/315 MHz Low: 4.90625 MHz (USA) High: 6.76438 (Europe)

17 RSSI Output of the RSSI amplifier

18 TEST Test pin, during operation at GND

19 ENABLE

Low: polling mode off (sleep mode) High: polling mode on (active mode)

20 DATA Data output/configuration input

4900B–RKE–11/07 ATA3742 3. RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1 MHz IF signal. As seen in Figure 1-2 on page 2, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesi zer. The XTO (crystal oscillator) generates the reference frequency f XTO. The VCO (voltage-controlled oscillator) gen- erates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared to f XTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage V LF for the VCO. By means of that configuration, V LF is controlled in a way that f LO / 64 is equal to f XTO. If fLO is determined, f XTO can be calculated using the following formula: fXTO = fLO /6 4 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The crystal should be connected to GND via the capacitor CL according to Figure 3-1. The value of that capacitor is recommended by the crystal su pplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. Figure 3-1. PLL Peripherals The passive loop filter connected to pin LF is designed for a loop bandwidth of B Loop = 100 kHz. This value for B Loop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo- nents are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longe r be possible since f LO can- not settle in time before the bit check starts to evaluate the incoming data stream. In that case, self-polling will also not work. fLO is determined by the RF input frequency f RF and the IF frequency f IF using the following formula: fLO = fRF – fIF XTO LFVCC LF LFGND DVCC VS VS CL 820Ω 4.7 nF C10 1 nF

4900B–RKE–11/07 ATA3742 To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency f XTO. This means that there is a fixed relation between f IF and fLO that depends on the logic level at pin MODE. This is described by the following formulas: The relation is designed to achieve the nominal IF frequency of f IF = 1 MHz for most applica- tions. For applications where f RF = 315 MHz, MODE must be set to “0”. In the case of fRF = 433.92 MHz, MODE must be set to “1”. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on f RF. Table 3-1 summarizes the dif- ferent conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para- sitic board inductances and capacitances also influence the input matching. The RF receiver ATA3742 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef =4 0d B can be achieved. There are SAWs ava ilable that exhibit a notch at ∆f=2M H z . T h e s e S A W s work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 3-2 on page 6 shows a typical input matching network for f RF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates input matching to 50Ω without a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks for the parameters given in the “Electrical Characteristics” on page 26. Table 3-1. Calculation of LO and IF Frequency Conditions Local Oscillator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 f LO = 314 MHz f IF = 1 MHz fRF = 433.92 MHz, MODE = 1 f LO = 432.92 MHz f IF = 1 MHz

300 MHz < fRF < 365 MHz, MODE = 0

365 MHz < fRF < 450 MHz, MODE = 1

MODE 0 (USA) f IF fLO MODE 1 (Europe) f IF fLO fLO fRF 1 1 fLO fLO fRF 1 1 fLO

4900B–RKE–11/07 ATA3742 4. Analog Signal Processing

4.1 IF Amplifier

The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is f IF = 1 MHz for applications where f RF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, see Table 3-1 on page 5 to determine the center frequency. The receiver ATA3742-M3 employs an IF bandwidth of B IF = 600 kHz and can be used together with the U2741B in FSK and ASK mode.

4.2 RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is ∆R RSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode, the SNR is not affected by the dynamic range of the RSSI amplifier. The output voltage of the RSSI amplifier is internally compared to a threshold voltage V Th_red. VTh_red is determined by the value of the external resistor R Sense. RSense is connected between pin SENS and GND or V S. The output of the comparator is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity.

4.3 Pin RSSI

The output voltage of the RSSI amplifier (V RSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input-power range P Ref is –100 dBm to –55 dBm. The temperature coefficient TC of VRSSI is typically –2.2 mV/K. Due to TC and gain tolerance, it is not possible to find out the abso- lute level of each transmitter, but the level differences can be used to distinguish several transmitters. As illustrated in Figure 4-2 on page 8, the RSSI output voltage is not constant over the temperature range. Figure 4-1 illustrates an application that realizes a temperature compen- sation of VRSSI.

4900B–RKE–11/07 ATA3742 RSense can be connected to VS or GND via a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice vers a at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, t he data stream at pin DATA will disappear when the input si gnal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern shown in Figure 4-3 is issued at pin DATA to indicate that the receiver is still active. Figure 4-3. Steady L State Limited DATA Output Pattern

4.4 FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic “L” sets the demodulator to FSK mode; logic “H” sets it into ASK mode. In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detection refer- ence voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the SNR exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower values may be used, but the sensitivity of the receiver will be reduced. The minimum usable deviation is dependent on the selected baud rate. In FSK mode, only BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be detected if the SNR exceeds 2 dB. The output signal of the demodulator is filtered by t he data filter before it is fed into the digital signal processing circuit. The data filter improves the SNR as its pass band can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order high-pass and a 1st-order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in “Electrical Characteristics” on page 26. The values are slightly different for ASK and FSK mode. The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (refer to Section “Configuration of the Receiver” on page 20). BR_Range must be set in accordance to the used baud rate. The ATA3742 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always re main within the range of V DC_min = 33% and V DC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. tDATA_L_maxtmin2 DATA fcu_DF

4900B–RKE–11/07 ATA3742 Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). These limits are defined in the el ectrical characteristics. They should not be exceeded to main- tain full sensitivity of the receiver.

4.5 Receiving Characteristics

The RF receiver ATA3742 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end f ilter is illustrated in Figure 4-4 on page 10 . This example relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in te rms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA3742. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA3742 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm. Note that the receiving bandwidth and the IF-filter band- width are equivalent in ASK mode but not in FSK mode. Figure 4-4. Receiving Frequency Response -20 -30 -40 -50 -60 -100 -90 -80 -70 -10 -6 -5 -2 -1 -4 -3 0 1 4 5 6 23 df (mHz) dP (dB) without SAW with SAW

4900B–RKE–11/07 ATA3742 5. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time , the bit check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active and transfer the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time, resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate, etc. Regarding the number of connection wires to the mi crocontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontrol- ler, or it can be operated by up to three uni-directional ports.

5.1 Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 5-1 on page 11 , this clock cycle T Clk is derived from th e crystal oscillator (XTO) in combination with a divi der. The division factor is contro lled by the logical state at pin MODE. As described in Section “RF Front End” on page 4, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (f RFin), which also defines the operating frequency of the local oscillator (fLO). Figure 5-1. Generation of the Basic Clock Cycle Pin MODE can now be set in accordance with the desired clock cycle T Clk. TClk controls the fol- lowing application-relevant parameters:  Timing of the polling circuit including bit check  Timing of the analog and digital signal processing  Timing of the register programming  Frequency of the reset marker  IF filter center frequency (f IF0) MODE L: USA (:10) H: Europe (:14) XTO Divider :14/10 DVCC XTO fXTO TCLK

4900B–RKE–11/07 ATA3742 Most applications are dominated by two transmission frequencies: f Send = 315 MHz is mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter.  Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)  Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)  Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T XClk is defined by the following for- mulas for further reference:

5.2 Polling Mode

As seen in Figure 5-3 on page 15 , the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of I S =I Soff. During the start-up period, T Startup, all sig- nal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit, looking fo r a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBitcheck. This period varies check by check as it is a statistical process. An average value for TBitcheck is given in the electrical char- acteristics. During TStartup and TBitcheck the current consumption is I S =I Son. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be cal- culated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitt er must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStar- tup, TBitcheck and the startup time of a connected microcontroller (T Start,microcontroller ). TBitcheck thus depends on the actual bit rate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. TPreburst ≥ TSleep + TStartup + TBitcheck + TStart_microcontroller BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk ISpoll ISoff TSleep ISon TStartup TBitcheck+()×+×

4900B–RKE–11/07 ATA3742

5.2.1 Sleep Mode

The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the exten- sion factor X Sleep according to Table 5-7 on page 22 , and the basic clock cycle T Clk . It is calculated to be: TSleep = Sleep × XSleep × 1024 × TClk In US and European applications, the maximum value of T Sleep is about 60 ms if X Sleep is set to “1”. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting X Sleep to 8. X Sleep can be set to 8 by bit X SleepStd or by bit X SleepTemp , resulting in a different mode of action as described below: XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to “0”, automatically result- ing in a regular sleep time. This functionality can be used to save current in the presence of a modulated disturber similar to an expected trans mitter signal. The connected microcontroller is rarely activated in that condition. If the disturbe r disappears, the receiver switches back to regu- lar polling and is again sensitive to appropriate transmitter signals. The highest register value of Sleep sets the receiver into a permanent sleep condition (see Table 5-6 on page 22 ). The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This func tion is desirable where several devices share a single data line.

5.2.2 Bit-check Mode

In bit-check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a pro- grammable time window. The maximum count of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable.

5.2.3 Configuring the Bit Check

Assuming a modulation scheme that contains 2 ed ges per bit, two time frame checks verify one bit. This is valid for Manchester, bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N Bitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N Bitcheck is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBitcheck is set to a lower value. In poll- ing mode, the bit check time is not dependent on N Bitcheck . Figure 5-1 on page 11 shows an example where 3 bits are tested successfully and the data signal is transferred to pin DATA. According to Figure 5-2, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time t ee is in between the lower bit check limit T Lim_min and the upper bit check limit T Lim_max , the check will be continued. If t ee is smaller than T Lim_min or t ee exceeds TLim_max, the bit check will be terminated and the receiver switches to sleep mode.

4900B–RKE–11/07 ATA3742 Figure 5-2. Valid Time Window for Bit Check For best noise immunity it is recommended to use a low span between T Lim_min and T Lim_max . This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A mendation. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge time tee. Using preburst patterns that con- tain various edge-to-edge time periods, the bit check limits must be programmed according to the required span. The bit check limits are determined by means of the formula below: T Lim_min = Lim_min × TXClk TLim_max = (Lim_max – 1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using the above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution when defining T Lim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to Section “Receiv- ing Mode” on page 17. Due to this, the lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. 1/fSig Tee TLim_max TLim_min Dem_out

4900B–RKE–11/07 ATA3742 Figure 5-3. Polling Mode Flow Chart Bit-check Mode: The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on pin IC_ACTIVE = > high T Bit-check IS = ISon Start-up Mode: The signal processing circuits are enabled. After the start-up time (T Startup) all circuits are in stable condition and ready to receive. Output level on pin IC_ACTIVE = > high T Startup IS = ISon Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or ENABLE I S = ISon Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on pin IC_ACTIVE = > low T Sleep = Sleep × XSleep × 1024 × TClk IS = ISoff Bit Check OK ? 5-bit word defined by Sleep0 to Sleep4 in OPMODE register Sleep: Is defined by the selected baud-rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. T Startup: Basic clock cycle defined by f XTO and pin MODE TClk: If the bit check fails, the average time period for that check depends on the selected baud-rate range and on T Clk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. If the bit check is ok, T Bit-check depends on the number of bits to be checked (NBit-check) and on the utilized data rate. Depends on the result of the bit check.XBit-check: Extension factor defined by XSleepTemp according to Table 5-7 XSleep: OFF Command YES NO

4900B–RKE–11/07 ATA3742 Figure 5-5 on page 16 to Figure 5-7 illustrate the bit check fo r the default bit check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during T Startup. The output of the ASK/FSK demodulator (Dem_out) is undefined during that period. When the bit check bec omes active, the bit check count er is clocked with the cycle TXClk. Figure 5-5 on page 16 shows how the bit check proceeds if the bit check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Fig- ure 5-6 on page 16 , the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 5-7.

5.2.4 Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBitcheck varies for each check. Therefore, an average value for T Bitcheck is given in the electrical characteristics. T Bitcheck depends on the selected baud rate range and on T Clk. A higher baud rate range causes a lower value for TBitcheck resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, T Bitcheck is dependent on the frequency of that sig- nal, fSig, and on the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby results in a longer period for TBitcheck requiring a higher value for the transmitter preburst TPreburst.

5.3 Receiving Mode

If the bit check is successful for all bits specified by N Bitcheck, the receiver switches to receiving mode. As shown in Figure 5-4 on page 16 , the internal data signal is switched to pin DATA in that case. A connected microcontroller can be woken up by the negative edge at pin DATA. The receiver stays in that condition until it is switched back to polling mode explicitly.

5.3.1 Digital Signal Processing

The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud rate range (BR_Range). Figure 5-8 on page 18 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit check counter. Data can change its state only after T XClk elapses. The edge-to-edge time period t ee of the data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to t ee ≥ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max- imum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. T DATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 5-9. If tee is in between the specified bit check limits, the following level is frozen for the time period T DATA_min = tmin1, in case of t ee being outside that bit check limits TDATA_min = tmin2 is the relevant stable time period. The maximum time period for DATA to be Low is limited to T DATA_L_max. This function ensures a finite response time during programming or switching off the receiver via pin DATA. T DATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 5-10 gives an example where Dem_out remains Low after the receiver is in receiving mode.

4900B–RKE–11/07 ATA3742

5.3.2 Switching the Receiver Back to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin ENABLE. When using pin DATA, this pin must be pulled to Low for the period t 1 by the connected micro- controller. Figure 5-11 illustrates the timing of the OFF command (see also Figure 5-15 on page 24). The minimum value of t 1 depends on BR_Range. The maximum value for t 1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in Section “Configuration of the Receiver” on page 20. Set- ting the receiver to sleep mode via DATA is achieved by programming bit 1 of the OPMODE register to be “1”. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF com- mand, the sleep time T Sleep elapses. Note that the capacitive load at pin DATA is limited. The resulting time constant τ together with an optional external pull-up resistor may not be exceeded to ensure proper operation. If the receiver is set to polling mode via pin ENABLE, an “L” pulse (TDoze) must be issued at that pin. Figure 5-12 on page 20 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is held to “L”. If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to “0” to enable an instantaneous response time. Th is command is a faster option than via pin DATA, at the cost of an additional connection to the microcontroller. Figure 5-11. Timing Diagram of the OFF Command via Pin DATA Serial bi-directional data line Out1 (microcontroller) DATA (ATA3742) TSleep t10 Bit 1 ("1") (Start Bit) OFF command X X Receiving mode Startup mode t1 t2 t5

4900B–RKE–11/07 ATA3742 Figure 5-12. Timing Diagram of the OFF Command via Pin ENABLE

5.4 Configuration of the Receiver

The ATA3742 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register con- tents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 5-2 on page 21 shows the structure of the registers. Refering to Table 5-1, bit 1 defines if the receiver is set back to polling mode via the O FF command (see Section “Receiving Mode” on page 17), or if it is programmed. Bit 2 represents the register address. It selects the appropri- ate register to be programmed. Table 5-3 on page 21 and the following illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim is used to define the bit check limits T Lim_min and TLim_max as shown in Table 5-3 on page 21. ENABLE Serial bi-directional data line DATA (ATA3742) toff TDoze TSleep Startup modeReceiving mode X X Table 5-1. Effect of Bit 1 and Bit 2 in Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed

4900B–RKE–11/07 ATA3742 Table 5-2. Effect of the Configuration Words Within the Registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 OFF Command OPMODE Register 0 1 BR_Range N Bitcheck VPOUT Sleep X Sleep 0 1 Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X Sleep Std XSleep Temp ( D e f a u l t ) 0 0 1 0 0 010110 0 LIMIT Register 0 0 Lim_min Lim_max 0 0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 ( D e f a u l t ) 0 0 1 1 1 001100 0 Table 5-3. Effect of the Configuration Word BR_Range BR_Range Baud Rate Range/Extension Factor for Bit Check Limits (XLim)Baud1 Baud0 00 BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default) 01 BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 10 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 11 BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5-4. Effect of the Configuration Word NBitcheck NBitcheck Number of Bits to be CheckedBitChk1 BitChk0 00 0 01 3 1 0 6 (Default) 11 9 Table 5-5. Effect of the Configuration Bit Reserved Reserved Bit No Function (R eserved for Future Use) 0 (Default)

4900B–RKE–11/07 ATA3742 Table 5-6. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk)Sleep4 Sleep3 Slee p2 Sleep1 Sleep0 00000 0 ( R e c e i v e r i s c o n t i n u o u s l y p o l l i n g u n t i l a v a l i d s i g n a l o c c u r s ) 00001 1 ( T Sleep ≈ 2 ms for XSleep = 1 in US/European applications) 00010 2 00011 3 01011 1 1 ( U S A : T Sleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) 11101 2 9 11110 3 0 11111 3 1 ( P e r m a n e n t s l e e p m o d e ) Table 5-7. Effect of the Configuration Word XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk)XSleepStd XSleepTemp 0 0 1 (Default) 01 8 ( X Sleep is reset to 1 if bit check fails once) 10 8 ( X Sleep is set permanently) 11 8 ( X Sleep is set permanently) Table 5-8. Effect of the Configuration Word Lim_min Lim_min Lower Limit Value for Bit Check Lim_min < 10 is not applicable (T Lim_min = Lim_min × XLim × TClk) 001010 1 0 001011 1 1 001100 1 2 001101 1 3 001110 14 (Default) (USA: T Lim_min = 228 µs, Europe: TLim_min = 232 µs) 111101 6 1 111110 6 2 111111 6 3

4900B–RKE–11/07 ATA3742

5.4.1 Conservation of the Register Information

The ATA3742 has an integrated power-on reset (POR) and brown-out detection circuitry to pro- vide a mechanism to preserve the RAM register information. According to Figure 5-13, a power-on reset is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration regis- ters in that condition. Once V S exceeds VThReset, the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency f RM at a 50% duty cycle. RM can be canceled via an “L” pulse t1 at pin DATA. The RM implies the following characteristics: f RM is lower than the lowest feasible frequency of a data signal. This means, RM cannot be misinterpreted by the connected microcontroller.  If the receiver is set back to polling mode via pin DATA, RM cannot be cancelled by accident if t1 is applied according to the proposal in the Section “Programming the Configuration Register” on page 24. By means of that mechanism, the receiver cannot lose its register information without communi- cating that condition via the reset marker RM. Table 5-9. Effect of the Configuration Word Lim_max Lim_max Upper Limit Value for Bit Check Lim_max < 12 is not applicable (T Lim_max = (Lim_max – 1) × XLim × TClk) 001100 1 2 001101 1 3 001110 1 4 011000 24 (Default) (USA: T Lim_max = 375 µs, Europe: TLim_max = 381 µs) 111101 6 1 111110 6 2 111111 6 3

4900B–RKE–11/07 ATA3742 Figure 5-13. Generation of the Power-on Reset Figure 5-14. Timing of the Register Programming

5.4.2 Programming the C onfiguration Register

The configuration registers are programmed seria lly via the bi-directional data line according to Figure 5-14 and Figure 5-15. Figure 5-15. One-wire Connection to a Microcontroller POR DATA (ATA3742) X tRst VThreset VS 1/fRM Serial bi-directional data line Out1 (microcontroller) DATA (ATA3742) Bit 2 ("1") (Register select) Bit 13 ("0") (Poll 8) Bit 14 ("1") (Poll 8R) Bit 1 ("0") (Start bit) Programming frame X X Startup mode Receiving mode t1 t2 t5 TSleept9 Bi-directional data line Internal pull-up resistor DATA (ATA3742) DATA I/O ATA3742 Out1 (microcontroller) Microcontroller

4900B–RKE–11/07 ATA3742 To start programming, the serial data line DATA is pulled to “L” for the time period t 1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t 2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t 3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t 4, the duration is defined by t5. Within the pro- gramming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t Bit 14 is followed by the equivalent time window t 9. During this window, the equivalent acknowl- edge pulse t8 (E_Ack) occurs if the just-programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both during sleep and active mode of the receiver. During programming, the LNA, LO, low-pass filter, IF amplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t 1 initiates the programming of the configuration registers. If bit 1 is set to “1”, it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t 1, the following convention should be considered: t 1(min) < t1 < 1535 × TClk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset marker (RM) is still present at pin DATA. This period is generally used to switch the rece iver to polling mode. In a reset condition, RM is not canceled by accident. t 1 > 5632 × TClk Programming (or the OFF command) is initiated in any case. RM is canceled if present. This period is used if the connected microcontr oller detected RM. If a configuration register is programmed, this time period for t 1 can generally be used. Note that the capacitive load at pin DATA is limited. The resulting ti me constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation.

4900B–RKE–11/07 ATA3742 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Power dissipation P tot 450 mW Junction temperature T j 150 °C Storage temperature T stg –55 +125 °C Ambient temperature T amb –40 +105 °C Maximum input level, input matched to 50Ω Pin_max 10 dBm 7. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 100 K/W 8. Electrical Characteristics All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameter Test Condition Symbol

6.76438 Mhz Oscillator

(Mode 1)

4.90625 Mhz Oscillator

(Mode 0) Variable Oscillator Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) T Clk 2.0697 2.0383 1 / (f XTO /1 0 ) 1/( f XTO /1 4 ) µs µs Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 T XClk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs Polling Mode Sleep time Sleep and X Sleep are defined in the OPMODE register T Sleep Sleep × XSleep × 1024 × 2.0697 Sleep × XSleep × 1024 × 2.0383 Sleep × XSleep × 1024 × TClk ms Start-up time BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Startup 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 × TClk µs µs µs µs Time for Bit Check Average bit-check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Bitcheck 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms Bit-check time for a valid input signal f Sig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 TBitcheck 3/f Sig 6/f Sig 9/f Sig 3.5 / fSig 6.5 / fSig 9.5 / fSig 3/f Sig 6/f Sig 9/f Sig 3.5 / fSig 6.5 / fSig 9.5 / fSig TXClk 3/ fSig 6/f Sig 9/f Sig TXClk 3.5 / fSig 6.5 / fSig 9.5 / fSig ms ms ms ms

4900B–RKE–11/07 ATA3742 Receiving Mode Intermediate frequency MODE=0 (USA) MODE=1 (Europe) fIF 1.0 1.0 f XTO × 64 / 314 fXTO × 64 / 432.92 MHz MHz Baud-rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 µs / T Clk BR_Range1 × 2 µs / TClk BR_Range2 × 2 µs / TClk BR_Range3 × 2 µs / TClk kBaud kBaud kBaud kBaud Minimum time period between edges at pin DATA (Figure 5-9 on page 18) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T DATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 149 182 37.3 45.5 18.6 22.8 147 179 36.7 44.8 18.3 22.4 9 × T XClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk µs µs µs µs µs µs µs µs Maximum low period at DATA (Figure 5-10 on page 18) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TDATA_L_max 2169 1085 542 271 2136 1068 534 267 131 × TXClk 131 × TXClk 131 × TXClk 131 × TXClk µs µs µs µs OFF command at pin ENABLE (Figure 5-12 on page 20) t Doze 3.1 3.05 1.5 × TClk µs Configuration of the Receiver Frequency of the reset marker (Figure 5-13 on page 24) fRM 117.9 119.8 Hz Programming start pulse (Figure 5-11 on page 19, Figure 5-14 on page 24) BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR t 2188 1104 561 290 11656 3176 3176 3176 3176 2155 1087 553 286 11479 3128 3128 3128 3128 1057 × TClk 533 × TClk 271 × TClk 140 × TClk 5632 × TClk 1535 × TClk 1535 × TClk 1535 × TClk 1535 × TClk µs Programming delay period (Figure 5-11 on page 19, Figure 5-14 on page 24) t2 795 798 783 786 384.5 × TClk 385.5 × TClk µs 8. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameter Test Condition Symbol (Mode 1) (Mode 0) Variable Oscillator

4900B–RKE–11/07 ATA3742 Synchroni-zati on pulse (Figure 5-11 on page 19, Figure 5-14 on page 24) t 3 265 261 128 × TClk µs Delay until the program window starts (Figure 5-11 on page 19, Figure 5-14 on page 24) t4 131 129 63.5 × TClk µs Programming window (Figure 5-11 on page 19, Figure 5-14 on page 24) t 5 530 522 256 × TClk µs Time frame of a bit (Figure 5-14 on page 24) t6 1060 1044 512 × TClk µs Programming pulse (Figure 5-11 on page 19, Figure 5-14 on page 24) t 7 133 529 131 521 64 × TClk 256 × TClk µs Equivalent acknowledge pulse: E_Ack (Figure 5-14 on page 24) t8 265 261 128 × TClk µs Equivalent time window (Figure 5-14 on page 24) t9 534 526 258 × TClk µs OFF-bit programming window (Figure 5-11 on page 19) t 10 930 916 449.5 × TClk µs 8. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameter Test Condition Symbol (Mode 1) (Mode 0) Variable Oscillator

4900B–RKE–11/07 ATA3742 9. Electrical Characteristics All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS =5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit Current consumption Sleep mode (XTO and polling logic active) ISoff 190 350 µA IC active (start up, bit check, receiving mode) pin DATA = H ISon 7.0 8.6 mA LNA Mixer Third-order intercept point LNA/mixer/IF amplifier input matched according to Figure 3-3 on page 6 IIP3 –28 dBm LO spurious emission at RFIn Input matched according to Figure 3-3 on page 6, required according to I-ETS 300220 ISLORF –73 –57 dBm Noise figure LNA and mixer (DSB) Input matching according to Figure 3-3 on page 6 NF 7 dB LNA_IN input impedance at 433.92 MHz at 315 MHz ZiLNA_IN 1.0 || 1.56 1.3 || 1.0 kΩ || pF kΩ || pF 1 dB compression point (LNA, mixer, IF amplifier) Input matched according to Figure 3-3 on page 6, referred to RFin IP1db –40 dBm Maximum input level Input matched according to Figure 3-3 on page 6, BER ≤ 10 -3, ASK mode Pin_max –28 –20 dBm dBm Local Oscillator Operating frequency range VCO f VCO 299 449 MHz Phase noise VCO/LO fosc = 432.92 MHz at 1 MHz at 10 MHz L (fm) –93 –113 –90 –110 dBC/Hz dBC/Hz Spurious of the VCO at ±f XTO –55 –47 dBC VCO gain KVCO 190 MHz/V Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820Ω C9 = 4.7 nF C10 = 1 nF BLoop 100 kHz Capacitive load at pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self-polling. CLF_tot 10 nF XTO operating frequency XTO crystal frequency, appropriate load capacitance must be connected to XTAL

6.764375 MHz

4.90625 MHz

fXTO 6.764375 –30 ppm 4.90625 –30 ppm 6.764375 4.90625 6.764375 +30 ppm 4.90625 +30 ppm MHz MHz Series resonance resistor of the crystal fXTO = 6.764 MHz

4.906 MHz RS

Ω Ω

4900B–RKE–11/07 ATA3742 Static capacitance of the crystal C xto 6.5 pF Analog Signal Processing Input sensitivity ASK Input matched according to Figure 3-3 on page 6 ASK (level of carrier) BER ≤ 10 -3, fIF = 1 MHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V PRef_ASK Input sensitivity ASK BR_Range0 –108 –110 –112 dBm BR_Range1 –106.5 –108.5 –110.5 dBm BR_Range2 –106 –108 –110 dBm BR_Range3 –104 –106 –108 dBm Sensitivity variation ASK for the full operating range compared to T amb = 25°C, VS =5 V fin = 433.92 MHz/315 MHz fIF = 1 MHz PASK = PRef_ASK + ∆PRef ∆PRef +2.5 –1.5 dB Sensitivity variation ASK for full operating range including IF filter compared to Tamb =2 5 ° C , VS = 5V fin = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + ∆PRef ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB Input sensitivity FSK Input matched according to Figure 3-3 on page 6, BER ≤ 10 -3, fIF = 1 MHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V PRef_FSK Input sensitivity FSK BR_Range0 df ≥ ±20 kHz df ≥ ±30 kHz –95.5 –96.5 –97.5 –98.5 –99.5 –100.5 dBm dBm BR_Range1 df ≥ ±20 kHz df ≥ ±30 kHz –94.5 –95.5 –96.5 –97.5 –98.5 –99.5 dBm dBm Sensitivity variation FSK for the full operating range compared to Tamb =2 5 ° C , VS =5 V fin = 433.92 MHz/315 MHz fIF = 1 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +2.5 –1.5 dB Sensitivity variation FSK for full operating range including IF filter compared to T amb =2 5 ° C , VS = 5V fin = 433.92 MHz/315 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB FSK frequency deviation The sensitivity of the receiver is higher for higher values of ∆fFSK BR_Range0 BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation FSK kHz kHz SNR to suppress inband noise signals ASK mode FSK mode SNRASK SNRFSK dB dB Dynamic range RSSI amplifier ∆RRSSI 60 dB 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS =5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4900B–RKE–11/07 ATA3742 Lower cut-off frequency of the data filter fcu_DF 0.11 0.16 0.20 kHz Recommended CDEM for best performance ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF Recommended CDEM for best performance FSK mode BR_Range0 (Default) BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation CDEM nF nF Maximum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 t ee_sig 1000 560 320 180 µs µs µs µs Upper cut-off frequency data filter Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 f u 2.5 4.3 7.6 13.6 3.1 5.4 9.5 17.0 3.7 6.5 11.4 20.4 kHz kHz kHz kHz Minimum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 t ee_sig 270 156 µs µs µs µs Reduced sensitivity R Sense connected from pin Sens to VS, input matched according to Figure 3-3 on page 6 PRef_Red dBm (peak level) Reduced sensitivity (VS =5 V , Tamb =2 5 ° C ) RSense = 56 kΩ, fin =4 3 3 . 9 2M H z , –67 –72 –77 dBm RSense = 100 kΩ, fin = 433.92 MHz –76 –81 –86 dBm RSense = 56 kΩ, fin = 315 MHz –68 –73 –78 dBm RSense = 100 kΩ, fin = 315 MHz –77 –82 –87 dBm Reduced sensitivity variation over full operating range RSense = 56 kΩ RSense = 100 kΩ PRed = PRef_Red + ∆PRed ∆PRed dB dB Reduced sensitivity variation for different values of RSense Values relative to RSense = 56 kΩ RSense = 56 kΩ RSense = 68 kΩ RSense = 82 kΩ RSense = 100 kΩ RSense = 120 kΩ RSense = 150 kΩ PRed = PRef_Red + ∆PRed ∆PRed –3.5 –6.0 –9.0 –11.0 –13.5 dB dB dB dB dB dB 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS =5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF

4900B–RKE–11/07 ATA3742 Threshold voltage for reset V ThRESET 1.95 2.8 3.75 V Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load I ol = 1 mA τ = CL (Rpup//RExt) without external pull-up resistor R ext = 5 kΩ VOI RPup τ CL CL 0.08 0.3 2.5 540 V kΩ µs pF pF FSK/ASK input - Low-level input voltage - High-level input voltage FSK selected ASK selected V Il VIh 0.8 × VS 0.2 × VS V V ENABLE input - Low-level input voltage - High-level input voltage Idle mode Active mode VIl VIh 0.8 × VS 0.2 × VS V V MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 × VS 0.2 × VS V V TEST input - Low-level input voltage Test input must always be set to LOW VIl 0.2 × VS V 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS =5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4900B–RKE–11/07 ATA3742 11. Package Information 12. Revision History 10. Ordering Information Extended Type Number Package Remarks ATA3742P3-TGSY SO20 Tube, Pb-free ATA3742P3-TGQY SO20 Taped and reeled, Pb-free technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 11 0 Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4900B-RKE-11/07 • Put datasheet in the newest template

• Pb-free Logo on page 1 deleted

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