Download PDFAT97SC3203 ATMEL
Document overview
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Technical content
Features
- Compliant with Trusted Computing Group (TCG) Trusted Platform Module (TPM) Main Specification Version 1.2 Compliant with TCG PC Client Specific TPM Interface Specification Version 1.2 Single Chip Turnkey Solution Hardware Asymmetric Crypto Engine 2048 RSA Sign in 500 ms AVR® RISC Microprocessor 33 MHz LPC (Low Pin Count) Bus for Easy PC Interface Secure Hardware and Firmware Design True Random Number Generator (RNG) – FIPS 140.2 compliant Secure Real-time Clock Option 3.3V ±10% Supply Voltage 28-lead TSSOP Package or 40-lead QFN Package 0–70°C Temperature Range
Description
The AT97SC3203 Trusted Platform Module (TPM) is the latest offering from Atmel, the world's leading choice for TPMs. Atmel, supplier of the world's first production v1.1b TPM, the AT97SC3201, expands its success into v1.2 TPMs with the AT97SC3203. Atmel continues to pace the development of TPM technology and actively participates in the Trusted Computing Group (TCG) and contributes expertise in the development of the TPM specificat ions. By utilizing Atmel TPMs, you can be confident that you are implementing the most advanced TPMs available on the market today and in the future. The AT97SC3203 is a fully integrated security module designed to be integrated into personal computers and othe r embedded systems. It implements version 1.2 of the Trusted Computing Group specification for Trusted Platform Modules. The TPM includes a cryptographic accelerator capable of computing a 2048-bit RSA signature in 500 ms and a 1024-bit RSA signature in 100 ms. Performance of the SHA-1 accelerator is L50 µs per 64-byte block. In most cases, TCG key generation operations will be completed using a proprietary mechanism in less than 1 msec. The chip communicates with the PC through the LPC interface. The TPM supports SIRQ (for interrupts) and CLKRUN to perm it clock stopping for power savings in mobile computers. Trusted Platform Module AT97SC3203 Summary Advance Information Rev. 5116AS-TPM–7/05
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Figure 1. AT97SC3203 Block Diagram Figure 2. Atmel AT97SC3203 TPM Pin Configuration
33 MHz
Table 1. Pin Descriptions LFRAME# 22 26 Input LPC frame: Indicates th e start of an LPC cycle, or an abort. tied to the 3V power supply pin through a resistor. this pin is unused, it should be tied to ground. LRESET# 16 20 Input PCI signal to reset all devices that reside on the PCI bus. motherboard. May be referred to as Vcc. resistor. Reserved for the SMBus Data I/O function. resistor. Reserved for the SMBus Clock Input function. the GPIO-Express-00. Default TPM configuration: GPIO Input. GPIO6 also serves as the XOR chain Output during I/O test mode. should be tied to the 3V power supply directly or through a resistor.
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Notes: 1. These parameters guaranteed by design. the pin should be tied directly to the 3V power supply pin. should be tied to ground if not used. XtalO 14 13 Output 32 kHz Crystal Oscillator Output. extended periods may affect device reliability. Table 2. DC Parameters (Preliminary) Table 1. Pin Descriptions (Continued)
Notes: 1. These parameters guaranteed by design.
- All parameters measured with respect to signal crossing Vtest = 0.4 * VCC unless otherwise noted.
- The minimum parameter must never be violated under any ci rcumstances unless Lreset# is asserted. If proper CLKRUN#
signaling is observed, the maximum specification can be violated. Notes: 1. Current as of publication date. Contact Atmel marketing for status update. Table 3. AC Parameters Table 4. Ordering Information
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5116AS-TPM–7/05 Package Drawing 28A3 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 1/8/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 9.60 9.70 9. 80 2, 5 E 8.10 BSC E1 6.00 6.10 6.20 3, 5 A – – 1.20 A2 0. 80 1.00 1.05 b 0.19 – 0. 30 4 e 0.65 B SC L 0.45 0.60 0.75 L1 1.00 REF 28A3, 28-lead, 6.1 x 9.7 mm Body, 0.65 pitch, Thin Shrink Small Outline Package (TSSOP) Notes: 1. Thi s drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information. 2. Dimen sion D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimen sion E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimen sion b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimen sion at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protr usion and adjacent lead is 0.07 mm. 5. Dimen sion D and E1 to be determined at Datum Plane H. 28A3 A A L D A2 E E1 e b Top View Side View End View
5116AS-TPM–7/05 40ML1 – QFN San Jose, CA 95131 TITLE DRAWING NO. R REV. A Side View 40ML1, 40-lead 6.0 x 6.0 mm Body, 0.50 mm Pitch, Molded Quad Flat No Lead Package (MLF2) A40ML1 3/9/04 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation WJJD-2, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 6.00 BSC E 6.00 BSC D2 3.95 4.10 4.25 E2 3.95 4.10 4.25 A - 0.85 0.90 A1 0.0 0.01 0.05 A2 - 0.65 0.70 A3 0.20 REF L 0.30 0.40 0.50 e 0.50 BSC b 0.18 0.23 0.30 2 D E Top View N Pin 1 Indicator L PIN1 ID b N e Bottom View
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