AT93C86A_0702 ATMEL

Document overview

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  • PDF pages: 15

Technical content

Features

  • Medium-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V)
  • Automotive Temperature Range –40°C to +125°C
  • User Selectable Internal Organization – 16K: 2048 x 8 or 1024 x 16
  • 3-wire Serial Interface
  • Sequential Read Operation
  • Schmitt Trigger, Filtered Inputs for Noise Suppression
  • 2 MHz Clock Rate (5V) Compatibility
  • Self-timed Write Cycle (10 ms max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
  • Lead-Free/Halogen-Free Devices Available
  • 8-lead JEDEC SOIC and 8-lead TSSOP Packages

Description

The AT93C86A provides 16384 bits of serial electrically erasable programmable read only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin is connected to V CC and 2048 words of 8 bits each when it is tied to ground. The device is optimized for use in many auto motive applications where low-power and low-voltage operations are essential. The AT93C86A is available in space saving 8- lead JEDEC SOIC and 8-lead TSSOP packages. Table 1. Pin Configuration

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AT93C86A is available in a 2.7V to 5.5V version. Figure 1. Block Diagram Meg ohm pullup, then the x 16 organization is selected.

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 2. Pin Capacitance(1) Table 3. DC Characteristics

2.0 V CC + 1 V

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Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics

1 MHz

5096D–SEEPR–2/07 Functional The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host pro- cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the appropriate Op Code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the mem- ory location to be read. After the instruction and address are decoded, data from the selected memory location is available at th e serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A sup- ports sequential read o perations. The device will automa tically increment the internal address pointer and clock out the next memory location as long as CS is held high. In this case, the dummy bit (logic “0”) will no t be clocked out betw een memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or V CC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction pr ograms all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory loca tion. The self-timed programming cycle t WP starts after the last bit of data is received at se rial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the Table 5. Instruction Set for the AT93C86A ERASE 1 11 A 10 – A0 A9 – A0 Erases memory location An – A0. WRITE 1 01 A 10 – A0 A9 – A0 D7 – D0 D15 – D0 Writes memory location An – A0. ERAL 1 00 10XXXXXXXX 10XXXXXXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. WRAL 1 00 01XXXXXXXX 01XXXXXXXX D 7 – D0 D15 – D0 Writes all memory locations. EWDS 1 00 00XXXXXXXX 00XXXXXXXX Disables a ll programming instructions.

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5096D–SEEPR–2/07 data pattern contained in the instruction and th e part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the self- timed programming cycle tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem- ory array to the logic “1” state and is prim arily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The Eral instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS). The Wral instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the Ewen and Ewds instructions and can be executed at any time.

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Figure 4. EWEN Timing Figure 5. EWDS Timing Figure 6. WRITE Timing

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Figure 9. ERAL Timing(1) Note: 1. Valid only at V CC = 4.5V to 5.5V.

5096D–SEEPR–2/07 Ordering Code Package Operation Range AT93C86A-10SQ-2.7 AT93C86A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

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5096D–SEEPR–2/07 Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 3/17/05 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 θ 0˚ – 8˚ ØØ EE NN TOP VIEWTOP VIEW CC E1E1 END VIEW AA bb LL A1A1 ee DD SIDE VIEWSIDE VIEW

5096D–SEEPR–2/07 8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

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5096D–SEEPR–2/07

Revision History

Doc. Rev. Date Comments 5096D 2/2007 Removed PDIP package offering Removed Pb’d part numbers 5096C 9/2006 Revision history implement ed; Removed ‘Preliminary’ status from datasheet.

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