AT93C86A_08 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 14

Technical content

  1. Features
  • Medium-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V)
  • Automotive Temperature Range –40°C to +125°C
  • User Selectable Internal Organization – 16K: 2048 x 8 or 1024 x 16
  • 3-wire Serial Interface
  • Sequential Read Operation
  • Schmitt Trigger, Filtered Inputs for Noise Suppression
  • 2 MHz Clock Rate (5V) Compatibility
  • Self-timed Write Cycle (10 ms max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
  • Lead-Free/Halogen-Free Devices Available
  • 8-lead JEDEC SOIC and 8-lead TSSOP Packages 2. Description The AT93C86A provides 16384 bits of serial electrically erasable programmable read only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin is connected to V CC and 2048 words of 8 bits each when it is tied to ground. The device is optimized for use in many auto motive applications where low-power and low-voltage operations are essential. The AT93C86A is available in space saving 8- lead JEDEC SOIC and 8-lead TSSOP packages. The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instru ction at DI, the address is decoded and the data is clocked out serially on the data out put pin DO. The write cycle is completely self-timed and no separate erase cycle is required before Write. The write cycle is only enabled when the part is in the Erase/Writ e Enable state. When CS is brought “high” following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C86A is available in a 2.7V to 5.5V version. Table 2-1. Pin Configuration Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply ORG Internal Organization DC Don’t Connect Three-wire Automotive Temperature Serial EEPROM 16K (2048 x 8 or 1024 x 16) AT93C86A Rev. 5096E–SEEPR–1/08 8-lead SOIC CS SK DI DO VCC DC ORG GND 8-lead TSSOP CS SK DI DO VCC DC ORG GND

5096E–SEEPR–1/08 AT93C86A Figure 2-1. Block Diagram Note: When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. Note: 1. This parameter is characterized and is not 100% tested. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on any Pin ADDRESS DECODER OUTPUT BUFFER DO ORG DI CS SK Vcc GND CLOCK GENERATOR MODE DECODE LOGIC DATA REGISTER MEMORY ARRAY 2048 x 8 OR 1024 x 16 Table 2-2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions Max Units Conditions COUT Output Capacitance (DO) 5 pF V OUT = 0V CIN Input Capacitance (CS, SK, DI) 5 pF V IN = 0V

5096E–SEEPR–1/08 AT93C86A Note: 1. V IL min and VIH max are reference only and are not tested. Table 2-3. DC Characteristics Applicable over recommended operating range from: T A = –40°C to +125 °C, VCC = +2.7V to +5.5V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Unit VCC1 Supply Voltage 2.7 5.5 V VCC2 Supply Voltage 4.5 5.5 V ICC Supply Current V CC = 5.0V READ at 1.0 MHz 0.5 2.0 mA WRITE at 1.0 MHz 0.5 2.0 mA ISB1 Standby Current V CC = 2.7V CS = 0V 6.0 10.0 µA ISB2 Standby Current V CC = 5.0V CS = 0V 10.0 15.0 µA IIL Input Leakage V IN = 0V to VCC 0.1 3.0 µA IOL Output Leakage V IN = 0V to VCC 0.1 3.0 µA VIL1 (1) VIH1 (1) Input Low Voltage Input High Voltage 2.7V ≤ VCC ≤ 5.5V −−−−0.6 0.8 V

2.0 V CC + 1 V

Output High Voltage 2.7V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V IOH = –0.4 mA 2.4 V Table 2-4. AC Characteristics Applicable over recommended operating range from TA = –40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units fSK SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V

1 MHz

tSKH SK High Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 50 ns tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 100 ns tCSH CS Hold Time Relative to SK 0 ns tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 100 ns tPD1 Output Delay to ‘1’ AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 500 ns tPD0 Output Delay to ‘0’ AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 500 ns

5096E–SEEPR–1/08 AT93C86A Note: 1. This parameter is characterized and is not 100% tested. tSV CS to Status Valid AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tDF CS to DO in High Impedance AC Test CS = VIL 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 150 ns tWP Write Cycle Time 2.7V ≤ VCC ≤ 5.5V 0.1 4 10 ms Endurance(1) 5.0V, 25°C 1M Write Cycles Table 2-4. AC Characteristics (Continued) Applicable over recommended operating range from TA = –40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units Table 2-5. Instruction Set for the AT93C86A Instruction SB Op Code Address Data Commentsx 8 x 16 x 8 x 16 READ 1 10 A 10 – A0 A9 – A0 Reads data stored in memory, at specified address. EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write enable must precede all programming modes. ERASE 1 11 A 10 – A0 A9 – A0 Erases memory location An – A0. WRITE 1 01 A 10 – A0 A9 – A0 D7 – D0 D15 – D0 Writes memory location An – A0. ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. WRAL 1 00 01XXXXXXXXX 01XXXXXXXX D 7 – D0 D15 – D0 Writes all memory locations. Valid when VCC = 4.5V to 5.5V and Disable Register cleared. EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Disabl es all programming instructions.

5096E–SEEPR–1/08 AT93C86A 3. Functional Description The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven inst ructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the appropriate Op Code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the memory loca- tion to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pi n DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A suppor ts sequential read operations. The device will automatically increment the internal address point er and clock out the next memory location as long as CS is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE (EWEN): To assure data integr ity, the part automatic ally goes into the Erase/Write Disable (EWDS) state when power is first app lied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruc- tion is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction program s all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Read y/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts after the last bit of data is received at serial data input pin DI . The DO pin outputs the Ready/Busy status of the part if CS is brought high after bei ng kept low for a minimum of 250 ns (t CS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The Eral instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS). The Wral instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be exe- cuted after all programming operations. The operat ion of the Read instruction is independent of both the Ewen and Ewds instructions and can be executed at any time.

5096E–SEEPR–1/08 AT93C86A Figure 4-8. ERAL Timing(1) Note: 1. Valid only at V CC = 4.5V to 5.5V. D

5096E–SEEPR–1/08 AT93C86A 5. AT93C86A Ordering Information Ordering Code Package Operation Range AT93C86A-10SQ-2.7 AT93C86A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

5096E–SEEPR–1/08 AT93C86A 6. Packaging Information 6.1 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 3/17/05 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 θ 0° – 8° ØØ EE NN TOP VIEW CC E1E1 END VIEW AA bb LL A1A1 ee DD SIDE VIEW

5096E–SEEPR–1/08 AT93C86A 6.2 8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

5096E–SEEPR–1/08 AT93C86A 7. Revision History Doc. Rev. Date Comments 5096E 1/2008 Moved to new template Replaced Table 5 with correct version 5096D 2/2007 Removed PDIP package offering Removed Pb’d part numbers 5096C 9/2006 Revision history implemented; Removed ‘Preliminary’ status from datasheet.

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