AT93C56A_06 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 20

Technical content

Features

  • Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)
  • User-selectable Internal Organization – 2K: 256 x 8 or 128 x 16 – 4K: 512 x 8 or 256 x 16
  • Three-wire Serial Interface
  • Sequential Read Operation
  • 2 MHz Clock Rate (5V)
  • Self-timed Write Cycle (10 ms Max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
  • Automotive Devices Available
  • 8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP and 8-ball dBGA2 Packages

Description

The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program- mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each (when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C56A/66A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, 8- lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball dBGA2 packages. The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a read instruct ion at DI, the address is decoded and the data is clocked out serially on the data outp ut pin DO. The write cycle is completely self-timed and no separate erase cycle is required before write. The write cycle is only enabled when the part is in the Erase/Writ e Enable State. When CS is brought “high” following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. Table 1. Pin Configurations

2 AT93C56A/66A

Figure 1. Block Diagram Meg ohm pullup, then the x 16 organization is selected.

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 2. Pin Capacitance(1) Table 3. DC Characteristics

4 AT93C56A/66A

Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics

Note: The X’s in the address field represent don’t care values and must be clocked. ory locations, thus allowing for a continuous stream of data to be read. CC power is removed from the part. Table 5. Instruction Set for the AT93C56A and AT93C66A ERASE 1 11 A 8 – A0 A7 – A0 Erases memory location An – A0. WRITE 1 01 A 8 – A0 A7 – A0 D7 – D0 D15 – D0 Writes memory location An – A0.

6 AT93C56A/66A

the self-timed programming cycle tWP. minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. The WRAL instruction is valid only at VCC = 5.0V ± 10%. Figure 2. Synchronous Data Timing Note: 1. This is the minimum SK period.

8 AT93C56A/66A

Figure 6. WRITE Timing Figure 7. WRAL Timing(1) Note: 1. Valid only at V CC = 4.5V to 5.5V. Figure 8. ERASE Timing

Figure 9. ERAL Timing(1) Note: 1. Valid only at V CC = 4.5V to 5.5V.

10 AT93C56A/66A

3378K–SEEPR–12/06 2. “U” designates Green package + RoHS compliant. 3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT93C56A-10PU-2.7(2) AT93C56A-10PU-1.8(2) AT93C56A-10SU-2.7(2) AT93C56A-10SU-1.8(2) AT93C56AW-10SU-2.7(2) AT93C56AW-10SU-1.8(2) AT93C56A-10TU-2.7(2) AT93C56A-10TU-1.8(2) AT93C56AU3-10UU-1.8(2) AT93C56AY1-10YU-1.8(2) (Not recommended for new design) AT93C56AY6-10YH-1.8(3) 8P3 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8U3-1 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) AT93C56A-W1.8-11 (4) Die Sales Industrial Temperature (−40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8U3-1 8-ball, die Ball Grid Array Package (dBGA2) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm) Options −2.7 Low-voltage (2.7V to 5.5V) −1.8 Low-voltage (1.8V to 5.5V)

3378K–SEEPR–12/06 2. “U” designates Green package + RoHS compliant. 3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT93C66A-10PU-2.7(2) AT93C66A-10PU-1.8(2) AT93C66A-10SU-2.7(2) AT93C66A-10SU-1.8(2) AT93C66AW-10SU-2.7(2) AT93C66AW-10SU-1.8(2) AT93C66A-10TU-2.7(2) AT93C66A-10TU-1.8(2) AT93C66AU3-10UU-1.8(2) AT93C66AY1-10YU-1.8(2) (Not recommended for new design) AT93C66AY6-10YH-1.8(3) 8P3 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8U3-1 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) AT93C66A-W1.8-11 (4) Die Sale Industrial Temperature (−40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8U3-1 8-ball, die Ball Grid Array Package (dBGA2) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm) Options −2.7 Low-voltage (2.7V to 5.5V) −1.8 Low-voltage (1.8V to 5.5V)

12 AT93C56A/66A

3378K–SEEPR–12/06 Packaging Information 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D E e Lb2 b A2 A N eA c

4 PLCS

(Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2

3378K–SEEPR–12/06 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

14 AT93C56A/66A

3378K–SEEPR–12/06 8S2 – EIAJ SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) 10/7/03 8S2 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 2, 3 E 7.70 8.26 L 0.51 0.85 ∅ 0˚ 8˚ e 1.27 BSC 4 End View Side View e b A D E N C L Top View

3378K–SEEPR–12/06 8Y1 - MAP A – – 0.90 A1 0.00 – 0.05 D 4.70 4.90 5.10 E 2.80 3.00 3.20 D1 0.85 1.00 1.15 E1 0.85 1.00 1.15 b 0.25 0.30 0.35 e 0.65 TYP L 0.50 0.60 0.70 PIN 1 INDEX AREA D E A A1 b 8 7 6 e L PIN 1 INDEX AREA 1 2 34 A Top View End View Bottom View Side View San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 C8Y1 2/28/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

16 AT93C56A/66A

3378K–SEEPR–12/06 8Y6 - Mini-MAP (MLP 2x3) San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) C8Y6 8/26/05 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 E2 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 A3 0.20 REF L 0.20 0.30 0.40 e 0.50 BSC b 0.20 0.25 0.30 2 b (8X) Pin 1 ID Pin 1 Index Area D E A L (8X) e (6X) 1.50 REF.

3378K–SEEPR–12/06 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

18 AT93C56A/66A

3378K–SEEPR–12/06 8U3-1 – dBGA2 TITLE DRAWING NO. R REV.1150E Cheyenne Mt. Blvd Colorado Springs, CO 80906 PO8U3-1 b 5/3/05 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.713 0.79 0.85 A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 b 0.20 0.25 0.30 2 D 1.50 BSC E 2.00 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) bD E A Bottom View

8 Solder Balls

  1. This drawing is for general information only. 2. Dimension ‘b’ is measured at maximum solder ball diameter e 678 d (e1) (d1)

3378K–SEEPR–12/06

Revision History

Revision No. Date Comments 3378K 12/06 Removed DC/Don’t Connect and replaced with NC/No Conenct Adjusted size of Block diagram on pg. 2 Made all diagrams on pages 6-9 consistently the same size Corrected 8U3-1

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