AT93C46A_07 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 14

Technical content

Features

  • Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V)
  • Three-wire Serial Interface
  • 2 MHz Clock Rate Compatibility
  • Self-timed Write Cycle (10 ms max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
  • Lead-free/Halogen-free Devices Available
  • 8-lead JEDEC SOIC and 8-lead TSSOP Packages

Description

The AT93C46A provides 1024 bits of serial electrically-erasable programmable read- only memory (EEPROM) organized as 64 word s of 16 bits each. The device is opti - mized for use in many automotive applications where low-power and low-voltage operation are essential. The AT93C46A is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT93C46A is enabled through the Chip Select pin (CS) and accessed via a three- wire serial interface consisting of Data In put (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The write cycle is completely self-timed and no separate erase cycle is required befor e write. The write cycle is only enabled when the part is in the erase/write enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the ready/busy status of the part. The AT93C46A is available in 2.7V to 5.5V versions. Table 1. Pin Configuration

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Figure 1. Block Diagram

Note: This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 2. Pin Capacitance Table 3. DC Characteristics

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Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics

5089B–SEEPR–2/07 Functional The AT93C46A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host pro- cessor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the mem- ory location to be read. After the instruction and address are decoded, data from the selected memory location is available at th e serial output pin DO . Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 16-bit data output string. ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or V CC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction pr ograms all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS). A logic “1” at pin DO indicates that the selected memory location has been erased and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contai ns the 16 bits of data to be writ- ten into the specified memory location. The self-timed programming cycle, t WP, starts after the last bit of data is received at se rial data input pin DI. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and th e part is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought high after the end of the self- timed programming cycle, tWP. ERASE ALL (ERAL): The Erase All (ERAL) instructio n programs every bit in the mem- ory array to the logic “1” state and is prim arily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY Table 5. Instruction Set for the AT93C46A READ 1 10 A 5 − A0 Reads data stored in memory, at specified address. EWEN 1 00 11XXXX Write enable must precede all programming modes. ERASE 1 11 A 5 − A0 Erase memory location An − A0. WRITE 1 01 A 5 − A0 Writes memory location An − A0. ERAL 1 00 10XXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. WRAL 1 00 01XXXX Writes all memory locations. Valid only at V CC = 4.5V to 5.5V. EWDS 1 00 00XXXX Disables all programming instructions.

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status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%. Figure 2. Synchronous Data Timing Note: 1. This is the minimum SK period. Table 6. Organization Key for Timing Diagrams

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Figure 6. WRITE Timing Figure 7. WRAL Timing(1,2) Notes: 1. Valid only at V CC = 4.5V to 5.5V.

  1. Requires a minimum of nine clock cycles.

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5089B–SEEPR–2/07

Ordering Information

Ordering Code Package Operation Range AT93C46A-10SQ-2.7 AT93C46A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free/ Extended Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

5089B–SEEPR–2/07 Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

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5089B–SEEPR–2/07 8A2 –TSSOP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

5089B–SEEPR–2/07

Revision History

Doc. Rev. Date Comments 5089B 1/2007 Implemented revision history Removed PDIP package offering Removed Pb’d parts

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