AT91SAM9261S-CJ

AT91SAM9261S_1 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 709

Technical content

Features

• Incorporates the ARM926EJ-S™ ARM ® Thumb® Processor – DSP Instruction Extensions – ARM Jazelle ® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit – EmbeddedICE ™ , Debug Communication Channel Support – Mid-level implementation Embedded Trace Macrocell™  Additional Embedded Memories – 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed – 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed  External Bus Interface (EBI) – Supports SDRAM, Static Memory, NAND Flash and CompactFlash®  LCD Controller – Supports Passive or Active Displays – Up to 16-bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048  USB – USB 2.0 Full Speed (12 Mbits per second) Host Double Port  Dual On-chip Transceivers  Integrated FIFOs and Dedicated DMA Channels – USB 2.0 Full Speed (12 Mb its per second) Device Port  On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs  Bus Matrix – Handles Five Masters and Five Slaves – Boot Mode Select Option – Remap Command  Fully Featured System Controller (SYSC) for Efficient System Management, including – Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer – Three 32-bit PIO Controllers  Reset Controller (RSTC) – Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control  Shutdown Controller (SHDWC) – Programmable Shutdown Pin Control and Wake-up Circuitry  Clock Generator (CKGR) – 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator and two PLLs  Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals AT91 ARM Thumb-based Microcontrollers AT91SAM9261S 6242E–ATARM–11-Sep09

6242E–ATARM–11-Sep09 AT91SAM9261S  Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected  Debug Unit (DBGU) – 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose Two-wire UART Serial Communication  Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter  Watchdog Timer (WDT) – Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock  Real-Time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock  Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Ca pability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output  Nineteen Peripheral DMA (PDC) Channels  Multimedia Card Interface (MCI) – SDCard and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant  Three Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer  Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support  Two Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects  One Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability  Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel EEPROMs Supported  IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins  Required Power Supplies: – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)  Available in a 217-ball LFBGA RoHS-compliant Package

6242E–ATARM–11-Sep09 AT91SAM9261S 1. Description The AT91SAM9261S is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261S is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 16 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates con- trollers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261S integrates a ROM-based Boot Loader supporting code shadowing from, for example, external DataFlash ® into external SDRAM. The software controlled Power Manage- ment Controller (PMC) keeps system power c onsumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261S also benefits from the integration of a wide range of debug features includ- ing JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applic ations, especially those with real-time constraints.

6242E–ATARM–11-Sep09 AT91SAM9261S 2. Block Diagram Figure 2-1. AT91SAM9261S Block Diagram PIO ID SSC0 SSC1 SSC2 Timer Counter TC0 TC1 TC2 TWI LCD Controller DMA FIFO LUT DMA FIFO USB Host FIFO USB Device ARM926EJ-S Core JTAG Boundary Scan ICE AIC Fast SRAM 16K bytes PIO Instruction Cache 16K bytes Fast ROM 32K bytes Peripheral Bridge Peripheral DMA Controller PLLA PLLB PMC RSTC OSC PIOA PIOB PIOC RTT SHDWC POR OSC WDT GPBREG PIT POR EBI Static Memory Controller PIO Data Cache 16K bytesMMU PIO 5-layer Matrix CompactFlash NAND Flash SDRAM Controller BIU PIO PIO TransceiverTransceiver PDC PDC PDC APB DBGU MCI USART0 USART1 USART2 SPI0 SPI1 PDC PDC PDC PDC PDC PDC PDC System Controller TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK LCDD0-LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC MCCK MCCDA MCDA0-MCDA3 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK D0-D15 A0/NBS0 A2-A15/A18-A21 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 A23-A24 NCS5/CFCS1 BMS NCS2 A25/CFRNW NCS4/CFCS0 NCS6/NANDOE NCS7/NANDWE D16-D31 A1/NBS2/NWR2 NWAIT HDMA HDPB HDPA HDMB DDM DDP CFCE1 CFCE2 JTAGSEL TDI TDO RTCK TMS TCK NTRST FIQ IRQ0-IRQ2 PLLRCB PLLRCA DRXD DTXD XIN32 XOUT32 NRST PCK0-PCK3 SHDN WKUP GNDBU XIN XOUT VDDBU VDDCORE TST A22/REG

6242E–ATARM–11-Sep09 AT91SAM9261S 3. Signal Description Table 3-1. Signal Description by Peripheral Signal Name Function Type Active Level Comments Power VDDIOM EBI I/O Lines Power Supply Power 1.65 V to 1.95V and 3.0V to 3.6V VDDIOP Peripherals I/O Lines Power Supply Power 2.7V to 3.6V VDDBU Backup I/O Lines Power Supply Power 1.08V to 1.32V VDDPLL PLL Power Supply Power 3.0V to 3.6V VDDOSC Oscillator Power Supply Power 3.0V to 3.6V VDDCORE Core Chip Power Supply Power 1.08V to 1.32V GND Ground Ground GNDPLL PLL Ground Ground GNDOSC Oscillator Ground Ground GNDBU Backup Ground Ground Clocks, Oscillators and PLLs XIN Main Oscillator Input Input XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output PLLRCA PLL Filter Input PLLRCB PLL Filter Input PCK0 - PCK3 Programmable Clock Output Output Shutdown, Wakeup Logic SHDN Shutdown Control Output Do not tie over VDDBU. WKUP Wake-Up Input Input Accepts between 0V and VDDBU. ICE and JTAG TCK Test Clock Input No pull-up resistor. RTCK Returned Test Clock Output No pull-up resistor. TDI Test Data In Input No pull-up resistor. TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor. NTRST Test Reset Signal Input Low Pull-up resistor. JTAGSEL JTAG Selection Input Pull-down resistor. Accepts between 0V and VDDBU. Reset/Test NRST Microcontroller Reset I/O Low Pull-up resistor TST Test Mode Select Input Pull-down resistor. BMS Boot Mode Select Input Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

6242E–ATARM–11-Sep09 AT91SAM9261S AIC IRQ0 - IRQ2 External Interrupt Inputs Input FIQ Fast Interrupt Input Input PIO PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset PB0 - PB31 Parallel IO Controller B I/O Pulled-up input at reset PC0 - PC31 Parallel IO Controller C I/O Pulled-up input at reset EBI D0 - D31 Data Bus I/O Pulled-up input at reset A0 - A25 Address Bus Output 0 at reset NWAIT External Wait Signal Input Low SMC NCS0 - NCS7 Chip Select Lines Output Low NWR0 - NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0 - NBS3 Byte Mask Signal Output Low CompactFlash Support CFCE1 - CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash IO Read Output Low CFIOW CompactFlash IO Write Output Low CFRNW CompactFlash Read Not Write Output CFCS0 - CFCS1 CompactFlash Ch ip Select Lines Output Low NAND Flash Support NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDCS NAND Flash Chip Select Output Low SDRAM Controller SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BA0 - BA1 Bank Select Output SDWE SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output Multimedia Card Interface MCCK Multimedia Card Clock Output MCCDA Multimedia Card A Command I/O MCDA0 - MCDA3 Multimedia Card A Data I/O Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function Type Active Level Comments

6242E–ATARM–11-Sep09 AT91SAM9261S USART SCK0 - SCK2 Serial Clock I/O TXD0 - TXD2 Transmit Data Output RXD0 - RXD2 Receive Data Input RTS0 - RTS2 Request To Send Output CTS0 - CTS2 Clear To Send Input Synchronous Serial Controller TD0 - TD2 Transmit Data Output RD0 - RD2 Receive Data Input TK0 - TK2 Transmit Clock I/O RK0 - RK2 Receive Clock I/O TF0 - TF2 Transmit Frame Sync I/O RF0 - RF2 Receive Frame Sync I/O Timer/Counter TCLK0 - TCLK2 External Clock Input Input TIOA0 - TIOA2 I/O Line A I/O TIOB0 - TIOB2 I/O Line B I/O SPI SPI0_MISO - SPI1_MISO Master In Slave Out I/O SPI0_MOSI - SPI1_MOSI Master Out Slave In I/O SPI0_SPCK - SPI1_SPCK SPI Serial Clock I/O SPI0_NPCS0, SPI1_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPI0_NPCS1 - SPI0_NPCS3 SPI1_NPCS1 - SPI1_NPCS3 SPI Peripheral Chip Select Output Low Two-Wire Interface TWD Two-wire Serial Data I/O TWCK Two-wire Serial Clock I/O LCD Controller LCDD0 - LCDD23 LCD Data Bus Output LCDVSYNC LCD Vertical Synchronization Output LCDHSYNC LCD Horizontal Synchronization Output LCDDOTCK LCD Dot Clock Output LCDDEN LCD Data Enable Output LCDCC LCD Contrast Control Output USB Device Port DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function Type Active Level Comments

6242E–ATARM–11-Sep09 AT91SAM9261S USB Host Port HDMA USB Host Port A Data - Analog HDPA USB Host Port A Data + Analog HDMB USB Host Port B Data - Analog HDPB USB Host Port B Data + Analog Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function Type Active Level Comments

6242E–ATARM–11-Sep09 AT91SAM9261S

4.2 Pinout

Note: 1. Shaded cells define the pins powered by VDDIOM. Table 4-1. AT91SAM9261S Pinout for 217-ball LFBGA Package (1) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 A19 D5 VDDCORE J14 VDDIOP P17 PA20 A2 A16/BA0 D6 A10 J15 PB9 R1 PC19 A3 A14 D7 A5 J16 PB6 R2 PC21 A4 A12 D8 A0/NBS0 J17 PB4 R3 GND A5 A9 D9 SHDN K1 D6 R4 PC27 A6 A6 D10 NC K2 D8 R5 PC29 A7 A3 D11 VDDIOP K3 D10 R6 PC4 A8 A2 D12 PB29 K4 D7 R7 PC8 A9 NC D13 PB28 K8 GND R8 PC12 A10 XOUT32 D14 PB23 K9 GND R9 PC14 A11 XIN32 D15 PB20 K10 GND R10 VDDPLL A12 DDP D16 PB17 K14 VDDCORE R11 PA0 A13 HDPB D17 TCK K15 PB3/BMS R12 PA7 A14 HDMB E1 NWR1/NBS1/CFIOR K16 PB1 R13 PA10 A15 PB27 E2 NWR0/NWE/CFWE K17 PB2 R14 PA13 A16 GND E3 NRD/CFOE L1 D9 R15 PA17 A17 PB24 E4 SDA10 L2 D11 R16 GND B1 A20 E14 PB22 L3 D12 R17 PA18 B2 A18 E15 PB18 L4 VDDIOM T1 PC20 B3 A15 E16 PB15 L14 PA30 T2 PC23 B4 A13 E17 TDI L15 PA27 T3 PC26 B5 A11 F1 SDCKE L16 PA31 T4 PC2 B6 A7 F2 RAS L17 PB0 T5 VDDIOP B7 A4 F3 NWR3/NBS3/CFIOW M1 D13 T6 PC5 B8 A1/NBS2/NWR2 F4 NCS0 M2 D15 T7 PC9 B9 VDDBU F14 PB16 M3 PC18 T8 PC10 B10 JTAGSEL F15 NRST M4 VDDCORE T9 PC15 B11 WKUP F16 TDO M14 PA25 T10 VDDOSC B12 DDM F17 NTRST M15 PA26 T11 GNDOSC B13 PB31 G1 D0 M16 PA28 T12 PA1 B14 HDMA G2 D1 M17 PA29 T13 PA4 B15 PB26 G3 SDWE N1 D14 T14 PA6 B16 PB25 G4 NCS3/NANDCS N2 PC17 T15 PA8 B17 PB19 G14 PB14 N3 PC31 T16 PA11 C1 A22 G15 PB12 N4 VDDIOM T17 PA14 C2 A21 G16 PB11 N14 PA22 U1 PC25 C3 VDDIOM G17 PB8 N15 PA21 U2 PC0 C4 A17/BA1 H1 D2 N16 PA23 U3 PC3 C5 VDDIOM H2 D3 N17 PA24 U4 GND C6 A8 H3 VDDIOM P1 PC16 U5 PC6 C7 GND H4 SDCK P2 PC30 U6 VDDIOP C8 VDDIOM H8 GND P3 PC22 U7 GND C9 GNDBU H9 GND P4 PC24 U8 PC13 C10 TST H10 GND P5 PC28 U9 PLLRCB C11 GND H14 PB10 P6 PC1 U10 PLLRCA C12 HDPA H15 PB13 P7 PC7 U11 XIN C13 PB30 H16 PB7 P8 PC11 U12 XOUT C14 NC H17 PB5 P9 GNDPLL U13 PA2 C15 VDDIOP J1 D4 P10 PA3 U14 PA5 C16 PB21 J2 D5 P11 VDDIOP U15 PA12 C17 TMS J3 GND P12 VDDCORE U16 PA9 D1 NCS2 J4 CAS P13 PA15 U17 RTCK D2 NCS1/SDCS J8 GND P14 PA16 D3 GND J9 GND P15 VDDIOP D4 VDDIOM J10 GND P16 PA19

6242E–ATARM–11-Sep09 AT91SAM9261S 5. Power Considerations

5.1 Power Supplies

The AT91SAM9261S has six types of power supply pins:  VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal.  VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to  VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V and 3.6V, 3.3V nominal.  VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal.  VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal.  VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Sep- arated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are GNDBU, GNDOSC and GNDPLL, respectively.

5.2 Power Consumption

The AT91SAM9261S consumes about 550 µA of static current on VDDCORE at 25°C. This static current rises at up to 5.5 mA if the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C. For dynamic power consumption, the AT91SAM9261S consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditi ons (1.2V, 25°C), processor running full-perfor- mance algorithm. 6. I/O Line Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low level. It integrates a permanent pull-up resistor of about 15 k Ω to VDDIOP, so that it can be left unconnected for normal operations.

6242E–ATARM–11-Sep09 AT91SAM9261S

6.2 Test Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma- nent pull-down resistor of about 15 k Ω to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.

6.3 Reset Pin

NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can be left unconnected in case no reset from the system needs to be applied to the product. The NRST pin integrates a permanent pull-up resistor of 100 kΩ minimum to VDDIOP. The NRST signal is inserted in the Boundary Scan.

6.4 PIO Controller A, B and C Lines

All the I/O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up resistor of 100 kΩ. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs wi th pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables.

6.5 Shutdown Logic Pins

The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.

6242E–ATARM–11-Sep09 AT91SAM9261S 7. Processor and Architecture

7.1 ARM926EJ-S Processor

 RISC Processor Based on ARM v5TEJ Archit ecture with Jazelle technology for Java acceleration  Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set  DSP Instruction Extensions  5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W)  16 Kbyte Data Cache, 16 Kbyte Instruction Cache – Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement  Write Buffer – Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain  Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 embedded domains  Bus Interface Unit (BIU) – Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete AHB system flexibility – Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)

6242E–ATARM–11-Sep09 AT91SAM9261S

7.2 Debug and Test Features

 Integrated Embedded In-circuit Emulator Real-Time – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel  Debug Unit –T w o - p i n U A R T – Debug Communication Channel Interrupt Handling – Chip ID Register  IEEE1149.1 JTAG Boundary-scan on All Digital Pins

7.3 Bus Matrix

 Five Masters and Five Slaves handled – Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst Breaking with Slot Cycle Limit  One Address Decoder Provided per Master – Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap.  Boot Mode Select Option – Non-volatile Boot Memory can be Internal or External. – Selection is made by BMS pin sampled at reset.  Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors

7.4 Peripheral DMA Controller

 Transfers from/to peripheral to/from any memory space without intervention of the processor.  Next Pointer Support, forbids strong real-time constraints on buffer management.  Nineteen channels – Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Multimedia Card Interface

6242E–ATARM–11-Sep09 AT91SAM9261S 8. Memories Figure 8-1. AT91SAM9261S Memory Mapping ROM 16K Bytes 16K Bytes 0xFFFC 0000 16K Bytes 0xFFFC 4000 SPI1 0xFFFC C000 SPI0 16K Bytes 0xFFFC 8000 16K Bytes 16K Bytes 16K Bytes 0xFFFA 4000 TCO, TC1, TC2 0xFFFA 8000 MCI 0xFFFB 0000 0xFFFB 4000 USART0 0xFFFB C000 USART1 0xFFFA 0000 0xFFFA C000 USART2 16K Bytes TWI 16K Bytes 16K Bytes 0xFFFB 8000 16K Bytes 16K Bytes UDP SSC0 256M Bytes 0x1000 0000 0x0000 0000 0x0FFF FFFF 0xFFFF FFFF 0xF000 0000 0xEFFF FFFF Address Memory Space Internal Peripherals Internal Memories EBI Chip Select 0 EBI Chip Select 1/ SDRAMC EBI Chip Select 2 EBI Chip Select 3/ NAND Flash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI Chip Select 6 EBI Chip Select 7 Undefined (Abort) 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes 1,518M Bytes 0x2000 0000 0x1FFF FFFF 0x3000 0000 0x2FFF FFFF 0x4000 0000 0x3FFF FFFF 0x6FFF FFFF 0x6000 0000 0x5FFF FFFF 0x5000 0000 0x4FFF FFFF 0x7000 0000 0x7FFF FFFF 0x8000 0000 0x8FFF FFFF 0x9000 0000 256M Bytes 0xFFFF FD00 0xFFFF FC00 0xFFFF FA00 0xFFFF F800 0xFFFF F600 0xFFFF F400 0xFFFF F200

16 Bytes

256 Bytes

512 Bytes

512 BytesAIC

512 BytesMATRIX

512 BytesSMC

512 BytesSDRAMC

16 BytesRTT

16 BytesPIT

16 BytesWDT

Boot Memory (1) 0x0000 0000 (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP Notes : LCD User Interface 0x60 0000 SSC1 SSC2 0xFFFC D000 0xFFFF C000 SYSC Reserved0xFFFF FFFF System Controller Mapping 16K Bytes 0xFFFF FFFF Reserved 0xFFFF C000 0x70 0000 1M Bytes 1M Bytes 1M Bytes Reserved 0xF000 0000 Reserved Reserved 0x40 0000 1M Bytes

6242E–ATARM–11-Sep09 AT91SAM9261S A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decod- ing provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. The Bus Matrix manages five Masters and five Slaves. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. Regarding Master 0 and Master 1 (ARM926 ™ Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-3 for details. Each Slave has its own arbiter, thus allowing a different arbitration per Slave.

8.1 Embedded Memories

 32 KB ROM – Single Cycle Access at full bus speed  16 KB Fast SRAM – Single Cycle Access at full bus speed Table 8-1. List of Bus Matrix Masters Master 0 ARM926 Instruction Master 1 ARM926 Data Master 2 PDC Master 3 LCD Controller Master 4 USB Host Table 8-2. List of Bus Matrix Slaves Slave 0 Internal SRAM Slave 1 Internal ROM Slave 2 LCD Controller and USB Host Port Interfaces Slave 3 External Bus Interface Slave 4 Internal Peripherals

6242E–ATARM–11-Sep09 AT91SAM9261S

8.1.1 Internal Memory Mapping

Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Note: 1. EBI NCS0 is to be connected to a 16-bit non-volatile memo ry. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.

8.1.1.1 Internal SRAM

The AT91SAM9261S embeds a high-speed 16-Kbyte SRAM.

8.1.1.2 Internal ROM

The AT91SAM9261S integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.

8.1.1.3 USB Host Port

The AT91SAM9261S integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000.

8.1.1.4 LCD Controller

The AT91SAM9261S integrates an LCD Controller. T he interface is directly accessible on the AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.

8.1.2 Boot Strategies

The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these paramete rs can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 15. The AT91SAM9261S Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. Table 8-3. Internal Memory Mapping Address Master 0: ARM926 Inst ruction Master 1: ARM926 Data REMAP(RCB0) = 0 REMAP (RCB0) = 1 REMAP (RCB1) = 0 REMAP (RCB1) = 1 BMS = 1 BMS = 0 BMS = 1 BMS = 0 0x0000 0000 Int. ROM EBI NCS0 (1) Int. RAM C Int. ROM EBI NCS0 (1) Int. RAM C

6242E–ATARM–11-Sep09 AT91SAM9261S

8.1.2.1 BMS = 1, Boot on Embedded ROM

The system boots using the Boot Program.  Enable the 32,768 Hz oscillator  Auto baudrate detection  Downloads and runs an application from external storage media into internal SRAM  Automatic detection of valid application  Bootloader on a non volatile memory – SPI Serial Flash or DataFlash connected to NPCS0 of the SPI0 –N A N D F l a s h – SDCARD (boot ROM does not support high capacity SDCards)  SAM-BA Boot in case no valid program is detected in external NVM, supporting: – Serial communication on a DBGU – USB Device HS Port

8.1.2.2 BMS = 0, Boot on External Memory

 Boot on slow clock (32,768 Hz)  Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock 4. Switch the main clock to the new value.

8.2 External Memories

The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3). Refer to the memory map in Figure 8-1 on page 15.

6242E–ATARM–11-Sep09 AT91SAM9261S

9.1 Block Diagram

Figure 9-1. System Controller Block Diagram NRST SLCK Advanced Interrupt Controller Real-Time Timer Periodic Interval Timer Reset Controller PA0-PA31 periph_nreset System Controller Watchdog Timer wdt_fault WDRPROC PIO Controllers Power Management Controller XIN XOUT PLLRCA MAINCK PLLACK pit_irq MCK proc_nreset wdt_irq periph_irq{2..4]periph_nreset periph_clk[2..21] PCK MCK pmc_irq UDPCK nirq nfiq rtt_irq Embedded Peripherals periph_clk[2..4] pck[0-3] in out enable ARM926EJ-S SLCK SLCK irq0-irq2 fiq irq0-irq2 fiq periph_irq[6..21] periph_irq[2..21] int int periph_nreset periph_clk[6..21] jtag_nreset ice_nreset proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq SLCK Boundary Scan TAP Controller jtag_nreset debug PCK debug idle debug Bus Matrix MCK periph_nreset proc_nreset backup_nreset periph_nreset idle Debug Unit dbgu_irqMCK dbgu_rxd periph_nreset force_ntrst dbgu_txd USB Device Port UDPCK periph_nreset periph_clk[10] periph_irq[10] usb_suspend usb_suspendrtt_alarm Shutdown Controller SLCK rtt_alarm backup_nreset SHDN WKUP

4 General-purpose

backup_nreset XIN32 XOUT32 LCDCK PLLRCB PLLBCK UHPCK PB0-PB31 PC0-PC31 USB Host Port UHPCK periph_nreset periph_clk[20] periph_irq[20] LCD Controller LCDCK periph_nreset periph_clk[21] periph_irq[21] VDDBU Powered VDDCORE Powered force_ntrst ntrst VDDCORE POR MAIN OSC PLLA VDDBU POR SLOW CLOCK OSC PLLB ice_nreset

6242E–ATARM–11-Sep09 AT91SAM9261S

9.2 Reset Controller

 Based on two Power-on-Reset cells  Status of the last reset – Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset  Controls the internal resets and the NRST pin output

9.3 Shutdown Controller

 Shutdown and Wake-up logic: – Software programmable assertion of the SHDN pin – Deassertion Programmable on a WKUP pin level change or on alarm

9.4 General-purpose Backup Registers

 Four 32-bit general-purpose backup registers

9.5 Clock Generator

 Embeds the Low-power 32768 Hz Slow Clock Oscillator – Provides the permanent Slow Clock to the system  Embeds the Main Oscillator – Oscillator bypass feature – Supports 3 to 20 MHz crystals  Embeds Two PLLs – Outputs 80 to 240 MHz clocks – Integrates an input divider to increase output accuracy – 1 MHz minimum input frequency  Provides SLCK, MAINCK, PLLACK and PLLBCK. Figure 9-2. Clock Generator Block Diagram Power Management Controller XIN XOUT PLLRCA Slow Clock SLCK Main Clock MAINCK PLLA Clock PLLACK ControlStatus PLL and Divider BPLLRCB PLLB Clock PLLBCK XIN32 XOUT32 Slow Clock Oscillator Main Oscillator PLL and Divider A Clock Generator

6242E–ATARM–11-Sep09 AT91SAM9261S

9.6 Power Management Controller

 The Power Management Controller provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clock USBCK (HCK0) – the LCD Controller Clock LCDCK (HCK1) – up to thirty peripheral clocks – four programmable clock outputs: PCK0 to PCK3 Figure 9-3. Power Management Controller Block Diagram

9.7 Periodic Interval Timer

 Includes a 20-bit Periodic Counter with less than 1 µs accuracy  Includes a 12-bit Interval Overlay Counter  Real time OS or Linux ®/WindowsCE® compliant tick generator

9.8 Watchdog Timer

 12-bit key-protected only-once programmable counter  Windowed, prevents the processor to be in a dead-lock on the watchdog access

9.9 Real-time Timer

 32-bit Free-running backup counter  Alarm Register capable to generate a wake-up of the system MCK periph_clk[2..21] int UDPCK usb_suspend SLCK MAINCK PLLACK Prescaler /1,/2,/4,...,/64 PCK Processor Clock Controller Idle ModeMaster Clock Controller APB Peripherals Clock Controller ON/OFF USB Clock Controller ON/OFF SLCK MAINCK PLLACK Prescaler /1,/2,/4,...,/64 Programmable Clock Controller PLLBCK Divider /1,/2,/4 pck[0..3] PLLBCK PLLBCK UHPCK Divider /1,/2,/3,/4 HCKx AHB Peripherals Clock Controller ON/OFF

6242E–ATARM–11-Sep09 AT91SAM9261S

9.10 Advanced Interrupt Controller

 Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor  Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external interrupts – Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive  Four External Sources  8-level Priority Controller – Drives the normal interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt  Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector P r o t e c t M o d e – Easy debugging by preventing automatic operations when protect mode is enabled F a s t F o r c i n g – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor  General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt

9.11 Debug Unit

 Composed of four functions –T w o - p i n U A R T – Debug Communication Channel (DCC) support – Chip ID Registers – ICE Access Prevention T w o - p i n U A R T – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter  Debug Communication Channel Support

6242E–ATARM–11-Sep09 AT91SAM9261S – Offers visibility of COMMRX and COMMT X signals from the ARM Processor  Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals  ICE Access prevention – Enables software to prevent system access through the ARM Processor’s ICE – Prevention is made by asserting the NTRST line of the ARM Processor’s ICE

9.12 PIO Controllers

 Three PIO Controllers, each controlling up to 32 programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O Lines – PIOC has 32 I/O Lines  Fully programmable through Set/Clear Registers  Multiplexing of two peripheral functions per I/O Line  For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visib ility of the level on the pin at any time  Synchronous output, provides Set and Clear of several I/O lines in a single write

6242E–ATARM–11-Sep09 AT91SAM9261S 10. Peripherals

10.1 User Interface

The User Peripherals are mapped in the upper 25 6 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each Us er Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 15.

10.2 Peripheral Identifiers

Table 10-1 defines the Peripheral Identifiers of the AT91SAM9261S. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note: Setting AIC, SYSIRQ, UHP , LCDC and IRQ0 to IRQ2 bits in the clock set/clear registers of the PMC has no effect. Table 10-1. Peripheral Identifiers Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt

0 AIC Advanced Interrupt Controller FIQ

1 SYSIRQ System Interrupt

2 PIOA Parallel I/O Controller A

3 PIOB Parallel I/O Controller B

4 PIOC Parallel I/O Controller C

9 MCI Multimedia Card Interface

10 UDP USB Device Port

11 TWI Two-Wire Interface

12 SPI0 Serial Peripheral Interface 0

13 SPI1 Serial Peripheral Interface 1

14 SSC0 Synchronous Serial Controller 0

15 SSC1 Synchronous Serial Controller 1

16 SSC2 Synchronous Serial Controller 2

17 TC0 Timer/Counter 0

18 TC1 Timer/Counter 1

19 TC2 Timer/Counter 2

20 UHP USB Host Port

21 LCDC LCD Controller

29 AIC Advanced Interrupt Controller IRQ0

30 AIC Advanced Interrupt Controller IRQ1

31 AIC Advanced Interrupt Controller IRQ2

6242E–ATARM–11-Sep09 AT91SAM9261S

10.3 Peripheral Multiplexing on PIO Lines

The AT91SAM9261S features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A or B. Table 10-2 on page 28 , Table 10-3 on page 29 and Table 10-4 on page 30 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control- lers. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. Note that some output only peripheral functions might be duplicated within the tables. The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset Stat e” column, the PIO line is assigned to this func- tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.

10.3.1 Resource Multiplexing

10.3.1.1 LCD Controller

The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel without any limitation. Interfacing 24 bit-per-p ixel TFTs panel prevents using the SSC0 and the chip select line 0 of the SPI1. 16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LC DD19 to LCDD23. Intensity bit is output on LCDD2, LCDD10 and LCDD18. Usin g the peripheral B does not prevent using the SSC0 and the SPI1 lines.

10.3.1.2 EBI

If not required, the NWAIT function (external wait request) can be deactivated by software, allowing this pin to be used as a PIO. 10.3.1.3 32-bit Data Bus Using a 32-bit Data Bus prevents:  using the three Timer Counter channels’ outputs and trigger inputs  using the SSC2

10.3.1.4 NAND Flash Interface

Using the NAND Flash interface prevents:  using NCS3, NCS6 and NCS7 to access other parallel devices

10.3.1.5 Compact Flash Interface

Using the CompactFlash interface prevents:  using NCS4 and/or NCS5 to access other parallel devices

6242E–ATARM–11-Sep09 AT91SAM9261S

10.3.1.6 SPI0 and the MultiMedia Card Interface

As the DataFlash Card is compat ible with the SDCard, it is us eful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI.

10.3.1.7 USARTs

 Using USART0 with its control signals prevents using some clock outputs and interrupt lines.

10.3.1.8 Clock Outputs

 Using the clock outputs multiplexed with the PIO A prevents using the Debug Unit and/or the Two Wire Interface.  Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0.

10.3.1.9 Interrupt Lines

 Using FIQ prevents using the USART0 control signals.  Using IRQ0 prevents using the NWAIT EBI signal.  Using the IRQ1 and/or IRQ2 prevents using the SPI1.

6242E–ATARM–11-Sep09 AT91SAM9261S

10.3.2 PIO Controller A Multiplexing

Table 10-2. Multiplexing on PIO Controller A PIO Controller A Application Usage I/O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments PA0 SPI0_MISO MCDA0 I/O VDDIOP PA1 SPI0_MOSI MCCDA I/O VDDIOP PA2 SPI0_SPCK MCCK I/O VDDIOP PA3 SPI0_NPCS0 I/O VDDIOP PA4 SPI0_NPCS1 MCDA1 I/O VDDIOP PA5 SPI0_NPCS2 MCDA2 I/O VDDIOP PA6 SPI0_NPCS3 MCDA3 I/O VDDIOP PA7 TWD PCK0 I/O VDDIOP PA8 TWCK PCK1 I/O VDDIOP PA9 DRXD PCK2 I/O VDDIOP PA10 DTXD PCK3 I/O VDDIOP PA11 TSYNC SCK1 I/O VDDIOP PA12 TCLK RTS1 I/O VDDIOP PA13 TPS0 CTS1 I/O VDDIOP PA14 TPS1 SCK2 I/O VDDIOP PA15 TPS2 RTS2 I/O VDDIOP PA16 TPK0 CTS2 I/O VDDIOP PA17 TPK1 TF1 I/O VDDIOP PA18 TPK2 TK1 I/O VDDIOP PA19 TPK3 TD1 I/O VDDIOP PA20 TPK4 RD1 I/O VDDIOP PA21 TPK5 RK1 I/O VDDIOP PA22 TPK6 RF1 I/O VDDIOP PA23 TPK7 RTS0 I/O VDDIOP PA24 TPK8 SPI1_NPCS1 I/O VDDIOP PA25 TPK9 SPI1_NPCS2 I/O VDDIOP PA26 TPK10 SPI1_NPCS3 I/O VDDIOP PA27 TPK11 SPI0_NPCS1 I/O VDDIOP PA28 TPK12 SPI0_NPCS2 I/O VDDIOP PA29 TPK13 SPI0_NPCS3 I/O VDDIOP PA30 TPK14 A23 A23 VDDIOP PA31 TPK15 A24 A24 VDDIOP

6242E–ATARM–11-Sep09 AT91SAM9261S

10.3.3 PIO Controller B Multiplexing

Note: 1. PB3 is multiplexed with BMS signal. Care should be taken during reset time. Table 10-3. Multiplexing on PIO Controller B PIO Controller B Application Usage I/O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments PB0 LCDVSYNC I/O VDDIOP PB1 LCDHSYNC I/O VDDIOP PB2 LCDDOTCK PCK0 I/O VDDIOP PB3 (1) LCDDEN See footnote (1) I/O VDDIOP PB4 LCDCC LCDD2 I/O VDDIOP PB5 LCDD0 LCDD3 I/O VDDIOP PB6 LCDD1 LCDD4 I/O VDDIOP PB7 LCDD2 LCDD5 I/O VDDIOP PB8 LCDD3 LCDD6 I/O VDDIOP PB9 LCDD4 LCDD7 I/O VDDIOP PB10 LCDD5 LCDD10 I/O VDDIOP PB11 LCDD6 LCDD11 I/O VDDIOP PB12 LCDD7 LCDD12 I/O VDDIOP PB13 LCDD8 LCDD13 I/O VDDIOP PB14 LCDD9 LCDD14 I/O VDDIOP PB15 LCDD10 LCDD15 I/O VDDIOP PB16 LCDD11 LCDD19 I/O VDDIOP PB17 LCDD12 LCDD20 I/O VDDIOP PB18 LCDD13 LCDD21 I/O VDDIOP PB19 LCDD14 LCDD22 I/O VDDIOP PB20 LCDD15 LCDD23 I/O VDDIOP PB21 TF0 LCDD16 I/O VDDIOP PB22 TK0 LCDD17 I/O VDDIOP PB23 TD0 LCDD18 I/O VDDIOP PB24 RD0 LCDD19 I/O VDDIOP PB25 RK0 LCDD20 I/O VDDIOP PB26 RF0 LCDD21 I/O VDDIOP PB27 SPI1_NPCS1 LCDD22 I/O VDDIOP PB28 SPI1_NPCS0 LCDD23 I/O VDDIOP PB29 SPI1_SPCK IRQ2 I/O VDDIOP PB30 SPI1_MISO IRQ1 I/O VDDIOP PB31 SPI1_MOSI PCK2 I/O VDDIOP

6242E–ATARM–11-Sep09 AT91SAM9261S

10.3.4 PIO Controller C Multiplexing

Table 10-4. Multiplexing on PIO Controller C PIO Controller C Application Usage I/O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments PC0 NANDOE NCS6 I/O VDDIOP PC1 NANDWE NCS7 I/O VDDIOP PC2 NWAIT IRQ0 I/O VDDIOP PC3 A25/CFRNW A25 VDDIOP PC4 NCS4/CFCS0 I/O VDDIOP PC5 NCS5/CFCS1 I/O VDDIOP PC6 CFCE1 I/O VDDIOP PC7 CFCE2 I/O VDDIOP PC8 TXD0 PCK2 I/O VDDIOP PC9 RXD0 PCK3 I/O VDDIOP PC10 RTS0 SCK0 I/O VDDIOP PC11 CTS0 FIQ I/O VDDIOP PC12 TXD1 NCS6 I/O VDDIOP PC13 RXD1 NCS7 I/O VDDIOP PC14 TXD2 SPI1_NPCS2 I/O VDDIOP PC15 RXD2 SPI1_NPCS3 I/O VDDIOP PC16 D16 TCLK0 I/O VDDIOM PC17 D17 TCLK1 I/O VDDIOM PC18 D18 TCLK2 I/O VDDIOM PC19 D19 TIOA0 I/O VDDIOM PC20 D20 TIOB0 I/O VDDIOM PC21 D21 TIOA1 I/O VDDIOM PC22 D22 TIOB1 I/O VDDIOM PC23 D23 TIOA2 I/O VDDIOM PC24 D24 TIOB2 I/O VDDIOM PC25 D25 TF2 I/O VDDIOM PC26 D26 TK2 I/O VDDIOM PC27 D27 TD2 I/O VDDIOM PC28 D28 RD2 I/O VDDIOM PC29 D29 RK2 I/O VDDIOM PC30 D30 RF2 I/O VDDIOM PC31 D31 PCK1 I/O VDDIOM

6242E–ATARM–11-Sep09 AT91SAM9261S

10.3.5 System Interrupt

The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:  the SDRAM Controller  the Debug Unit  the Periodic Interval Timer  the Real-Time Timer  the Watchdog Timer  the Reset Controller  the Power Management Controller The clock of these peripherals cannot be deacti vated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller.

10.3.6 External Interrupts

All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.

10.4 External Bus Interface

 Integrates two External Memory Controllers: – Static Memory Controller – SDRAM Controller  Additional logic for NAND Flash and CompactFlash support – NAND Flash support: 8-bit as well as 16-bit devices are supported – CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled.  Optimized External Bus – 16- or 32-bit Data Bus – Up to 26-bit Address Bus, up to 64 Mbytes addressable – Eight Chip Selects, each reserved to one of the eight Memory Areas – Optimized pin multiplexing to re duce latencies on External Memories  Configurable Chip Select Assignment Managed by EBI_CSA Register located in the MATRIX user interface – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash Support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support – Static Memory Controller on NCS6 - NCS7

6242E–ATARM–11-Sep09 AT91SAM9261S

10.5 Static Memory Controller

 External memory mapping, 256 Mbyte address space per Chip Select Line  Up to Eight Chip Select Lines  8-, 16- or 32-bit Data Bus  Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size)  Multiple device adaptability – Compliant with LCD Module – Control signal programmable setup, pulse and hold time for each Memory Bank  Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time  Slow Clock Mode Supported

10.6 SDRAM Controller

 Supported Devices – Standard and Low Power SDRAM (Mobile SDRAM)  Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path  Programming Facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable  Energy-saving Capabilities – Self-refresh, power down and deep power down modes supported  Error detection – Refresh Error Interrupt  SDRAM Power-up Initialization by software  CAS Latency of 1, 2 and 3 supported  Auto Precharge Command not used

6242E–ATARM–11-Sep09 AT91SAM9261S

10.7 Serial Peripheral Interface

 Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to fifteen peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors  Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection  Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device

10.8 Two-wire Interface

 Compatibility with standard two-wire serial memory  One, two or three bytes for slave address  Sequential read/write operations

10.9 USART

 Programmable Baud Rate Generator  5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By-8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding  RS485 with driver control signal  ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit  IrDA modulation and demodulation

6242E–ATARM–11-Sep09 AT91SAM9261S – Communication at up to 115.2 Kbps  Test Modes – Remote Loopback, Local Loopback, Automatic Echo

10.10 Synchronous Serial Controller

 Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and more).  Contains an independent receiver and transmitter and a common clock divider.  Offers a configurable frame sync and data length.  Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal.  Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal.

10.11 Timer Counter

 Three 16-bit Timer Counter Channels  Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation –D e l a y T i m i n g – Pulse Width Modulation – Up/down Capabilities  Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals  Two global registers that act on all three TC Channels

10.12 Multimedia Card Interface

 Compatibility with MultiMedia Ca rd Specification Version 2.2  Compatibility with SD Memory Ca rd Specification Version 1.0  Cards clock rate up to Master Clock divided by 2  Embedded power management to slow down clock rate when not used  Each MCI has two slots, each supporting – One slot for one MultiMedia Card bus (up to 30 cards) or – One SD Memory Card  Support for stream, block and multi-block data read and write

6242E–ATARM–11-Sep09 AT91SAM9261S

10.13 USB

 USB Host Port: – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-sp eed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with two downstream USB ports – Two embedded USB transceivers – No overcurrent detection – Supports power management – Operates as a master on the Bus Matrix  USB Device Port: – USB V2.0 full-speed compliant, 12 Mbits per second – Embedded USB V2.0 full-speed transceiver – Embedded dual-port RAM for endpoints – Suspend/Resume logic – Ping-pong mode (two memory banks) for isochronous and bulk endpoints – Six general-purpose endpoints: Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode Endpoint 3: 64 bytes, no ping-pong mode Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode  Embedded pad pull-up configurable via USB_PUCR Register located in the MATRIX user interface

10.14 LCD Controller

 Single and Dual scan color and monochrome passive STN LCD panels supported  Single scan active TFT LCD panels supported.  4-bit single scan, 8-bit single or dual scan , 16-bit dual scan STN interfaces supported  Up to 24-bit single scan TFT interfaces supported  Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays  1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN  1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN  1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT  Single clock domain architecture  Resolution supported up to 2048 x 2048

6242E–ATARM–11-Sep09 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S 11. ARM926EJ-S Processor Description

11.1 Overview

The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microproces- sors. The ARM926EJ-S implements ARM architectu re version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32- bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features fo r efficient execution of Java bytecode, provid- ing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java- powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including:  an ARM9EJ-S ™ integer core  a Memory Management Unit (MMU)  separate instruction and data AMBA ™ AHB bus interfaces

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11.2 ARM9EJ-S Processor

11.2.1 ARM9EJ-S Operating States

The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:  ARM state: 32-bit, word-aligned ARM instructions.  THUMB state: 16-bit, halfword-aligned Thumb instructions.  Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words.

11.2.2 Switching State

The operating state of the ARM9EJ-S core can be switched between:  ARM state and THUMB state using the BX and BLX instructions, and loads to the PC  ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler.

11.2.3 Instruction Pipelines

The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is us ed for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages.

11.2.4 Memory Access

The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S con- trol logic automatically detects these cases and stalls the core or forward data.

11.2.5 Jazelle Technology

The Jazelle technology enables direct and efficient execution of Java byte codes on ARM pro- cessors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode appears as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into AR M instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system . All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode.

6242E–ATARM–11-Sep09 AT91SAM9261S Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hard- ware or in software.

11.2.6 ARM9EJ-S Operating Modes

In all states, there are seven operation modes:  User mode is the usual ARM program execution state. It is used for executing most application programs  Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process  Interrupt (IRQ) mode is used for general-purpose interrupt handling  Supervisor mode is a protected mode for the operating system  Abort mode is entered after a data or instruction prefetch abort  System mode is a privileged user mode for the operating system  Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources.

11.2.7 ARM9EJ-S Registers

The ARM9EJ-S core has a total of 37 registers.  31 general-purpose 32-bit registers  6 32-bit status registers Table 11-1 shows all the registers in all modes. Table 11-1. ARM9TDMI ™ Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ

6242E–ATARM–11-Sep09 AT91SAM9261S The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address va lues. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a pro- gram counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another reg- ister called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines:  constraints on the use of registers  stack conventions  argument passing and result return The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:  Eight general-purpose registers r0-r7  Stack pointer, SP  Link register, LR (ARM r14) P C R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ Mode-specific banked registers Table 11-1. ARM9TDMI™ Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode

6242E–ATARM–11-Sep09 AT91SAM9261S  CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12).

11.2.7.1 Status Registers

The ARM9EJ-S core contains one CPSR, and fi ve SPSRs for exception handlers to use. The program status registers:  hold information about the most recently performed ALU operation  control the enabling and disabling of interrupts  set the processor operation mode Figure 11-1. Status Register Format Figure 11-1 shows the status register format, where:  N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags  The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.  The J bit in the CPSR indicates when the AR M9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state.  Mode: five bits to encode the current processor mode

11.2.7.2 Exceptions

Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are:  Fast interrupt (FIQ)  Normal interrupt (IRQ)  Data and Prefetched aborts (Abort)  Undefined instruction (Undefined)  Software interrupt and Reset (Supervisor) NZ CVQ JI F T ModeReserved Mode bits Thumb state bit FIQ disable IRQ disable Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than 31 30 29 28 27 24 7 6 5 0

6242E–ATARM–11-Sep09 AT91SAM9261S When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep- tions according to the following priority order:  Reset (highest priority)  Data Abort F I Q I R Q P r e f e t c h A b o r t  BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and pro- ceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that cor- responds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. T he offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until th e instruction reaches the Execute stage in the

6242E–ATARM–11-Sep09 AT91SAM9261S pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feat ure of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pi peline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place.

11.2.8 ARM Instruction Set Overview

The ARM instruction set is divided into:  Branch instructions  Data processing instructions  Status register transfer instructions  Load and Store instructions  Coprocessor instructions  Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 11-2 gives the ARM instruction mnemonic list. Table 11-2. ARM Instruction Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry RSB Reverse Subtract RSC Rever se Subtract with Carry CMP Compare CMN Compare Negated TST Test TEQ Test Equivalence AND Logical AND BIC Bit Clear EOR Logical Exclusive OR OR R Logical (inclusive) OR MUL Multiply MLA Multiply Accumulate SMULL Sign Long Multiply UMULL Unsigned Long Multiply SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply Accumulate MSR Move to Status Register MRS Move From Status Register B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRSH Load Signed Halfword LDRSB Load Signed Byte LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte

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11.2.9 New ARM Instruction Set

Notes: 1. A Thumb BLX contains two consecutiv e Thumb instructions, and takes four cycles.

11.2.10 Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into:  Branch instructions  Data processing instructions  Load and Store instructions  Load and Store multiple instructions  Exception-generating instruction LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation LDRT Load Register with Translation STRT Store Register with Translation LDM Load Multiple STM Store Multiple SWP Swap Word SWPB Swap Byte MCR Move To Coprocessor MRC Move From Coprocessor LDC Load To Coprocessor STC Store From Coprocessor CDP Coprocessor Data Processing Table 11-2. ARM Instruction Mnemonic List (Continued) Mnemonic Operation Mnemonic Operation Table 11-3. New ARM Instruction Mnemonic List Mnemonic Operation Mnemonic Operation BXJ Branch and exchange to Java MRRC Mo ve double from coprocessor BLX (1) Branch, Link and exchange MCR2 Alternative move of ARM reg to coprocessor SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint SMULxy Signed Multiply 16 * 16 bit PLD Soft Preload, Memory prepare to load from address SMULWy Signed Multiply 32 * 16 bit STRD Store Double QADD Saturated Add STC2 Alternative Store from Coprocessor QDADD Saturated Add with Double LDRD Load Double QSUB Saturated subtract LDC2 Alternative Load to Coprocessor QDSUB Saturated Subtract with double CLZ Count Leading Zeroes

6242E–ATARM–11-Sep09 AT91SAM9261S Table 11-4 gives the Thumb instruction mnemonic list. Table 11-4. Thumb Instruction Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR OR R Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply BLX Branch, Link, and Exchange B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack BCC Conditional Branch BKPT Breakpoint

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11.3 CP15 Coprocessor

Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:  ARM9EJ-S  Caches (ICache, DCache and write buffer) M M U  Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Notes: 1. Register locations 0, 5 and 13 each provid e access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. Table 11-5. CP15 Registers Register Name Read/Write 0I D C o d e (1) Read/Unpredictable

0 Cache type (1) Read/Unpredictable

1 Control Read/write

2 Translation Table Base Read/write

3 Domain Access Control Read/write

4 Reserved None

5 Data fault Status

(1) Read/write

5 Instruction fault status (1) Read/write

6 Fault Address Read/write

7 Cache Operations Read/Write

8 TLB operations Unpredictable/Write

9 Cache lockdown

(2) Read/write

10 TLB lockdown Read/write

11 Reserved None

12 Reserved None

13 FCSE PID

(1) Read/write

13 Context ID (1) Read/Write

14 Reserved None

15 Test configuration Read/Write

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11.3.1 CP15 Registers Access

CP15 registers can only be accessed in privileged mode by:  MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.  MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below:  CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependen t on the CP15 register used. For details, refer to CP15 spe- cific register behavior.  opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0.  Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.  CRn[19:16]: Coprocessor Register Determines the destination coprocessor register.  L: Instruction Bit 0 = MCR instruction 1 = MRC instruction  opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15.  cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. 31 30 29 28 27 26 25 24 c o n d 1110 23 22 21 20 19 18 17 16 opcode_1 L CRn 15 14 13 12 11 10 9 8 R d 1111 76543210 opcode_2 1 CRm

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11.4 Memory Management Unit (MMU)

The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian OS ®, Windows CE, and Linux. These virtual memory features are memo ry access permission c ontrols and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extens ion) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB secti on of physical memory along with attribute infor- mation (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain tw o subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 11-6 shows the different attributes of each page in the physical memory. The MMU consists of:  Access control logic  Translation Look-aside Buffer (TLB)  Translation table walk hardware

11.4.1 Access Control Logic

The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). Table 11-6. Mapping Details Mapping Name Mapping Size Acc ess Permission By Subpage Size Section 1M byte Section - Large Page 64K bytes 4 separated subpages 16K bytes Small Page 4K bytes 4 separated subpages 1K byte Tiny Page 1K byte Tiny Page -

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11.4.2 Translation Look-aside Buffer (TLB)

The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic dete rmines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory.

11.4.3 Translation Table Walk Hardware

The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Page- mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B.

11.4.4 MMU Faults

The MMU generates an abort on the following types of faults:  Alignment faults (for data accesses only)  Translation faults  Domain faults  Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B.

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11.5 Caches and Write Buffer

The ARM926EJ-S contains a 16 KB Instruction Cache (ICache), a 16 KB Data Cache (DCache), and a write buffer. Al though the ICache and DCache s hare common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a ca che line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word caus es a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown).

11.5.1 Instruction Cache (ICache)

The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset.

11.5.2 Data Cache (DCache) and Write Buffer

ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory band- width and latency on data access performance. The operations of DCache and write buffer are closely connected.

11.5.2.1 DCache

The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA AHB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protecti on checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, whic h incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half- lines as dirty. If the

6242E–ATARM–11-Sep09 AT91SAM9261S cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entr y, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table.

11.5.2.2 Write Buffer

The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.

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11.6 Bus Interface Unit

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits:  It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture.  Each AHB layer becomes simple because it only has one master, so no arbitration or master- to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions.  The arbitration becomes effective when more than one master wants to access the same slave simultaneously.

11.6.1 Supported Transfers

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 word s in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 11-7 gives an overview of the supported transfers and different kinds of transactions they are used for.

11.6.2 Thumb Instruction Fetches

All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.

11.6.3 Address Alignment

The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. Table 11-7. Supported Transfers HBurst[2:0] Description SINGLE Single transfer Single transfer of word, half word, or byte:  data write (NCNB, NCB, WT, or WB that has missed in DCache)  data read (NCNB or NCB)  NC instruction fetch (prefetched and non-prefetched)  page table walk read INCR4 Four-word incrementing burst Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. INCR8 Eight-word incrementing burst Full-line cache writ e-back, eight-word burst NCNB, NCB, WT, or WB write. WRAP8 Eight-word wrapping burst Cache linefill

6242E–ATARM–11-Sep09 AT91SAM9261S 12. AT91SAM9261S Debug and Test

12.1 Overview

The AT91SAM9261S features a number of complementary debu g and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.

12.2 Block Diagram

Figure 12-1. Debug and Test Block Diagram ICE-RTARM9EJ-S PDC DBGU PIO DRXD DTXD TMS TCK TDI JTAGSEL TDO TST Reset and Test TAP: Test Access Port Boundary Port ICE/JTAG TAP ARM926EJ-S POR RTCK NTRST

6242E–ATARM–11-Sep09 AT91SAM9261S

12.3 Application Examples

12.3.1 Debug Environment

Figure 12-2 on page 54 shows a complete debug environment example. The ICE/JTAG inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debug- ger running on a personal computer provides th e user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example AT91SAM9261S-based Application Board ICE/JTAG Interface Host Debugger PC ICE/JTAG Connector TerminalRS232 ConnectorAT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S

12.3.2 Test Environment

Figure 12-3 on page 55 shows a test environment example. Test vectors are sent and inter- preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example

12.4 Debug and Test Pin Description

AT91SAM9261S-based Application Board In Test AT91SAM9261S Test Adaptor Chip 2Chip n Chip 1 Table 12-1. Debug and Test Pin List Pin Name Function Type Active Level Reset/Test NRST Microcontroller Reset Input/Output Low TST Test Mode Select Input High ICE and JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out Output TMS Test Mode Select Input NTRST Test Reset Signal Input Low RTCK Returned Test Clock Output JTAGSEL JTAG Selection Input Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

6242E–ATARM–11-Sep09 AT91SAM9261S

12.5 Functional Description

12.5.1 Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.

12.5.2 Embedded In-circuit Emulator

The ARM9EJ-S EmbeddedICE-RT ™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ -S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document ARM9EJ-S Technical Ref- erence Manual (DDI 0222A).

12.5.3 JTAG Signal Description

TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG regis- ters to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the te st interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to syn- chronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode.

6242E–ATARM–11-Sep09 AT91SAM9261S

12.5.4 Debug Unit

The Debug Unit provides a two-pin (DXRD a nd TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two Peripheral DMA Controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9261S Debug Unit Chip ID value is 0x0197 03A0 on 32-bit width. 12.5.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In IC E debug mode, the AR M processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.

12.5.5.1 JTAG Boundary-scan Register

The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associ- ated control signals. Each AT91SAM9261S input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2. AT91SAM9261S JTAG Boundary Scan Register Bit Number Pin Name Pin Ty pe Associated BSR Cells

483 A18 OUT OUTPUT

482 A[22:16] CONTROL

481 A19 OUT OUTPUT

480 A20 OUT OUTPUT

479 A21 OUT OUTPUT

478 A22 OUT OUTPUT

477 NCS0 OUT OUTPUT

476 A[7:0] CONTROL

475 NCS1 OUT OUTPUT

474 NCS0/NCS1/NCS2/NCS3

NRD/NWR0/NWR1/NWR3 CONTROL

6242E–ATARM–11-Sep09 AT91SAM9261S

473 NCS2 OUT OUTPUT

472 NCS3 OUT OUTPUT

471 NRD OUT OUTPUT

469 OUTPUT

467 OUTPUT

465 NWR3 OUT OUTPUT

464 SDRAMCKE OUT OUTPUT

463 SDRAMCKE/RAS/CAS

461 OUTPUT

460 CONTROL

459 RAS OUT OUTPUT

458 CAS OUT OUTPUT

457 SDWE OUT OUTPUT

455 OUTPUT

454 CONTROL

451 OUTPUT

450 CONTROL

448 OUTPUT

447 CONTROL

445 OUTPUT

444 CONTROL

442 OUTPUT

441 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 439 D5 IN/OUT INPUT

438 OUTPUT

437 CONTROL

435 OUTPUT

434 CONTROL

432 OUTPUT

431 CONTROL

429 OUTPUT

428 CONTROL

425 OUTPUT

424 CONTROL

422 OUTPUT

421 CONTROL

419 OUTPUT

418 CONTROL

416 OUTPUT

415 CONTROL

412 OUTPUT

411 CONTROL

409 OUTPUT

408 CONTROL

406 OUTPUT

405 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 404 PC16 IN/OUT INPUT

403 OUTPUT

402 CONTROL

399 OUTPUT

398 CONTROL

395 OUTPUT

394 CONTROL

391 OUTPUT

390 CONTROL

387 OUTPUT

386 CONTROL

383 OUTPUT

382 CONTROL

379 OUTPUT

378 CONTROL

375 OUTPUT

374 CONTROL

371 OUTPUT

370 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 368 PC23 IN/OUT INPUT

367 OUTPUT

366 CONTROL

363 OUTPUT

362 CONTROL

359 OUTPUT

358 CONTROL

355 OUTPUT

354 CONTROL

351 OUTPUT

350 CONTROL

347 OUTPUT

346 CONTROL

343 OUTPUT

342 CONTROL

339 OUTPUT

338 CONTROL

335 OUTPUT

334 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 332 PC2 IN/OUT INPUT

331 OUTPUT

330 CONTROL

327 OUTPUT

326 CONTROL

323 OUTPUT

322 CONTROL

319 OUTPUT

318 CONTROL

315 OUTPUT

314 CONTROL

311 OUTPUT

310 CONTROL

307 OUTPUT

306 CONTROL

303 OUTPUT

302 CONTROL

299 OUTPUT

298 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 296 PC11 IN/OUT INPUT

295 OUTPUT

294 CONTROL

291 OUTPUT

290 CONTROL

287 OUTPUT

286 CONTROL

283 OUTPUT

282 CONTROL

279 OUTPUT

278 CONTROL

275 OUTPUT

274 CONTROL

271 OUTPUT

270 CONTROL

267 OUTPUT

266 CONTROL

263 OUTPUT

262 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 260 PA4 IN/OUT INPUT

259 OUTPUT

258 CONTROL

255 OUTPUT

254 CONTROL

251 OUTPUT

250 CONTROL

247 OUTPUT

246 CONTROL

243 OUTPUT

242 CONTROL

239 OUTPUT

238 CONTROL

235 OUTPUT

234 CONTROL

231 OUTPUT

230 CONTROL

227 OUTPUT

226 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 224 PA13 IN/OUT INPUT

223 OUTPUT

222 CONTROL

219 OUTPUT

218 CONTROL

215 OUTPUT

214 CONTROL

211 OUTPUT

210 CONTROL

207 OUTPUT

206 CONTROL

203 OUTPUT

202 CONTROL

199 OUTPUT

198 CONTROL

195 OUTPUT

194 CONTROL

191 OUTPUT

190 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 188 PA22 IN/OUT INPUT

187 OUTPUT

186 CONTROL

183 OUTPUT

182 CONTROL

179 OUTPUT

178 CONTROL

175 OUTPUT

174 CONTROL

171 OUTPUT

170 CONTROL

167 OUTPUT

166 CONTROL

163 OUTPUT

162 CONTROL

159 OUTPUT

158 CONTROL

155 OUTPUT

154 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 152 PA31 IN/OUT INPUT

151 OUTPUT

150 CONTROL

147 OUTPUT

146 CONTROL

143 OUTPUT

142 CONTROL

139 OUTPUT

138 CONTROL

135 OUTPUT

134 CONTROL

131 OUTPUT

130 CONTROL

127 OUTPUT

126 CONTROL

123 OUTPUT

122 CONTROL

119 OUTPUT

118 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S 116 PB8 IN/OUT INPUT

115 OUTPUT

114 CONTROL

111 OUTPUT

110 CONTROL

107 OUTPUT

106 CONTROL

103 OUTPUT

102 CONTROL

99 OUTPUT

98 CONTROL

95 OUTPUT

94 CONTROL

91 OUTPUT

90 CONTROL

87 OUTPUT

86 CONTROL

83 OUTPUT

82 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S PB17 IN/OUT INPUT

79 OUTPUT

78 CONTROL

75 OUTPUT

74 CONTROL

71 OUTPUT

70 CONTROL

67 OUTPUT

66 CONTROL

63 OUTPUT

62 CONTROL

59 OUTPUT

58 CONTROL

55 OUTPUT

54 CONTROL

51 OUTPUT

50 CONTROL

47 OUTPUT

46 CONTROL

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S PB26 IN/OUT INPUT

43 OUTPUT

42 CONTROL

39 OUTPUT

38 CONTROL

35 OUTPUT

34 CONTROL

31 OUTPUT

30 CONTROL

27 OUTPUT

26 CONTROL

23 OUTPUT

22 CONTROL

20 A0 OUT OUTPUT

18 A1 OUT OUTPUT

17 A2 OUT OUTPUT

16 A3 OUT OUTPUT

15 A4 OUT OUTPUT

14 A5 OUT OUTPUT

13 A6 OUT OUTPUT

12 A7 OUT OUTPUT

11 A8 OUT OUTPUT

10 A[15:8] CONTROL

09 A9 OUT OUTPUT

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S

08 A10 OUT OUTPUT

07 SDA10 OUT OUTPUT

06 A11 OUT OUTPUT

05 A12 OUT OUTPUT

04 A13 OUT OUTPUT

03 A14 OUT OUTPUT

02 A15 OUT OUTPUT

01 A16 OUT OUTPUT

00 A17 OUT OUTPUT

Table 12-2. AT91SAM9261S JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Ty pe Associated BSR Cells

6242E–ATARM–11-Sep09 AT91SAM9261S

12.5.6 ID Code Register

Access: Read-only  VERSION[31:28]: Product Version Number Set to 0x0.  PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B08  MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_803F. 31 30 29 28 27 26 25 24 VERSION PART NUMBER 23 22 21 20 19 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER MANUFACTURER IDENTITY 76543210 MANUFACTURER IDENTITY 1

6242E–ATARM–11-Sep09 AT91SAM9261S 13. AT91SAM9261S Boot Program

13.1 Overview

The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial flash Boot program and Data- Flash ® Boot program are executed. It looks for a sequence of seven valid ARM exception vectors in a Serial Flash or DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM . This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, NAND Flash Boot program is then executed. The NAND Flash Boot program looks for a sequence of seven valid ARM exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the SD Card is not formatted or if boot.bin file is not found, TWI Boot program is then exe- cuted. The TWI Boot program searches for a va lid application in a EEPROM memory. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, SAM-BA Boot is then executed. It waits for transac- tions either on the USB device, or on the DBGU serial port.

6242E–ATARM–11-Sep09 AT91SAM9261S

13.2 Flow Diagram

The Boot Program implements the algorithm in Figure 13-1. Figure 13-1. Boot Program Algorithm Flow Diagram Timeout < 50ms Character(s) received on DBGU Run SAM-BA Boot Run SAM-BA Boot OR SAM-BA Boot USB Enumeration Successful No Timeout 50ms. EEPROMBoot Download from EEPROM Run Ye s TWI/EEPROM Boot No Device Setup SD Card Boot Download from SDCARD Run Ye s SD Card Boot Nand Flash Boot Download from Nand Flash Run Ye s Nand Flash Boot Timeout < 50msNo SPI DataFlash Boot Download from DataFlash NPCS0 Run Ye s DataFlash Boot Timeout < 25 msNo SPI Serial Flash Boot Download from Serial Flash NPCS0 Run Ye s Serial Flash Boot Timeout < 25 msNo

6242E–ATARM–11-Sep09 AT91SAM9261S

13.3 Device Initialization

Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. Main Oscillator Frequency Detection 3. C variable initialization 4. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. Table 13-1 defines the crystals supported by the Boot Program. 5. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) 6. Enable the user reset 7. Jump to SerialFlash Boot sequence through NPCS0. If SerialFlash Boot succeeds, per- form a remap and jump to 0x0. 8. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, per- form a remap and jump to 0x0. 9. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 10. Jump to SD Card Boot sequence. If SD Card Boot succeeds, perform a remap and jump to 0x0. 11. Jump to EEPROM Boot sequence. If EEPROM Boot succeeds, perform a remap and jump to 0x0. 12. Activation of the Instruction Cache 13. Jump to SAM-BA Boot sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port Table 13-1. Crystals Supported by Software Auto-Detection (MHz)

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 13-2. Remap Action after Download Completion

13.4 Valid Image Detection

The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corre- sponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see “Structure of ARM Vector 6” on page 76).

13.4.1 Valid ARM Exception Vectors

Figure 13-3. LDR Opcode Figure 13-4. B Opcode Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF –I = = 0 –P = = 1 – U offset added (U==1) or subtracted (U==0) –W = = 1

13.4.2 Structure of ARM Vector 6

The ARM exception vector 6 is used to store information needed by the DataFlash boot pro- gram. This information is described below. REMAP Internal ROM Internal SRAM Internal SRAM Internal ROM 0x0030_0000 0x0000_0000 0x0010_0000 0x0000_0000 31 28 27 24 23 20 19 16 15 12 11 0

111001 IP U0 W 1 R n R d

11101010 Offset (24 bits)

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 13-5. Structure of the ARM Vector 6

13.4.2.1 Example

An example of valid vectors follows: 00 ea000006 B 0x20 04 eafffffe B 0x04 08 ea00002f B _main 0c eafffffe B 0x0c 10 eafffffe B 0x10 14 00001234 B 0x14 <- Code size = 4660 bytes 18 eafffffe B 0x18 The size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct size of his application.

13.5 Serial Flash Boot

The Serial Flash boot looks for a valid application in the SPI SerialFlash memory. SPI0 is configured in master mode to generate a SPCK at 8MHz. Serial Flash shall be con- nected to NPCS0. The SerialFlash boot reads the se rial flash status register (I nstruction code 0x05). The serial flash is considered as ready if bit 0 of the returned status register is cleared. If no serial flash is connected or if it does not answer, SerialFlash boots exits after a 1000 attempts. If the serial flash is ready, Serial Flash boot reads the first 8 words into SRAM (Instruction code “Continuos read array” 0x0b) and checks if it corresponds to valid exception vectors according to the Valid Image detection algorithm. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. 31 0 Size of the code to download in bytes

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 13-6. Serial Flash Download

13.6 DataFlash Boot Sequence

The Dataflash boot looks for a valid application in the SPI DataFlash memory. SPI0 is configured in master mode to generate a SPCK at 8MHz. Serial Flash shall be con- nected to NPCS0. The DataFlash boot reads the dataflash flash status register (Instruction code 0xD7). The data flash is considered as ready if bit 7 of the returned status register is set. If no dataflash is connected or if it does not answer, DataFlash boots exits after a 1000 attempts. End Read the first 8 instructions (0x0b). Decode the sixth ARM vector Yes Read the SerialFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application Send status command (0x05) 8 vectors (except vector 6) are LDR or Branch instruction Yes Start Is status OK ? Jump to next boot solution No No

6242E–ATARM–11-Sep09 AT91SAM9261S If the dataflash is ready, DataFlash boot reads the first 8 words into SRAM (Instruction code “Continuous Read Array” 0x0b) and checks if it corresponds to valid exception vectors according to the Valid Image detection algorithm. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. The DataFlash boot is configured to be compatible with the future design of the DataFlash. Figure 13-7. Serial DataFlash Download End Read the first 8 instructions (32 bytes). Decode the sixth ARM vector Ye s Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application Send status command 8 vectors (except vector 6) are LDR or Branch instruction Ye s Start Is status OK ? Jump to next boot solution No No

6242E–ATARM–11-Sep09 AT91SAM9261S

13.7 NAND Flash Boot

The NAND Flash Boot program searches for a valid application in the NAND Flash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See “Valid Image Detection” on page 76 for more information on Valid Image Detection.

13.7.1 Supported NAND Flash Devices

Any 8 or 16-bits NAND Flash Devices.

13.8 SD Card Boot

The SD Card Boot program searches for a valid application in the SD Card memory. (Boot ROM does not support high capacity SDCards.) It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If a valid file is found, this application is loaded into inte rnal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader.

13.9 EEPROM Boot

The EEPROM Boot progra m searches for a vali d application in an EEPR OM connected to the TWI address: 0x0050_0000. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See “Valid Image Detection” on page 76 for more information on Valid Image Detection.

13.10 SAM-BA Boot

If no valid DataFlash device has been found during the DataFlash boot sequence, the SAM-BA boot program is performed. The SAM-BA boot principle is to: – Wait for USB Device enumeration. – In parallel, wait for characte r(s) received on the DBGU – Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 13-2.

6242E–ATARM–11-Sep09 AT91SAM9261S  Write commands: Write a byte ( O), a halfword (H) or a word (W) to the target. – Address: Address in hexadecimal. – Value: Byte, halfword or word to write in hexadecimal. – Output: ‘>’.  Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’  Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.  Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ G o (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’  Get Version (V): Return the SAM-BA boot version – Output: ‘>’

13.10.1 DBGU Serial Port

Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send th e application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of Table 13-2. Commands Available through the SAM-BA Boot Command Action Argument(s) Example O write a byte Address, Value# O200001,CA# o read a byte Address,# o200001,# H write a half word Address, Value# H200002,CAFE# h read a half word Address,# h200002,# W write a word Address, Value# W200000,CAFEDECA# w read a word Address,# w200000,# S send a file Address,# S200000,# R receive a file Address, NbOfBytes# R200000,1234# G go Address# G200200# V display version No argument V#

6242E–ATARM–11-Sep09 AT91SAM9261S the binary file must be lower than the SRAM si ze because the Xmodem protocol requires some SRAM memory to work.

13.10.2 Xmodem Protocol

The Xmodem protocol supported is the 128-byte l ength block. This protocol uses a two-charac- ter CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which: – <SOH> = 01 hex – <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – <255-blk #> = 1’s complement of the blk#. – <checksum> = 2 bytes CRC16 Figure 13-8 shows a transmission using this protocol. Figure 13-8. Xmodem Transfer Example

13.10.3 USB Device Port

A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ®, from Windows 98SE to Windows XP ®. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Host Device SOH 01 FE Data[128] CRC CRC C ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK

6242E–ATARM–11-Sep09 AT91SAM9261S Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details.

13.10.3.1 Enumeration Process

The USB protocol is a master/slave protocol. Th is is the host that starts the enumeration send- ing requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. The device also handles some class requests defined in the CDC class. Unhandled requests are STALLed.

13.10.3.2 Communication Endpoints

There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM- BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. Table 13-3. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the curr ent device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Used to set or enable a specific feature. CLEAR_FEATURE Used to clear or disable a specific feature. Table 13-4. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present.

6242E–ATARM–11-Sep09 AT91SAM9261S

13.11 Hardware and Software Constraints

 The DataFlash, SerialFlash, NAND Flash, SDCard (1), and EEPROM downloaded code size must be inferior to 12 Kbytes.  The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap).  The downloaded code must be position-independent or linked at address 0x0000_0000.  The DataFlash must be connected to NPCS0 of the SPI. Note: 1. Boot ROM does not support high capacity SDCards. The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices con- nected could be unintentionally driven at boot time , and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 13-5 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 13-5. Pins Driven during Boot Program Execution Peripheral Pin PIO Line SPI0 MOSI PIOA1 SPI0 MISO PIOA0 SPI0 SPCK PIOA2 SPI0 NPCS0 PIOA3 PIOC NANDCS PIOC14 PIOC NAND OE PIOC0 PIOC NAND WE PIOC1 Address Bus NAND CLE A21 Address Bus NAND ALE A22 MCI0 MCDA0 PIOA0 MCI0 MCCDA PIOA1 MCI0 MCCK PIOA2 MCI0 MCDA1 PIOA4 MCI0 MCDA2 PIOA5 MCI0 MCDA3 PIOA6 TWI TWCK PIOA8

6242E–ATARM–11-Sep09 AT91SAM9261S TWI TWD PIOA7 DBGU DRXD PIOA9 DBGU DTXD PIOA10 Table 13-5. Pins Driven during Boot Program Execution Peripheral Pin PIO Line

6242E–ATARM–11-Sep09 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S 14. Reset Controller (RSTC)

14.1 Overview

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.

14.2 Block Diagram

Figure 14-1. Reset Controller Block Diagram NRST Startup Counter proc_nreset wd_fault periph_nreset backup_neset SLCK Reset State Manager Reset Controller rstc_irq NRST Manager exter_nresetnrst_out Main Supply POR WDRPROC user_reset Backup Supply POR

6242E–ATARM–11-Sep09 AT91SAM9261S

14.3 Functional Description

14.3.1 Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:  proc_nreset: Processor reset line. It also resets the Watchdog Timer.  backup_nreset: Affects all the peripherals powered by VDDBU.  periph_nreset: Affects the whole set of embedded peripherals.  nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Cont roller, either on external events or on soft- ware action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion du ring a programmable ti me, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startu p. The wait de lay is given by the crystal oscillator startup time maximum value that can be foun d in the section Crystal Oscil- lator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con- troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.

14.3.2 NRST Manager

The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager. Figure 14-2. NRST Manager

14.3.2.1 NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. External Reset Timer URSTS URSTEN ERSTL exter_nreset URSTIEN RSTC_MR RSTC_MR RSTC_MR RSTC_SR NRSTL nrst_out NRST rstc_irq Other interrupt sources user_reset

6242E–ATARM–11-Sep09 AT91SAM9261S The level of the pin NRST can be read at any ti me in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit UR STS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.

14.3.2.2 NRST External Reset Control

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed -up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.

14.3.3 BMS Sampling

The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 14-3. BMS Sampling SLCK Core Supply POR output BMS sampling delay = 3 cycles BMS Signal proc_nreset XXX H or L

6242E–ATARM–11-Sep09 AT91SAM9261S

14.3.4 Reset States

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

14.3.4.1 General Reset

A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The pur- pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 2 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Suppl y POR Cell, all resets signals are immedi- ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 shows how he General Reset affects the reset signals. Figure 14-4. Genera Reset State SLCK periph_nreset proc_nreset Backup Supply POR output NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles Startup Time MCK Processor Startup = 2 cycles backup_nreset Any Freq. RSTTYP XXX 0x0 = General Reset XXX Main Supply POR output BMS Sampling

6242E–ATARM–11-Sep09 AT91SAM9261S

14.3.4.2 Wake-up Reset

The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 2 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXT ERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the re set signals are immediately asserted. This tran- sition is synchronous with the output of the Main Supply POR. Figure 14-5. Wake-up State

14.3.4.3 User Reset

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST inpu t signal is resynchronized with SLCK to insure proper behav- ior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. SLCK periph_nreset proc_nreset Main Supply POR output NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) MCK Processor Startup = 2 cycles backup_nreset Any Freq. Resynch. 2 cycles RSTTYP XXX 0x1 = WakeUp Reset XXX

6242E–ATARM–11-Sep09 AT91SAM9261S When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How- ever, if NRST does not rise after EXTERN AL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-6. User Reset State

14.3.4.4 Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at  PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.  PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.)  EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these com- mands can be performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles. SLCK periph_nreset proc_nreset NRST NRST (nrst_out) >= EXTERNAL RESET LENGTH MCK Processor Startup = 2 cycles Any Freq. Resynch. 2 cycles RSTTYP Any XXX Resynch. 2 cycles 0x4 = User Reset

6242E–ATARM–11-Sep09 AT91SAM9261S The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset

14.3.4.5 Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock cycles. When in Watchdog Reset, assertion of t he reset signals depends on the WDRPROC bit in WDT_MR:  If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. SLCK periph_nreset if PERRST=1 proc_nreset if PROCRST=1 Write RSTC_CR NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 2 cycles Any Freq. RSTTYP Any XXX 0x3 = Software Reset Resynch. 1 cycle SRCMP in RSTC_SR

6242E–ATARM–11-Sep09 AT91SAM9261S  If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset si gnal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watc hdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset Only if WDRPROC = 0 SLCK periph_nreset proc_nreset wd_fault NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 2 cycles Any Freq. RSTTYP Any XXX 0x2 = Watchdog Reset

6242E–ATARM–11-Sep09 AT91SAM9261S

14.3.5 Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:  Backup Reset  Wake-up Reset  Watchdog Reset  Software Reset  User Reset Particular cases are listed below:  When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.  When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect.  When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered.

14.3.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:  RSTTYP field: This field gives the type of the last reset, as explained in previous sections.  SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.  NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.  URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 14-9. Reset Controller Status and Interrupt MCK NRST NRSTL 2 cycle resynchronization 2 cycle resynchronization URSTS read RSTC_SRPeripheral Access rstc_irq if (URSTEN = 0) and (URSTIEN = 1)

6242E–ATARM–11-Sep09 AT91SAM9261S

14.4 Reset Controller (RSTC) User Interface

Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. Table 14-1. Register Mapping Offset Register Name Access Reset Back-up Reset 0x00 Control Register RSTC_CR Write-only - 0x04 Status Register (1) RSTC_SR Read-only 0x0000_0001 0x0000_0000 0x08 Mode Register RSTC_MR Read-write - 0x0000_0000

6242E–ATARM–11-Sep09 AT91SAM9261S

14.4.1 Reset Controller Control Register

Name: RSTC_CR Address: 0xFFFFFD00 Access Type:Write-only  PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor.  PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals.  EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– E X T R S T P E R R S T – P R O C R S T

6242E–ATARM–11-Sep09 AT91SAM9261S

14.4.2 Reset Controller Status Register

Name: RSTC_SR Address: 0xFFFFFD04 Access Type:Read-only  URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.  RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.  NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK).  SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RSTTYP Reset Type Comments 0 0 0 General Reset Both VDDCORE and VDDBU rising 0 0 1 Wake Up Reset VDDCORE rising 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor re set required by the software 1 0 0 User Reset NRST pin detected low

6242E–ATARM–11-Sep09 AT91SAM9261S

14.4.3 Reset Controller Mode Register

Name: RSTC_MR Address: 0xFFFFFD08 Access Type:Read-write  URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.  URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.  ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– E R S T L 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S 15. Real-time Timer (RTT)

15.1 Overview

The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt and/or triggers an alarm on a programmed value.

15.2 Block Diagram

Figure 15-1. Real-time Timer

15.3 Functional Description

The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit va lue. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 2 32 seconds, corre- sponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free -running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the st atus register is clear ed two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent se veral executions of the interrupt handler, the interrupt must be disabled in the interrupt ha ndler and re-enabled when the status register is clear. SLCK RTPRES RTTINC ALMS 16-bit Divider 32-bit Counter ALMV CRTV RTT_MR RTT_VR RTT_AR RTT_SR RTTINCIEN RTT_MR ALMIEN rtt_int RTT_MR set set RTT_SR read RTT_SR reset reset RTT_MR reload rtt_alarm RTTRST RTT_MR RTTRST

6242E–ATARM–11-Sep09 AT91SAM9261S The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advis- able to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is pro- grammed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately re loads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). Figure 15-2. RTT Counting Prescaler ALMVALMV-10 ALMV+1 RTPRES - 1 RTT APB cycle read RTT_SR ALMS (RTT_SR) APB Interface MCK RTTINC (RTT_SR) ALMV+2 ALMV+3... APB cycle

6242E–ATARM–11-Sep09 AT91SAM9261S

15.4 Real-time Timer (RTT) User Interface

Table 15-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read-write 0x0000_8000 0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000

6242E–ATARM–11-Sep09 AT91SAM9261S

15.4.1 Real-time Timer Mode Register

Name: RTT_MR Address: 0xFFFFFD20 Access Type: Read/Write  RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES … 0: The prescaler period is equal to RTPRES.  ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt.  RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt.  RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R T T R S T R T T I N C I E N A L M I E N 15 14 13 12 11 10 9 8 RTPRES 76543210 RTPRES

6242E–ATARM–11-Sep09 AT91SAM9261S

15.4.2 Real-time Timer Alarm Register

Name: RTT_AR Address: 0xFFFFFD24 Access Type: Read/Write  ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.

15.4.3 Real-time Timer Value Register

Name: RTT_VR Address: 0xFFFFFD28 Access Type: Read-only  CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 31 30 29 28 27 26 25 24 ALMV 23 22 21 20 19 18 17 16 ALMV 15 14 13 12 11 10 9 8 ALMV 76543210 ALMV 31 30 29 28 27 26 25 24 CRTV 23 22 21 20 19 18 17 16 CRTV 15 14 13 12 11 10 9 8 CRTV 76543210 CRTV

6242E–ATARM–11-Sep09 AT91SAM9261S

15.4.4 Real-time Timer Status Register

Name: RTT_SR Address: 0xFFFFFD2C Access Type: Read-only  ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.  RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S 16. Periodic Interval Timer (PIT)

16.1 Overview

The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.

16.2 Block Diagram

Figure 16-1. Periodic Interval Timer

16.3 Functional Description

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis- ter (PIT_SR) rises and triggers an interrupt , provided the interrupt is enabled (PITIEN in PIT_MR). 20-bit Counter MCK/16 PIV PIT_MR CPIV PIT_PIVR PICNT 12-bit Adder read PIT_PIVR CPIV PICNT PIT_PIIR PITSPIT_SR set reset PITIEN PIT_MR pit_irq MCK Prescaler

6242E–ATARM–11-Sep09 AT91SAM9261S Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is rese t and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For exam- ple, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITE N bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is re set (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN MCK Prescaler PIVPIV - 10 PITEN CPIV 1 restarts MCK Prescaler 0 1 APB cycle read PIT_PIVR 0PICNT PITS (PIT_SR) MCK APB Interface APB cycle

6242E–ATARM–11-Sep09 AT91SAM9261S

16.4 Periodic Interval Time r (PIT) User Interface

Table 16-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read-write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000

6242E–ATARM–11-Sep09 AT91SAM9261S

16.4.1 Periodic Interval Timer Mode Register

Name: PIT_MR Address: 0xFFFFFD30 Access Type: Read/Write  PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).  PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled.  PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– P I V 15 14 13 12 11 10 9 8 PIV 76543210 PIV

6242E–ATARM–11-Sep09 AT91SAM9261S

16.4.2 Periodic Interval Timer Status Register

Name: PIT_SR Address: 0xFFFFFD34 Access Type: Read-only  PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

16.4.3 Periodic Interval Timer Value Register

Name: PIT_PIVR Address: 0xFFFFFD38 Access Type: Read-only Reading this register clears PITS in PIT_SR.  CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.  PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

16.4.4 Periodic Interval Timer Image Register

Name: PIT_PIIR Address: 0xFFFFFD3C Access Type: Read-only  CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.  PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 31 30 29 28 27 26 25 24 PICNT 23 22 21 20 19 18 17 16 PICNT CPIV 15 14 13 12 11 10 9 8 CPIV 76543210 CPIV 31 30 29 28 27 26 25 24 PICNT 23 22 21 20 19 18 17 16 PICNT CPIV 15 14 13 12 11 10 9 8 CPIV 76543210 CPIV

6242E–ATARM–11-Sep09 AT91SAM9261S 17. Watchdog Timer (WDT)

17.1 Overview

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.

17.2 Block Diagram

Figure 17-1. Watchdog Timer Block Diagram = 0 set resetread WDT_SR or reset wdt_fault (to Reset Controller) set reset WDFIEN wdt_int WDT_MR SLCK1/128 12-bit Down Counter Current Value WDD WDT_MR <= WDD WDV WDRSTT WDT_MR WDT_CR reload WDUNF WDERR reload write WDT_MR WDRSTEN WDT_MR

6242E–ATARM–11-Sep09 AT91SAM9261S

17.3 Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_M R). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WD T_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer under- flow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog c ounter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR. Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarti ng the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow ) and WDERR (Watchdog Error) trigger an inter- rupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 17-2. Watchdog Behavior WDV WDD WDT_CR = WDRSTT Watchdog Fault Normal behavior Watchdog Error Watchdog Underflow FFF if WDRSTEN is 1 if WDRSTEN is 0 Forbidden Window Permitted Window

6242E–ATARM–11-Sep09 AT91SAM9261S

17.4 Watchdog Timer (WDT) User Interface

Table 17-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only - 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000

6242E–ATARM–11-Sep09 AT91SAM9261S

17.4.1 Watchdog Timer Control Register

Register Name:WDT_CR Address: 0xFFFFFD40 Access Type: Write-only  WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

17.4.2 Watchdog Timer Mode Register

Register Name: WDT_MR Address: 0xFFFFFD44 Access Type: Read-write Once  WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter.  WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt.  WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset.  WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.  WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.  WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state.  WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state.  WDDIS: Watchdog Disable 31 30 29 28 27 26 25 24 WDIDLEHLT WDDBGHLT WDD 23 22 21 20 19 18 17 16 WDD 15 14 13 12 11 10 9 8 WDDIS WDRPROC WDRSTEN WDFIEN WDV 76543210 WDV

6242E–ATARM–11-Sep09 AT91SAM9261S 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.

6242E–ATARM–11-Sep09 AT91SAM9261S

17.4.3 Watchdog Timer Status Register

Register Name: WDT_SR Address: 0xFFFFFD48 Access Type: Read-only  WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.  WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S 18. Shutdown Controller (SHDWC)

18.1 Overview

The Shutdown Controller controls the pow er supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines.

18.2 Block Diagram

Figure 18-1. Shutdown Controller Block Diagram

18.3 I/O Lines Description

18.4 Product Dependencies

18.4.1 Power Management

The Shutdown Controller is continuously clock ed by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller.

18.5 Functional Description

The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. Shutdown Wake-up Shutdown Output Controller SHDN WKUP0 SHDW WKMODE0 Shutdown Controller RTT Alarm RTTWKEN SHDW_MR SHDW_SHMR SHDW_SR CPTWK0 WAKEUP0 RTTWK SHDW_SR set set reset reset read SHDW_SR read SHDW_SR SLCK SHDW_SR Table 18-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output

6242E–ATARM–11-Sep09 AT91SAM9261S A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter pro- viding the main power supplies of the system , and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system. The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at 1. The shutdow n is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any level change on WKUP 0. The detection can also be disabled. Pro- gramming is performed by defining WKMODE0. Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corre- sponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the read of SHDW_SR. The Shutdown Controller can be programmed so as to activate the wake-up using the RTT alarm (the detection of the rising edge of the RT T alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the RTTWKEN fields. When enabled, the detec- tion of the RTT alarm is reported in the RTTWK bi t of the SHDW_SR Status register. It is reset after the read of SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails.

6242E–ATARM–11-Sep09 AT91SAM9261S

18.6 Shutdown Controller (SHDWC) User Interface

18.6.1 Shutdown Control Register

Register Name: SHDW_CR Address: 0xFFFFFD10 Access Type: Write-only  SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. Table 18-2. Register Mapping Offset Register Name Access Reset 0x00 Shutdown Control Register SHDW_CR Write-only - 0x04 Shutdown Mode Register SHDW_MR Read-write 0x0000_0303 0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

18.6.2 Shutdown Mode Register

Register Name: SHDW_MR Address: 0xFFFFFD14 Access Type: Read/Write  WKMODE0: Wake-up Mode 0  CPTWK0: Counter on Wake-up 0 Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake- up event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released (CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.  RTTWKEN: Real-time Timer Wake-up Enable 0 = The RTT Alarm signal has no effect on the Shutdown Controller. 1 = The RTT Alarm signal forces the de-assertion of the SHDN pin. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– – – 76543210 CPTWK0 – – WKMODE0 WKMODE[1:0] Wake-up Inpu t Transition Selection 0 0 None. No detection is performed on the wake-up input 0 1 Low to high level 1 0 High to low level 1 1 Both levels change

6242E–ATARM–11-Sep09 AT91SAM9261S

18.6.3 Shutdown Status Register

Register Name: SHDW_SR Address: 0xFFFFFD18 Access Type: Read-only  WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. 1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.  RTTWK: Real-time Timer Wake-up 0 = No wake-up alarm from the RTT occurred since the last read of SHDW_SR. 1 = At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S 19. General Purpose Backup Register (GPBR)

19.1 Overview

The System Controller embeds 4 general-purpose backup registers.

19.2 General Purpose Backup Regist ers (GPBR) User Interface

Table 19-1. Register Mapping Offset Register Name Access Reset 0x0 General Purpose Backup Register 0 SYS_GPBR0 Read-write – 0xC General Purpose Backup Register 3 SYS_GPBR 3 Read-write –

6242E–ATARM–11-Sep09 AT91SAM9261S

19.2.1 General Purpose Backup Register x

Register Name:SYS_GPBRx Addresses: 0xFFFFFD50 [0], 0xFFFFFD54 [1], 0xFFFFFD58 [2], 0xFFFFFD5C [3] Access Type: Read-write  GPBR_VALUEx: Value of GPBR x 31 30 29 28 27 26 25 24 GPBR_VALUEx 23 22 21 20 19 18 17 16 GPBR_VALUEx 15 14 13 12 11 10 9 8 GPBR_VALUEx 76543210 GPBR_VALUEx

6242E–ATARM–11-Sep09 AT91SAM9261S 20. AT91SAM9261S Bus Matrix

20.1 Overview

The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 5 AHB Masters to 5 AHB Slaves. The Bus Matrix user interface is compliant with the ARM Advanced Peripheral Bus and provides 5 Special Function Registers (MATRIX_SFR) that allow the Bus Matrix to support application-specific features.

20.2 Memory Mapping

The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory mappings. Depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM, internal Flash, etc.) becomes possible. The Bus Matrix user interface provides a Master Configuration Register (MATRIX_MCFG) that performs a remap action for every master independently.

20.3 Special Bus Granting Techniques

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This technique reduces latency at first accesses. The bus granting technique sets a default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters; no default master, last access master and fixed default master.

20.3.1 No Default Master

At the end of current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode.

20.3.2 Last Access Master

At the end of current access, if no other request is pending, the slave remains connected to the last master that performs an access request.

20.3.3 Fixed Default Master

At the end of current access, if no other request is pending, the slave remains connected to its fixed default master. Unlike last access master, the fixed master does not change unless the user changes it by a software action. To change from one kind of default master to another, the Bus Matrix user interface provides 5 Slave Configuration Registers, one for each slave, that set default master for each slave. The Slave Configuration Register contains two fields; DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE flag selects the default master type (no default, last access master, fixed default master) whereas the 3-bit FIXED_DEFMSTR flag selects a fixed default master provided that DEFMSTR_TYPE is set to a fixed default master. See Section 20.5 “Bus Matrix (MATRIX) User Interface”.

6242E–ATARM–11-Sep09 AT91SAM9261S

20.4 Arbitration

The Bus Matrix provides an arbitration functi on that reduces latency when conflicting cases occur, i.e., when two or more masters try to access the same slave at the same time. The Bus Matrix arbitration mechanism uses slightly modified round-robin algorithms that grant the bus for the first access to a certain master depending on parameters located in the slave’s Slave Con- figuration Register. There are three round-robin algorithm types:  Round-Robin arbitration without default master  Round-Robin arbitration with last access master  Round-Robin arbitration with fixed default master

20.4.1 Round-Robin Arbitration Without Default Master

This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access. Arbitration without default master can be used for masters that perform significant bursts.

20.4.2 Round-Robin Arbitration With Last Access Master

This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs the access. Other non-privileged masters still obtain one latency cycle if they want to access the same slave. This technique can be used for masters that perform mainly single accesses.

20.4.3 Round-Robin Arbitration With Fixed Default Master

This is a biased round-robin algorithm. It allows the Bus Matrix arbiters to remove one latency cycle for the fixed master of a slave. At the end of the current access, the slave remains con- nected to its fixed default master. Any request attempted by this fixed default master does not cause any latency, wher eas other non-privilege d masters still obtain one latency cycle. This technique can be used for masters that perform mainly single accesses.

6242E–ATARM–11-Sep09 AT91SAM9261S

20.5 Bus Matrix (MATRIX) User Interface

Table 20-1. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register MATRIX_MCFG Write only 0x00000000 0x0004 Slave Configuration Register 0 MATRIX_SCFG0 Read-write 0x00000010 0x0008 Slave Configuration Register 1 MATRIX_SCFG1 Read-write 0x00000010 0x000C Slave Configuration Register 2 MATRIX_SCFG2 Read-write 0x00000010 0x0010 Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x00000010 0x0014 Slave Configuration Register 4 MATRIX_SCFG4 Read-write 0x00000010 0x0018 - 0x002C Reserved – – – 0x0030 EBI Chip Select Assignment Register EBI_CSA Read-write 0x00000000 0x0034 USB Pad Pull-up Control Register USB_PUCR Read-write 0x00000000

6242E–ATARM–11-Sep09 AT91SAM9261S

20.5.1 Bus Matrix Master Configuration Register

Name: MATRIX_MCFG Address: 0xFFFFEE00 Access Type:Write only  RCBx: Remap Command Bit for AHB Master x 0: No effect 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

20.5.2 Bus Matrix Slave Configuration Registers

Name: MATRIX_SCFG0...MATRIX_SCFG4 Address: 0xFFFFEE04 Access Type:Read-write  SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave. This limit has been set to avoid locking very slow slaves when very long bursts are used. This limit should not be very small. An unreasonably small va lue breaks every burst and the Bus Matrix spends its time arbitrating without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.  DEFMASTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in one cycle latency for the first transfer of a burst. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave remains connected to the last mas- ter that accessed it. This results in not having the one cycle latency when the last master is trying to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master re quest is pending, the slave connects with the fixed master that has its index in FIXED_DEFMSTR register. This results in not having the one cycle latency when the fixed master is trying to access the slave again.  FIXED_DEFMSTR: Fixed I ndex of Default Master This is the index of the Fixed Default Master for this slave. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – FIXED_DEFMSTR DEFMSTR_TYPE 15 14 13 12 11 10 9 8 76543210 SLOT_CYCLE

6242E–ATARM–11-Sep09 AT91SAM9261S

20.5.3 EBI Chip Select Assignment Register

Name: EBI_CSA Address: 0xFFFFEE30 Access Type:Read-write Reset: 0x0000_0000  EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip Select 1 is assigned to the Static Memory Controller. 1 = EBI Chip Select 1 is assigned to the SDRAM Controller.  EBI_CS3A: EBI Chip Select 3 Assignment 0 = EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC. 1 = EBI Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.  EBI_CS4A: EBI Chip Select 4 Assignment 0 = EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC. 1 = EBI Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.  EBI_CS5A: EBI Chip Select 5 Assignment 0 = EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined by the SMC. 1 = EBI Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.  EBI_DBPUC: EBI Data Bus Pull-Up Configuration 0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply. 1 = EBI D0 - D15 Data Bus bits are not internally pulled-up. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – EBI_CS5A EBI_CS4A EBI_CS3A – EBI_CS1A –

6242E–ATARM–11-Sep09 AT91SAM9261S

20.5.4 USB Pad Pull-up Control Register

Name: USB_PUCR Address: 0xFFFFEE34 Access Type:Read-write Reset: 0x0000_0000  UDP_PUP_ON: UDP Pad Pull-up Enable 0: Pad pull-up disabled 1: Pad pull-up enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 543210

6242E–ATARM–11-Sep09 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S 21. External Bus Interface (EBI)

21.1 Overview

The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memo ry Controller of an ARM-based device. The Static Memory and SDRAM Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM. The EBI also supports the CompactFlash and the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to eight external devices , each assigned to eight address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to ei ght chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external Memory Controllers.

6242E–ATARM–11-Sep09 AT91SAM9261S

21.2 Block Diagram

Figure 21-1 shows the organization of the External Bus Interface. Figure 21-1. Organization of the External Bus Interface External Bus Interface D[15:0] A[15:2], A[21:18] PIO MUX Logic NAND Flash Logic CompactFlash Logic User Interface Chip Select Assignor Static Memory Controller SDRAM Controller Bus Matrix APB AHB Address Decoders A16/BA0 A0/NBS0 A1/NWR2/NBS2 A17/BA1 NCS0 NCS3/NANDCS NRD/CFOE NCS1/SDCS NCS2 NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS CAS SDWE D[31:16] A[24:23] A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 NCS6/NANDOE NCS7/NANDWE CFCE1 CFCE2 NWAIT SDA10 A22/REG

6242E–ATARM–11-Sep09 AT91SAM9261S

21.3 I/O Lines Description

Table 21-1. I/O Lines Description Name Function Type Active Level EBI D0 - D31 Data Bus I/O A0 - A25 Address Bus Output NWAIT External Wait Signal Input Low SMC NCS0 - NCS7 Chip Select Lines Output Low NWR0 - NWR3 Write Signals Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0 - NBS3 Byte Mask Signals Output Low EBI for CompactFlash Support CFCE1 - CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash I/O Read Signal Output Low CFIOW CompactFlash I/O Write Signal Output Low CFRNW CompactFlash Read Not Write Signal Output CFCS0 - CFCS1 CompactFlash Chip Select Lines Output Low EBI for NAND Flash Support NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low SDRAM Controller SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Line Output Low BA0 - BA1 Bank Select Output SDWE SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low NWR0 - NWR3 Write Signals Output Low NBS0 - NBS3 Byte Mask Signals Output Low SDA10 SDRAM Address 10 Line Output

6242E–ATARM–11-Sep09 AT91SAM9261S The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 21-2 on page 140 details the connections between the two Memory Controllers and the EBI pins.

21.4 Application Example

21.4.1 Hardware Interface

Table 21-3 and Table 21-4 detail the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 21-2. EBI Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines SMC I/O Lines NWR1/NBS1/CFIOR NBS1 NWR1/NUB A0/NBS0 Not Supported SMC_A0/NLB A1/NBS2/NWR2 Not Supported SMC_A1 A[11:2] SDRAMC_A[9:0] SMC_A[11:2] SDA10 SDRAMC_A1 0 Not Supported A12 Not Supported SMC_A12 A[14:13] SDRAMC_A[12:11] SMC_A[14:13] A[25:15] Not Supported SMC_A[25:15] Table 21-3. EBI Pins and External Static Devices Connections Pins Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device Controller SMC D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D8 - D15 – D8 - D15 D8 - D15 D8 - D15 D8 - 15 D8 - 15 D16 - D23 – – – D16 - D23 D16 - D23 D16 - D23 D24 - D31 – – – D24 - D31 D24 - D31 D24 - D31 A0/NBS0 A0 – NLB – NLB (3) BE0(5) A1/NWR2/NBS2 A1 A0 A0 WE (2) NLB(4) BE2(5) NCS0 CS CS CS CS CS CS NCS1/SDCS CS CS CS CS CS CS NCS2 CS CS CS CS CS CS NCS3/NANDCS CS CS CS CS CS CS NCS4/CFCS0 CS CS CS CS CS CS

6242E–ATARM–11-Sep09 AT91SAM9261S Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. NWRx enables corresponding byte x writes. (x = 0, 1, 2 or 3) 3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5. BEx: Byte x Enable (x = 0,1,2 or 3) NCS5/CFCS1 CS CS CS CS CS CS NCS6/NAND0E CS CS CS CS CS CS NCS7/NANDWE CS CS CS CS CS CS NRD/CFOE OE OE OE OE OE OE NWR0/NWE WE WE (1) WE WE (2) WE WE NWR1/NBS1 – WE (1) NUB WE (2) NUB(3) BE1(5) NWR3/NBS3 – – – WE (2) NUB(4) BE3(5) Table 21-3. EBI Pins and External Static Devices Connections (Continued) Pins Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device Controller SMC Table 21-4. EBI Pins and External Devices Connections Pins Pins of the Interfaced Device SDRAM Compact Flash Compact Flash True IDE Mode NAND Flash Controller SDRAMC SMC D0 - D7 D0 - D7 D0 - D7 D0 - D7 I/O0-I/O7 D8 - D15 D8 - D15 D8 - 15 D8 - 15 I/O8-I/O15 D16 - D31 D16 - D31 – – – A0/NBS0 DQM0 A0 A0 – A1/NWR2/NBS2 DQM2 A1 A1 – A11 A9 – – – SDA10 A10 – – – A12 – – – – A15 – – – – A16/BA0 BA0 – – – A17/BA1 BA1 – – – A18 - A20 – – – – A21 – – – CLE A22 – REG REG ALE

6242E–ATARM–11-Sep09 AT91SAM9261S Notes: 1. Not directly connected to the Compac tFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. CE connection depends on the NAND Flash. For standard NAND Flash devices, it must be connected to any free PIO line. For “CE don’t care” NAND Flash devices, it can be connected to either NCS3/NANDCS or to any free PIO line. A23 - A24 – – – – A25 – CFRNW (1) CFRNW(1) – NCS0 – – – – NCS1/SDCS CS – – – NCS2 – – – – NCS3/NANDCS – – – CE (3) NCS4/CFCS0 – CFCS0 (1) CFCS0(1) – NCS5/CFCS1 – CFCS1 (1) CFCS1(1) – NCS6/NANDOE – – – RE NCS7/NANDWE – – – WE NRD/CFOE – OE – – NWR0/NWE/CFWE – WE WE – NWR1/NBS1/CFIOR DQM1 IOR IOR – NWR3/NBS3/CFIOW DQM3 IOW IOW – CFCE1 – CE1 CS0 – CFCE2 – CE2 CS1 – SDCK CLK – – – SDCKE CKE – – – RAS RAS – – – CAS CAS – – – SDWE WE – – – NWAIT – WAIT WAIT – Pxx (2) – CD1 or CD2 CD1 or CD2 – Pxx(2) –– – C E (3) Pxx(2) –– – R D Y Table 21-4. EBI Pins and External Devices Connections (Continued) Pins Pins of the Interfaced Device SDRAM Compact Flash Compact Flash True IDE Mode NAND Flash Controller SDRAMC SMC

6242E–ATARM–11-Sep09 AT91SAM9261S

21.4.2 Connection Examples

Figure 21-2 shows an example of connections between the EBI and external devices. Figure 21-2. EBI Connections to Memory Devices

21.5 Product Dependencies

21.5.1 I/O Lines

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica- tion, they can be used for other purposes by the PIO Controller. EBI D0-D31 A2-A15 RAS CAS SDCK SDCKE SDWE A0/NBS0 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS1/SDCS D0-D7 D8-D15 A16/BA0 A17/BA1 A18-A25 A10 SDA10 SDA10 A2-A11, A13 NCS0 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A16/BA0 A17/BA1 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 A10 SDA10 A2-A11, A13 A16/BA0 A17/BA1 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 D16-D23 D24-D31 A10 SDA10 A2-A11, A13 A16/BA0 A17/BA1 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 A10 SDA10 A2-A11, A13 A16/BA0 A17/BA1 NBS0 NBS1 NBS3 NBS2 NRD NWR0/NWE 128K x 8 SRAM 128K x 8 SRAM D0-D7 D0-D7A0-A16 A0-A16A1-A17 A1-A17 CS CS OE WE D0-D7 D8-D15 OE WENRD/NOE A0/NWR0/NBS0 NRD/NOE NWR1/NBS1 SDWE SDWESDWE SDWE

6242E–ATARM–11-Sep09 AT91SAM9261S

21.6 Functional Description

The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter- nal memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements:  Static Memory Controller (SMC)  SDRAM Controller (SDRAMC)  A chip select assignment feature that assigns an AHB address space to the external devices  A multiplex controller circuit that shares the pins between the different Memory Controllers  Programmable CompactFlash support logic  Programmable NAND Flash support logic

21.6.1 Bus Multiplexing

The EBI offers a complete set of control signal s that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in or der to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Controller without delaying the other external Memory Controller accesses.

21.6.2 Pull-up Control

The EBI_CSA register in the Bus Matrix User Interface permits enabling of on-chip pull-up resis- tors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by programming the appro- priate PIO controller.

21.6.3 Static Memory Controller

For information on the Static Memory Controller, refer to the Static Memory Controller section.

21.6.4 SDRAM Controller

For information on the SDRAM Controller, refer to the SDRAM section.

21.6.5 CompactFlash Support

The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the St atic Memory Controller (SMC) on the NCS4 and/or NCS5 address space. Programming the CS4A and/or CS5A bit of the EBI_CSA Register to the appropriate value enables this logic. For details on this register, refer to the Bus Matrix User Interface section. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.

6242E–ATARM–11-Sep09 AT91SAM9261S

21.6.5.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode

Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. The different modes are accessed through a specific memory mapping as illustrated on Figure 21-3. A[23:21] bits of the transfer address are used to select the desired mode as described in Table 21-5 on page 145. Figure 21-3. CompactFlash Memory Mapping Note: The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in True IDE mode).

21.6.5.2 CFCE1 and CFCE2 signals

To cover all types of access, the SMC must be al ternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS4 and or NCS5). The Chip Select Register (DBW field in the corresponding Chip Select Mode Register) of the NCS4 and/or NCS5 address space must be set as shown in Table 21-6 to enable the required access type. NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. Table 21-5. CompactFlash Mode Selection A[23:21] Mode Base Address

000 Attribute Memory

010 Common Memory

100 I/O Mode

110 True IDE Mode

111 Alternate True IDE Mode

Attribute Memory Mode Space Common Memory Mode Space I/O Mode Space True IDE Mode Space True IDE Alternate Mode Space Offset 0x00E0 0000 Offset 0x00C0 0000 Offset 0x0080 0000 Offset 0x0040 0000 Offset 0x0000 0000

6242E–ATARM–11-Sep09 AT91SAM9261S The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section.

21.6.5.3 Read/Write Signals

In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deac- tivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 21-4 on page 147 demonstrates a schematic representation of this logic. Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. Table 21-6. CFCE1 and CFCE2 Truth Table Mode CFCE2 CFCE1 DBW Comment SMC Access Mode Attribute Memory NBS1 NBS0 16 bits Access to Ev en Byte on D[7:0] Byte Select Common Memory NBS1 NBS0 16bits Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Byte Select 1 0 8 bits Access to Odd Byte on D[7:0] Don’t Care I/O Mode NBS1 NBS0 16 bits Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Byte Select 1 0 8 bits Access to Odd Byte on D[7:0] Don’t Care True IDE Mode Task File 1 0 8 bits Access to Even Byte on D[7:0] Access to Odd Byte on D[7:0] Don’t Care Data Register 1 0 16 bits Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Byte Select Alternate True IDE Mode Control Register Alternate Status Read 01 Don’t Care Access to Even Byte on D[7:0] Don’t Care Drive Address 0 1 8 bits Access to Odd Byte on D[7:0] Don’t Care True IDE Standby Mode or Address Space is not assigned to CF Don’t Care Don’t Care Don’t Care

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 21-4. CompactFlash Read/Write Control Signals

21.6.5.4 Multiplexing of CompactFlash Signals on EBI Pins

Table 21-8 on page 147 and Table 21-9 on page 148 illustrate the multiplexing of the Compact- Flash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 21-8 are strictly dedicated to the CompactFlash interface as soon as the CS4A and/or CS5A field of the EBI_CSA Register is set. These pins must not be used to drive any other memory devices. The EBI pins in Table 21-9 on page 148 remain shared between all memory areas when the cor- responding CompactFlash interface is enabled (CS4A = 1 and/or CS5A = 1). SMC NRD NWR0_NWE A21 CFIOR CFIOW CFOE CFWE CompactFlash Logic External Bus Interface A20 Table 21-7. CompactFlash Mode Selection Mode Base Address CFOE CFWE CFIOR CFIOW Attribute Memory Common Memory NRD NWR0_NWE 1 1 I/O Mode 1 1 NRD NWR0_NWE True IDE Mode 0 1 NRD NWR0_NWE Table 21-8. Dedicated CompactFlash Interface Multiplexing Pins CompactFlash Signals EBI Signals CS4A = 1 CS5A = 1 CS4A = 0 CS5A = 0 NCS4/CFCS0 CFCS0 NCS4 NCS5/CFCS1 CFCS1 NCS5

6242E–ATARM–11-Sep09 AT91SAM9261S

21.6.5.5 Application Example

Figure 21-5 on page 149 illustrates an example of a CompactFlash application.CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT sig- nal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 21-9. Shared CompactFlash Interface Multiplexing Pins Access to CompactFlash Device Access to Other EBI Devices CompactFlash Signals EBI Signals NRD/CFOE CFOE NRD NWR0/NWE/CFWE CFWE NWR0/NWE NWR1/NBS1/CFIOR CFIOR NWR1/NBS1 NWR3/NBS3/CFIOW CFIOW NWR3/NBS3 A25/CFRNW CFRNW A25

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 21-5. CompactFlash Application Example

21.6.6 NAND Flash Support

The EBI integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the CS3A field in the EBI_CSA Register in the Bus Matrix User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to the Bus Matrix User Interface section. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x40000000 and 0x4FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. For details on these waveforms, refer to the Static Memory Controller section. The NANDOE and NANDWE signals are multiplexed with NCS6 and NCS7 signals of the Static Memory Controller. This multiplexing is controlled in the MUX logic part of the EBI by the CS3A bit in the in the EBI_CSA Register For details on this register, refer to the Bus Matrix User Inter- face Section. NCS6 and NCS7 become unavailable. Performing an access within the address space reserved to NCS6 and NCS7 (i.e., between 0x70000000 and 0x8FFF FFFF) may lead to an unpredictable outcome. CompactFlash ConnectorEBI D[15:0] /OEDIR _CD1 _CD2 /OE D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NRD/CFOE A[10:0] _REG _OE _WE _IORD _IOWR _CE1 _CE2 NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 _WAITNWAIT

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 21-6. NAND Flash Signal Multiplexing on EBI Pins The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose. The command, address or data words on the data bus of the NAND Flash device are di stinguished by using their address within the NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) sig- nals are connected to PIO lines. The CE signa l then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. SMC NRD NWR0_NWE NANDOE NANDWE NAND Flash Logic NCS3 MUX Logic CS3A NCS7_NANDWE NCS6_NANDOE CS3A NCS7 NCS6

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 21-7. NAND Flash Application Example Note: The External Bus Interface is also able to support 16-bits devices. D[7:0] ALE NCS7/NANDWE NCS6/NANDOE NOE NWE A[22:21] CLE AD[7:0] PIO R/B EBI CE NAND Flash PIO NCS3/NANDCS Not Connected

6242E–ATARM–11-Sep09 AT91SAM9261S

21.7 Implementation Examples

All the hardware configurations are given for illustration only. The user should refer to the mem- ory manufacturer web site to check the device availability. 21.7.1 16-bit SDRAM

21.7.1.1 Hardware Configuration

21.7.1.2 Software Configuration

The following configuration has to be performed:  Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space.  Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller. D13 D12 D11 D14 RAS D10 CAS SDA10 SDCK SDWE SDCKE D15 A14 BA0 A10 A13 BA1 A11 RAS CAS SDA10 SDWE SDCKE SDCK CFIOR_NBS1_NWR1 SDCS_NCS1 BA0 BA1 D[0..15] A[0..14] 3V3

256 Mbits

(Not used A12) TSOP54 PACKAGE C1 100NFC1 100NF C7 100NFC7 100NF C2 100NFC2 100NF MT48LC16M16A2 MT48LC16M16A2 A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 A1022 BA020 A1236 DQ0 2 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 10 DQ6 11 DQ7 13 DQ8 42 DQ9 44 DQ10 45 DQ11 47 DQ12 48 DQ13 50 DQ14 51 DQ15 53 VDD 1 VSS 28 VSS 41 VDDQ 3VDD 27 N.C40 CLK38 CKE37 DQML15 DQMH39 CAS17 RAS18 WE16 CS19 VDDQ 9 VDDQ 43 VDDQ 49 VSSQ 6 VSSQ 12 VSSQ 46 VSSQ 52 VDD 14 VSS 54 A1135 BA121 C3 100NFC3 100NF C4 100NFC4 100NF C5 100NFC5 100NF C6 100NFC6 100NF

6242E–ATARM–11-Sep09 AT91SAM9261S 21.7.2 32-bit SDRAM

21.7.2.1 Hardware Configuration

21.7.2.2 Software Configuration

The following configuration has to be performed:  Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space.  Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller. CAS SDCKE SDCK RAS SDWE SDA10 D13 D18 D12 D22 D28 D11 D26 D21 D14 D24 D23 RAS D27 D19 D10 D31 D17 CAS SDA10 D25 D29 D16 SDCK D20 SDWE SDCKE D30 D15 BA0 A11 A14 BA1 A13 A3A3 A10 BA0 A10 A13 BA1 A14 A11 RAS CAS SDA10 SDWE SDCKE SDCK CFIOW_NBS3_NWR3CFIOR_NBS1_NWR1 SDCS_NCS1 BA0 BA1 D[0..31] A[0..14] 3V33V3

256 Mbits 256 Mbits

(Not used A12) TSOP54 PACKAGE C11 100NFC11 100NF C9 100NFC9 100NF C1 100NFC1 100NF C12 100NFC12 100NF MT48LC16M16A2 MT48LC16M16A2 A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 A1022 BA020 A1236 DQ0 2 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 10 DQ6 11 DQ7 13 DQ8 42 DQ9 44 DQ10 45 DQ11 47 DQ12 48 DQ13 50 DQ14 51 DQ15 53 VDD 1 VSS 28 VSS 41 VDDQ 3VDD 27 N.C40 CLK38 CKE37 DQML15 DQMH39 CAS17 RAS18 WE16 CS19 VDDQ 9 VDDQ 43 VDDQ 49 VSSQ 6 VSSQ 12 VSSQ 46 VSSQ 52 VDD 14 VSS 54 A1135 BA121 C7 100NFC7 100NF C13 100NFC13 100NF C8 100NFC8 100NF C14 100NFC14 100NF MT48LC16M16A2 MT48LC16M16A2 A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 A1022 BA020 A1236 DQ0 2 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 10 DQ6 11 DQ7 13 DQ8 42 DQ9 44 DQ10 45 DQ11 47 DQ12 48 DQ13 50 DQ14 51 DQ15 53 VDD 1 VSS 28 VSS 41 VDDQ 3VDD 27 N.C40 CLK38 CKE37 DQML15 DQMH39 CAS17 RAS18 WE16 CS19 VDDQ 9 VDDQ 43 VDDQ 49 VSSQ 6 VSSQ 12 VSSQ 46 VSSQ 52 VDD 14 VSS 54 A1135 BA121 C2 100NFC2 100NF C3 100NFC3 100NF C4 100NFC4 100NF C5 100NFC5 100NF C6 100NFC6 100NF C10 100NFC10 100NF

6242E–ATARM–11-Sep09 AT91SAM9261S 21.7.3 8-bit NAND Flash

21.7.3.1 Hardware Configuration

21.7.3.2 Software Configuration

The following configuration has to be performed:  Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register located in the bus matrix memory space  Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bit A21 and A22 during accesses.  NANDOE and NANDWE signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.  Configure a PIO line as an input to manage the Ready/Busy signal.  Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. NANDOE NANDWE (ANY PIO) (ANY PIO) ALE CLE D[0..7] 3V3 3V3 2 Gb TSOP48 PACKAGE U1 K9F2G08U0MU1 K9F2G08U0M WE18 N.C6 VCC 37 CE9 RE8 N.C20 WP19 N.C5 N.C1 N.C2 N.C3 N.C4 N.C21 N.C22 N.C23 N.C24 R/B7 N.C26 N.C 27N.C 28 I/O0 29 N.C 34N.C 35 VSS 36 PRE 38N.C 39 VCC 12 VSS 13 ALE17 N.C11 N.C10 N.C14 N.C15 CLE16 N.C25 N.C 33 I/O1 30 I/O3 32I/O2 31 N.C 47 N.C 46 N.C 45 I/O7 44I/O6 43I/O5 42I/O4 41 N.C 40 N.C 48R2 10KR2 10K 100NF 100NF R1 10KR1 10K 100NF 100NF

6242E–ATARM–11-Sep09 AT91SAM9261S 21.7.4 16-bit NAND Flash

21.7.4.1 Hardware Configuration

21.7.4.2 Software Configuration

The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode register of the Static Memory Controller. D14 D11 D12 D10 D13 D15 NANDOE NANDWE (ANY PIO) ALE CLE D[0..15] (ANY PIO) 3V3 3V3 2 Gb TSOP48 PACKAGE R1 10KR1 10K R2 10KR2 10K 100NF 100NF 100NF 100NF U1 MT29F2G16AABWP-ETU1 MT29F2G16AABWP-ET WE18 N.C6 VCC 37 CE9 RE8 N.C20 WP19 N.C5 N.C1 N.C2 N.C3 N.C4 N.C21 N.C22 N.C23 N.C24 R/B7 I/O0 26 I/O8 27 I/O1 28 I/O9 29 N.C34 N.C35 N.C 36PRE 38N.C 39 VCC 12 VSS 13 ALE17 N.C11 N.C10 N.C14 N.C15 CLE16 VSS 25 I/O11 33 I/O2 30 I/O3 32 I/O10 31 I/O15 47 I/O7 46 I/O14 45 I/O6 44 I/O13 43 I/O5 42 I/O12 41 I/O4 40 VSS 48

6242E–ATARM–11-Sep09 AT91SAM9261S

21.7.5 NOR Flash on NCS0

21.7.5.1 Hardware Configuration

21.7.5.2 Software Configuration

The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. A21 A22 A15 A12 A13 A11 A10 A14 A16 D14 D11 D12 D10 D13 D15 A17 A20 A18 A19 D[0..15] A[1..22] NRST NWE NCS0 NRD 3V3 3V3 TSOP48 PACKAGE 100NF 100NF 100NF 100NF AT49BV6416 AT49BV6416 A025 A124 A223 A322 A421 A520 A619 A718 A88 A97 A106 A115 A124 A133 A142 A151 A1648 A1717 A1816 A219 A2010 A1915 WE11 RESET12 WP14 OE28 CE26 VPP13 DQ0 29 DQ1 31 DQ2 33 DQ3 35 DQ4 38 DQ5 40 DQ6 42 DQ7 44 DQ8 30 DQ9 32 DQ10 34 DQ11 36 DQ12 39 DQ13 41 DQ14 43 DQ15 45 VCCQ 47 VSS 27VSS 46 VCC 37

6242E–ATARM–11-Sep09 AT91SAM9261S

21.7.6 Compact Flash

21.7.6.1 Hardware Configuration

WAIT# RESET CF_D3 CF_D2 CF_D1 CF_D0 CF_D7 CF_D6 CF_D5 CF_D4 CF_D11 CF_D10 CF_D9 CF_D8 CF_D15 CF_D14 CF_D13 CF_D12 CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 CF_A2 CF_A1 CF_A0 REG WE OE IOWR IORD CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 CF_A2 CF_A1 CF_A0 CF_D4 CF_D13 CF_D15 CF_D14 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 CF_D6 CF_D5 CF_D3 CF_D2 CF_D1 CF_D0 CE2 CE1 RESET RDY/BSY RDY/BSY WAIT# CFWE (ANY PIO) A25/CFRNW D[0..15] A[0..10] CFCSx A22/REG CFOE CFIOW CFIOR NWAIT (ANY PIO) CFCE2 CFCE1 (ANY PIO) 3V3 3V3 3V3 3V3 3V3 3V3 CFIRQ CFRST MEMORY & I/O MODE (CFCS0 or CFCS1) MN2A SN74ALVC32 MN2A SN74ALVC32 100NF 100NF MN1D 74ALVCH32245 MN1D 74ALVCH32245 4DIRT3 4OET4 4A1N5 4A2N6 4A3P5 4A4P6 4A5R5 4A6R6 4A7T6 4A8T5 4B1 N2 4B2 N1 4B3 P2 4B4 P1 4B5 R2 4B6 R1 4B7 T1 4B8 T2 MN1C 74ALVCH32245 MN1C 74ALVCH32245 3DIRJ3 3OEJ4 3A1J5 3A2J6 3A3K5 3A4K6 3A5L5 3A6L6 3A7M5 3A8M6 3B1 J2 3B2 J1 3B3 K2 3B4 K1 3B5 L2 3B6 L1 3B7 M2 3B8 M1 47K 47K MN3B SN74ALVC125 MN3B SN74ALVC125 47K 47K MN1B 74ALVCH32245 MN1B 74ALVCH32245 2DIRH3 2OEH4 2A1 E5 2A2 E6 2A3 F5 2A4 F6 2A5 G5 2A6 G6 2A7 H5 2A8 H6 2B1E2 2B2E1 2B3F2 2B4F1 2B5G2 2B6G1 2B7H2 2B8H1 VCC GND MN4 SN74LVC1G125-Q1 VCC GND MN4 SN74LVC1G125-Q1 5 1 MN3A SN74ALVC125 MN3A SN74ALVC125 10K 10K MN2B SN74ALVC32 MN2B SN74ALVC32 MN3C SN74ALVC125 MN3C SN74ALVC125 10K 10K 100NF 100NF N7E50-7516VY-20 N7E50-7516VY-20 GND 1 D32 D43 D54 D65 D76 CE1#7 A108 OE#9 A910 A811 A712 VCC 13 A614 A515 A416 A317 A218 A119 A020 D021 D122 D223 WP24 CD2#25 CD1#26 D1127 D1228 D1329 D1430 D1531 CE2#32 VS1# 33 IORD#34 IOWR#35 WE#36 RDY/BSY 37 VCC 38 CSEL# 39 VS2# 40 RESET41 WAIT#42 INPACK# 43 REG#44 BVD2 45 BVD1 46 D847 D948 D1049 GND 50 MN1A 74ALVCH32245 MN1A 74ALVCH32245 1A1 A5 1A2 A6 1A3 B5 1A4 B6 1A5 C5 1A6 C6 1A7 D5 1A8 D6 1DIRA3 1OEA4 1B1A2 1B2A1 1B3B2 1B4B1 1B5C2 1B6C1 1B7D2 1B8D1 MN3D SN74ALVC125 MN3D SN74ALVC125 11 12

6242E–ATARM–11-Sep09 AT91SAM9261S

21.7.6.2 Software Configuration

The following configuration has to be performed:  Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space.  The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line A22 for REG function.  A23, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.  Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively.  Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency.

6242E–ATARM–11-Sep09 AT91SAM9261S

21.7.7 Compact Flash True IDE

21.7.7.1 Hardware Configuration

CF_D3 CF_D2 CF_D1 CF_D0 CF_D7 CF_D6 CF_D5 CF_D4 CF_D11 CF_D10 CF_D9 CF_D8 CF_D15 CF_D14 CF_D13 CF_D12 RESET# CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 CF_A2 CF_A1 CF_A0 CD2 CD1 IOWR IORD CE2 CE1 REG WE OE IOWR IORD IORDY CF_A0 CF_A2 CF_A1 CF_D4 CF_D13 CF_D15 CF_D14 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 CF_D6 CF_D5 CF_D3 CF_D2 CF_D1 CF_D0 CE2 CE1 RESET# INTRQ IORDY INTRQ CFWE (ANY PIO) A25/CFRNW D[0..15] A[0..10] CFCSx A22/REG CFOE CFIOW CFIOR NWAIT (ANY PIO) CFCE2 CFCE1 (ANY PIO) 3V3 3V3 3V3 3V3 3V3 3V3 3V3 CFIRQ CFRST TRUE IDE MODE (CFCS0 or CFCS1) 100NF 100NF MN1D 74ALVCH32245 MN1D 74ALVCH32245 4DIRT3 4OET4 4A1N5 4A2N6 4A3P5 4A4P6 4A5R5 4A6R6 4A7T6 4A8T5 4B1 N2 4B2 N1 4B3 P2 4B4 P1 4B5 R2 4B6 R1 4B7 T1 4B8 T2 VCC GND MN4 SN74LVC1G125-Q1 VCC GND MN4 SN74LVC1G125-Q1 5 1 MN3C SN74ALVC125 MN3C SN74ALVC125 10K 10K MN1C 74ALVCH32245 MN1C 74ALVCH32245 3DIRJ3 3OEJ4 3A1J5 3A2J6 3A3K5 3A4K6 3A5L5 3A6L6 3A7M5 3A8M6 3B1 J2 3B2 J1 3B3 K2 3B4 K1 3B5 L2 3B6 L1 3B7 M2 3B8 M1 10K 10K N7E50-7516VY-20 N7E50-7516VY-20 GND 1 D32 D43 D54 D65 D76 CS0#7 A108 ATA SEL#9 A910 A811 A712 VCC 13 A614 A515 A416 A317 A218 A119 A020 D021 D122 D223 IOIS16#24 CD2#25 CD1#26 D1127 D1228 D1329 D1430 D1531 CS1#32 VS1# 33 IORD#34 IOWR#35 WE#36 INTRQ 37 VCC 38 CSEL# 39 VS2# 40 RESET#41 IORDY42 INPACK# 43 REG#44 DASP# 45 PDIAG# 46 D847 D948 D1049 GND 50 MN1A 74ALVCH32245 MN1A 74ALVCH32245 1A1 A5 1A2 A6 1A3 B5 1A4 B6 1A5 C5 1A6 C6 1A7 D5 1A8 D6 1DIRA3 1OEA4 1B1A2 1B2A1 1B3B2 1B4B1 1B5C2 1B6C1 1B7D2 1B8D1 MN1B 74ALVCH32245 MN1B 74ALVCH32245 2DIRH3 2OEH4 2A1 E5 2A2 E6 2A3 F5 2A4 F6 2A5 G5 2A6 G6 2A7 H5 2A8 H6 2B1E2 2B2E1 2B3F2 2B4F1 2B5G2 2B6G1 2B7H2 2B8H1 MN2A SN74ALVC32 MN2A SN74ALVC32 100NF 100NF 47K 47K 47K 47K MN3B SN74ALVC125 MN3B SN74ALVC125 MN3D SN74ALVC125 MN3D SN74ALVC125 11 12 MN2B SN74ALVC32 MN2B SN74ALVC32 MN3A SN74ALVC125 MN3A SN74ALVC125

6242E–ATARM–11-Sep09 AT91SAM9261S

21.7.7.2 Software Configuration

The following configuration has to be performed:  Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space.  The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes.  CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.  Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively.  Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency.

6242E–ATARM–11-Sep09 AT91SAM9261S 22. Static Memory Controller (SMC)

22.1 Overview

The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user- programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes.

22.2 I/O Lines Description

22.3 Multiplexed Signals

Table 22-1. I/O Line Description Name Description Type Active Level NCS[7:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A1/NWR2/NBS2 Address Bit 1/Write 2/Byte 2 Select Signal Output Low NWR3/NBS3 Write 3/Byte 3 Select Signal Output Low A[25:2] Address Bus Output D[31:0] Data Bus I/O NWAIT External Wait Signal Input Low Table 22-2. Static Memory Controller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 163 A0 NBS0 8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 163 NWR1 NBS1 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 163 A1 NWR2 NBS2 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page 163. Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 163 NWR3 NBS3 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 163

6242E–ATARM–11-Sep09 AT91SAM9261S

22.4 Application Example

22.4.1 Hardware Interface

Figure 22-1. SMC Connections to Static Memory Devices

22.5 Product Dependencies

22.5.1 I/O Lines

The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. Static Memory Controller D0-D31 A2 - A25 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 128K x 8 SRAM D0 - D7 A0 - A16 OE WE CS D0 - D7 D8-D15 A2 - A18 128K x 8 SRAM D0-D7 CS D16 - D23 D24-D31 128K x 8 SRAM D0-D7 CS NWR1/NBS1 NWR3/NBS3 NRD NWR0/NWE 128K x 8 SRAM D0 - D7 OE WE CS NRD A1/NWR2/NBS2 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A18A0 - A16 NRD OE WE OE WE NRD A2 - A18 A0 - A16 A2 - A18A0 - A16

6242E–ATARM–11-Sep09 AT91SAM9261S

22.6 External Memory Mapping

The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device co nnected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 22-2). A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory. Figure 22-2. Memory Connections for Eight External Devices

22.7 Connection to External Devices

22.7.1 Data Bus Width

A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is con- trolled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select. Figure 22-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 22-4 shows how to connect a 512K x 16-bit memory on NCS2. Figure 22-5 shows two 16-bit memories connected as a single 32-bit memory

22.7.2 Byte Write or Byte Select Access

Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access . This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. NRD NWE A[25:0] D[31:0] 8 or 16 or 32 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] D[31:0] or D[15:0] or D[7:0] NCS3 NCS0 NCS1 NCS2 NCS7 NCS4 NCS5 NCS6 NCS[0] - NCS[7] SMC

6242E–ATARM–11-Sep09 AT91SAM9261S

22.7.2.1 Byte Write Access

Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode.  For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.  For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided. Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory. Byte Write option is illustrated on Figure 22-6.

22.7.2.2 Byte Select Access

In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write.  For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device.  For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices. Figure 22-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access mode, on NCS3 (BAT = Byte Select Access).

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option

22.7.2.3 Signal Multiplexing

Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 22-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. SMC A1 NWR0 NRD NCS[3] Write Enable Read Enable Memory Enable NWR1 Write Enable Read Enable Memory Enable D[7:0] D[7:0] D[15:8] D[15:8] A[24:2] A[23:1] A[23:1] A[0] A[0]

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) SMC NWE NRD NCS[3] Write Enable Read Enable Memory Enable NBS0 D[15:0] D[15:0] D[31:16] A[25:2] A[23:0] Write Enable Read Enable Memory Enable D[31:16] A[23:0] Low Byte Enable High Byte Enable Low Byte Enable High Byte EnableNBS1 NBS2 NBS3 Table 22-3. SMC Multiplexed Signal Translation Signal Name 32-bit Bus 16-bit Bus 8-bit Bus Device Type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit Byte Access Type (BAT) Byte Select Byte Select Byte Write Byte Select Byte Write NBS0_A0 NBS0 NBS0 NBS0 A0 NWE_NWR0 NWE NWE NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NBS1 NWR1 NBS1 NWR1 NBS2_NWR2_A1 NBS2 NBS2 NWR2 A1 A1 A1 NBS3_NWR3 NBS3 NBS3 NWR3

6242E–ATARM–11-Sep09 AT91SAM9261S

22.8 Standard Read and Write Protocols

In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE sig- nal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same ti mings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines.

22.8.1 Read Waveforms

The read cycle is shown on Figure 22-8. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 22-8. Standard Read Cycle

22.8.1.1 NRD Waveform

The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRD_SETUP NRD_PULSE NRD_HOLD MCK NRD D[31:0] NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE

6242E–ATARM–11-Sep09 AT91SAM9261S

22.8.1.2 NCS Waveform

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.

22.8.1.3 Read Cycle

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

22.8.1.4 Null Delay Setup and Hold

If null setup and hold parame ters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 22-9).

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-9. No Setup, No Hold On NRD and NCS Read Signals

22.8.1.5 Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.

22.8.2 Read Mode

As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD tim- ings to know which signal rises first. The R EAD_MODE parameter in the SMC_MODE register of the corresponding chip select indicates wh ich signal of NRD and NCS controls the read operation.

22.8.2.1 Read is Controlled by NRD (READ_MODE = 1):

Figure 22-10 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. MCK NRD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRD D[31:0]

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD

22.8.2.2 Read is Controlled by NCS (READ_MODE = 0)

Figure 22-11 shows the typical read cycle of an LCD module. The read data is valid t PACC after the falling edge of the NCS signal and remains va lid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be. Figure 22-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS Data Sampling tPACC MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRDD[31:0] Data Sampling tPACC MCK D[31:0] A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRD

6242E–ATARM–11-Sep09 AT91SAM9261S

22.8.3 Write Waveforms

The write protocol is similar to the read protocol. It is depicted in Figure 22-12. The write cycle starts with the address setting on the memory address bus.

22.8.3.1 NWE Waveforms

The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.

22.8.3.2 NCS Waveforms

The NCS signal waveforms in write operation are not the same that those applied in read opera- tions, but are separately defined: 1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 22-12. Write Cycle A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NCS NWE_SETUP NWE_PULSE NWE_HOLD MCK NWE NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE

6242E–ATARM–11-Sep09 AT91SAM9261S

22.8.3.3 Write Cycle

The write_cycle time is defined as the total durat ion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer num- ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total wr ite cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

22.8.3.4 Null Delay Setup and Hold

If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 22-13). How- ever, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 22-13. Null Setup and Hold Values of NCS and NWE in Write Cycle

22.8.3.5 Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. NCS MCK NWE, NWR0, NWR1, NWR2, NWR3 D[31:0] NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1

6242E–ATARM–11-Sep09 AT91SAM9261S

22.8.4 Write Mode

The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi- cates which signal controls the write operation.

22.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):

Figure 22-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 22-14. WRITE_MODE = 1. The write operation is controlled by NWE

22.8.4.2 Write is Controlle d by NCS (WRITE_MODE = 0)

Figure 22-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. MCK D[31:0] NCS A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-15. WRITE_MODE = 0. The write operation is controlled by NCS

22.8.5 Coding Timing Parameters

All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type. The SMC_SETUP register groups the definition of all setup parameters:  NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP The SMC_PULSE register groups the definition of all pulse parameters:  NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters:  NRD_CYCLE, NWE_CYCLE Table 22-4 shows how the timing parameters are coded and their permitted range. MCK D[31:0] NCS NWE, NWR0, NWR1, NWR2, NWR3 A [25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 Table 22-4. Coding and Range of Timing Parameters Coded Value Number of Bits Effective Value Permitted Range Coded Value Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ ≤ 31 0 ≤ ≤ 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ ≤ 63 0 ≤ ≤ 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ ≤ 127 0 ≤ ≤ 256+127 0 ≤ ≤ 512+127 0 ≤ ≤ 768+127

6242E–ATARM–11-Sep09 AT91SAM9261S

22.8.6 Reset Values of Timing Parameters

Table 22-5 gives the default value of timing parameters at reset.

22.8.7 Usage Restriction

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre- dictable behavior of the SMC. For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to pro- gram non-null values so as to cover possible skews between address, NCS and NRD signals. For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 177. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD sig- nals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus.

22.9 Automatic Wait States

Under certain circumstances, the SMC automatica lly inserts idle cycles between accesses to avoid bus contention or operation conflict.

22.9.1 Chip Select Wait States

The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control li nes are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 22-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. Table 22-5. Reset Values of Timing Parameters Register Reset Value SMC_SETUP 0 All setup timings are set to 1 SMC_PULSE 0x01010101 All pulse timings are set to 1 SMC_CYCLE 0x00010001 The read and write operation last 3 Master Clock cycles and provide one hold cycle WRITE_MODE 1 Write is controlled with NWE READ_MODE 1 Read is controlled with NRD

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2

22.9.2 Early Read Wait State

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid:  if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 22-17).  in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 22-18). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.  in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 22-19. A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS0 NRD_CYCLE Chip Select Wait State NWE_CYCLE MCK NCS2 NRD NWE D[31:0] Read to Write Wait State

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle

22.9.3 Reload User Configuration Wait State

The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select.

22.9.3.1 User Procedure

To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters. The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching the code from a memory connected on this CS, may lead A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 write cycle (WRITE_MODE = 1) Early Read wait state MCK NRD internal write controlling signal external write controlling signal (NWE) D[31:0] read cycle (READ_MODE = 0 or READ_MODE = 1) no hold read setup = 1

6242E–ATARM–11-Sep09 AT91SAM9261S to unpredictable behavior. The instructions used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another CS.

22.9.3.2 Slow Clock Mode Transition

A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 191).

22.9.4 Read to Write Wait State

Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in add ition to chip select and reload user configuration wait states when they are to be inserted. See Figure 22-16 on page 177.

6242E–ATARM–11-Sep09 AT91SAM9261S

22.10 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:  before starting a read access to a different external memory  before starting a write access to the same device or to a different external one. The Data Float Output Time (t DF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t DF will not slow down the executio n of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE register for the corresponding chip select.

22.10.1 READ_MODE

Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turn- ing off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 22-20 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 22-21 shows the read oper- ation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3.

6242E–ATARM–11-Sep09 AT91SAM9261S

22.10.2 TDF Optimization Enabled (TDF_MODE = 1)

When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 22-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). Figure 22-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins

22.10.3 TDF Optimization Disabled (TDF_MODE = 0)

When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. Figure 22-23, Figure 22-24 and Figure 22-25 illustrate the cases:  read access followed by a read access on another chip select,  read access followed by a write access on another chip select,  read access followed by a write access on the same chip select, with no TDF optimization. A[25:2] NCS0 MCK NRD NWE D[31:0] Read to Write Wait State TDF_CYCLES = 6 read access on NCS0 (NRD controlled) NRD_HOLD= 4 NWE_SETUP= 3 write access on NCS0 (NWE controlled)

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects Figure 22-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects TDF_CYCLES = 6 TDF_CYCLES = 6 TDF_MODE = 0 (optimization disabled) A[25:2] read1 cycle Chip Select Wait State MCK read1 controlling signal (NRD) read2 controlling signal (NRD) D[31:0] read1 hold = 1 read 2 cycle read2 setup = 1

5 TDF WAIT STATES

NBS0, NBS1, NBS2, NBS3, A0, A1 TDF_CYCLES = 4 TDF_CYCLES = 4 TDF_MODE = 0 (optimization disabled) A[25:2] read1 cycle Chip Select Wait State Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 hold = 1 write2 cycle write2 setup = 1

2 TDF WAIT STATES

NBS0, NBS1, NBS2, NBS3, A0, A1

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select

22.11 External Wait

Any access can be extended by an external device using the NW AIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the correspo nding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select.

22.11.1 Restriction

When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode (“Asynchronous Page Mode” on page 194), or in Slow Clock Mode (“Slow Clock Mode” on page 191). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. TDF_CYCLES = 5 TDF_CYCLES = 5 TDF_MODE = 0 (optimization disabled) A[25:2] read1 cycle Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 hold = 1 write2 cycle write2 setup = 1

4 TDF WAIT STATES

NBS0, NBS1, NBS2, NBS3, A0, A1

6242E–ATARM–11-Sep09 AT91SAM9261S

22.11.2 Frozen Mode

When the external device asserts the NWAIT signal (active low), and after internal synchroniza- tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 22- 26. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 22-27. Figure 22-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[25:2] MCK NWE NCS 43 2 1 1 10 1 4563 2 2 2 2 1 0 Write cycle D[31:0] NWAIT FROZEN STATE NBS0, NBS1, NBS2, NBS3, A0,A1 internally synchronized NWAIT signal

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 A[25:2] MCK NCS NRD 55 5 22 0 21 0 21 0 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal FROZEN STATE NBS0, NBS1, NBS2, NBS3, A0,A1

6242E–ATARM–11-Sep09 AT91SAM9261S

22.11.3 Ready Mode

In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 22-28 and Figure 22-29 . After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external de vice uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Fig- ure 22-29. Figure 22-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[25:2] MCK NWE NCS 43 2 1 0 0 0 4563 2 1 1 1 0 Write cycle D[31:0] NWAIT internally synchronized NWAIT signal Wait STATE NBS0, NBS1, NBS2, NBS3, A0,A1

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 7 NCS_RD_PULSE =7 A[25:2] MCK NCS NRD 4563 2 0 0 4563 2 1 1 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal Wait STATE Assertion is ignored NBS0, NBS1, NBS2, NBS3, A0,A1

6242E–ATARM–11-Sep09 AT91SAM9261S

22.11.4 NWAIT Latency and Read/Write Timings

There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. T he programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Fig- ure 22-30. When EXNW_MODE is enabled (ready or frozen), th e user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 22-30. NWAIT Latency EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 A[25:2] MCK NRD 43 21 0 0 0 Read cycle minimal pulse length NWAIT latency NWAIT intenally synchronized NWAIT signal WAIT STATE 2 cycle resynchronization NBS0, NBS1, NBS2, NBS3, A0,A1

6242E–ATARM–11-Sep09 AT91SAM9261S

22.12 Slow Clock Mode

The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.

22.12.1 Slow Clock Mode Waveforms

Figure 22-31 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 22-6 indicates the value of read and write parameters in slow clock mode. Figure 22-31. Read/write Cycles in Slow Clock Mode A[25:2] NCS MCK NWE 1 NWE_CYCLE = 3 A[25:2] MCK NRD NRD_CYCLE = 2 NCS SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ NBS0, NBS1, NBS2, NBS3, A0,A1 NBS0, NBS1, NBS2, NBS3, A0,A1 Table 22-6. Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3

6242E–ATARM–11-Sep09 AT91SAM9261S

22.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode

When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 22-32 on page 192. The external device may not be fast enough to support such timings. Figure 22-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 22-32. Clock Rate Transition Occurs while the SMC is Performing a Write Operation A[25:2] NCS MCK NWE NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 11 1 2 3 2 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State This write cycle finishes with the slow clock mode set of parameters after the clock rate transition SLOW CLOCK MODE WRITE NBS0, NBS1, NBS2, NBS3, A0,A1

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode A[25:2] NCS MCK NWE SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 2 3 2 NORMAL MODE WRITEIDLE STATE Reload Configuration Wait State NBS0, NBS1, NBS2, NBS3, A0,A1

6242E–ATARM–11-Sep09 AT91SAM9261S

22.13 Asynchronous Page Mode

The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN fiel d). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 22-7. With page mode memory devices, the first access to one page (t pa) takes longer than the subse- quent accesses to the page (t sa) as shown in Figure 22-34 . When in page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Notes: 1. A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.

22.13.1 Protocol and Timings in Page Mode

Figure 22-34 shows the NRD and NCS timings in page mode access. Figure 22-34. Page Mode Read Protocol (Address MSB and LSB are defined in Table 22-7) The NRD and NCS signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the Us er Interface may be. Moreover, the NRD and NCS Table 22-7. Page Address and Data Address within a Page Page Size Page Address (1) Data Address in the Page(2) 4 bytes A[25:2] A[1:0] 8 bytes A[25:3] A[2:0] 16 bytes A[25:4] A[3:0] 32 bytes A[25:5] A[4:0] A[MSB] NCS MCK NRD D[31:0] NCS_RD_PULSE NRD_PULSENRD_PULSE tsatpa tsa A[LSB]

6242E–ATARM–11-Sep09 AT91SAM9261S timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page mode, the programming of the read timings is described in Table 22-8: The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (t pa) and the NRD_PULSE for accesses to the page (t sa), even if the programmed value for tpa is shorter than the programmed value for tsa.

22.13.2 Byte Access Type in Page Mode

The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that require byte selection signals, configure the BAT field of the SMC_REGISTER to 0 (byte select access type).

22.13.3 Page Mode Restriction

The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior.

22.13.4 Sequential and Non-sequential Accesses

If the chip select and the MSB of addresses as defined in Table 22-7 are identical, then the cur- rent access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa). Figure 22-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 c auses a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequen- tial accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. Table 22-8. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE t pa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE t sa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 22-35. Access to Non-sequential Data within the Same Page A[25:3] A[2], A1, A0 NCS MCK NRD Page address A1 A3 A7 D[7:0] NCS_RD_PULSE NRD_PULSENRD_PULSE D1 D3 D7

6242E–ATARM–11-Sep09 AT91SAM9261S

22.14 Static Memory Contro ller (SMC) User Interface

The SMC is programmed using the registers listed in Table 22-9. For each chip select, a set of 4 registers is used to pro- gram the parameters of the exter nal device connected on it. In Table 22-9, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 22-9. Register Mapping Offset Register Name Access Reset 0x10 x CS_number + 0x00 SMC Setup Register SMC_SETUP Read-write 0 0x10 x CS_number + 0x04 SMC Pulse Register SMC_PULSE Read-write 0x01010101 0x10 x CS_number + 0x08 SMC Cycle Register SMC_CYCLE Read-write 0x00010001 0x10 x CS_number + 0x0C SMC Mode Register SMC_MODE Read-write 0x10001000 0xEC-0xFC Reserved - - -

6242E–ATARM–11-Sep09 AT91SAM9261S

22.14.1 SMC Setup Register

Register Name:SMC_SETUP[0..7] Addresses: 0xFFFFEC00 [0], 0xFFFFEC10 [1], 0xFFFFEC20 [2], 0x FFFFEC30 [3], 0xFFFFEC40 [4], 0xFFFFEC50 [5], 0xFFFFEC60 [6], 0xFFFFEC70 [7] Access Type:Read-write  NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles  NCS_WR_SETUP: NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles  NRD_SETUP: NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles  NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 31 30 29 28 27 26 25 24 – – NCS_RD_SETUP 23 22 21 20 19 18 17 16 – – NRD_SETUP 15 14 13 12 11 10 9 8 – – NCS_WR_SETUP 76543210 – – NWE_SETUP

6242E–ATARM–11-Sep09 AT91SAM9261S

22.14.2 SMC Pulse Register

Register Name:SMC_PULSE[0..7] Addresses: 0xFFFFEC04 [0], 0xFFFFEC14 [1], 0xFFFFEC24 [2], 0x FFFFEC34 [3], 0xFFFFEC44 [4], 0xFFFFEC54 [5], 0xFFFFEC64 [6], 0xFFFFEC74 [7] Access Type:Read-write  NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle.  NCS_WR_PULSE: NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle.  NRD_PULSE: NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles The NRD pulse length must be at least 1 clock cycle. In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.  NCS_RD_PULSE: NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 – NCS_RD_PULSE 23 22 21 20 19 18 17 16 – NRD_PULSE 15 14 13 12 11 10 9 8 – NCS_WR_PULSE 76543210 –N W E _ P U L S E

6242E–ATARM–11-Sep09 AT91SAM9261S

22.14.3 SMC Cycle Register

Register Name:SMC_CYCLE[0..7] Addresses: 0xFFFFEC08 [0], 0xFFFFEC18 [1], 0xFFFFEC28 [2], 0x FFFFEC38 [3], 0xFFFFEC48 [4], 0xFFFFEC58 [5], 0xFFFFEC68 [6], 0xFFFFEC78 [7] Access Type:Read-write  NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total du ration in clock cycles of the write cycle. It is equal to the sum of the setup, pul se and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles  NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 76543210 NWE_CYCLE

6242E–ATARM–11-Sep09 AT91SAM9261S

22.14.4 SMC MODE Register

Register Name:SMC_MODE[0..7] Addresses: 0xFFFFEC0C [0], 0xFFFFEC1C [1], 0xFFFFEC2C [2], 0xFFFFEC3C [3], 0xFFFFEC4C [4], 0xFFFFEC5C [5], 0xFFFFEC6C [6], 0xFFFFEC7C [7] Access Type:Read-write  READ_MODE: 1: The read operation is controlled by the NRD signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD. 0: The read operation is controlled by the NCS signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS. W R I T E _ M O D E 1: The write operation is controlled by the NWE signal. – If TDF optimization is enabled (TDF_MODE =1), TDF wa it states will be inserted after the setup of NWE. 0: The write operation is controlled by the NCS signal. – If TDF optimization is enabled (TDF_MODE =1), TDF wa it states will be inserted after the setup of NCS.  EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or writ e signal. It is only taken into account during the pulse phase of the read and writ e controlling signal. When the use of NWAIT is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal.  Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.  Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – TDF_MODE TDF_CYCLES 15 14 13 12 11 10 9 8 76543210 – – EXNW_MODE – – WRITE_MODE READ_MODE EXNW_MODE NWAIT Mode

00 D i s a b l e d

01 R e s e r v e d

6242E–ATARM–11-Sep09 AT91SAM9261S  Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.  BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus.  1: Byte write access type: – Write operation is controlled us ing NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.  0: Byte select access type: – Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3 – Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3  DBW: Data Bus Width  TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.  TDF_MODE: TDF Optimization 1: TDF optimization is enabled. – The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization is disabled. – The number of TDF wait states is inserted before the next access begins.  PMEN: Page Mode Enabled 1: Asynchronous burst read in page mode is applied on the corresponding chip select. 0: Standard read is applied.  PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes. DBW Data Bus Width 00 8 - b i t b u s 01 1 6 - b i t b u s 10 3 2 - b i t b u s

11 R e s e r v e d

6242E–ATARM–11-Sep09 AT91SAM9261S 23. SDRAM Controller (SDRAMC)

23.1 Overview

The SDRAM Controller (SDRAMC) extends the memory capabilities of a ch ip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the frequency. The different modes available - self-refresh, power-down and deep power-down modes - mini- mize power consumption on the SDRAM device.

23.2 I/O Lines Description

Table 23-1. I/O Line Description Name Description Type Active Level SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BA[1:0] Bank Select Signals Output RAS Row Signal Output Low CAS Column Signal Output Low SDWE SDRAM Write Enable Output Low NBS[3:0] Data Mask Enable Signals Output Low SDRAMC_A[12:0] Address Bus Output D[31:0] Data Bus I/O

6242E–ATARM–11-Sep09 AT91SAM9261S

23.3 Application Example

23.3.1 Software Interface

The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configura- tion register. The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user. Table 23-2 to Table 23-7 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated. 23.3.1.1 32-bit Memory Data Bus Width Notes: 1. M[1:0] is the byte address inside a 32-bit word. 3. Bk[1] = BA1, Bk[0] = BA0. Table 23-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[7:0] M[1:0] Bk[1:0] Row[10:0] Column[8:0] M[1:0] Bk[1:0] Row[10:0] Column[9:0] M[1:0] Bk[1:0] Row[10:0] Column[10:0] M[1:0] Table 23-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M[1:0] Bk[1:0] Row[11:0] Column[8:0] M[1:0] Bk[1:0] Row[11:0] Column[9:0] M[1:0] Bk[1:0] Row[11:0] Column[10:0] M[1:0] Table 23-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[7:0] M[1:0] Bk[1:0] Row[12:0] Column[8:0] M[1:0] Bk[1:0] Row[12:0] Column[9:0] M[1:0] Bk[1:0] Row[12:0] Column[10:0] M[1:0]

6242E–ATARM–11-Sep09 AT91SAM9261S 23.3.1.2 16-bit Memory Data Bus Width Notes: 1. M0 is the byte address inside a 16-bit half-word. 4. Bk[1] = BA1, Bk[0] = BA0.

23.4 Product Dependencies

23.4.1 SDRAM Device Initialization

The initialization sequence is generated by softw are. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register. 3. The SDRAM memory type must be set in the Memory Device Register. 4. A minimum pause of 200 µs is provided to precede any signal toggle. (1)A NOP command is issued to the SDRAM devices. The application must set Mode to 1 in the Mode Register and perform a write access to any SDRAM address. Table 23-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[7:0] M0 Bk[1:0] Row[10:0] Column[8:0] M0 Bk[1:0] Row[10:0] Column[9:0] M0 Bk[1:0] Row[10:0] Column[10:0] M0 Table 23-6. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M0 Bk[1:0] Row[11:0] Column[8:0] M0 Bk[1:0] Row[11:0] Column[9:0] M0 Bk[1:0] Row[11:0] Column[10:0] M0 Table 23-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[7:0] M0 Bk[1:0] Row[12:0] Column[8:0] M0 Bk[1:0] Row[12:0] Column[9:0] M0 Bk[1:0] Row[12:0] Column[10:0] M0

6242E–ATARM–11-Sep09 AT91SAM9261S 6. An All Banks Precharge command is issued to the SDRAM devices. The application must set Mode to 2 in the Mode Register and perform a write access to any SDRAM address. 7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Register and perform a write access to any SDRAM location eight times. 8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular CAS latency and burst length. The application must set Mode to 3 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. 9. For mobile SDRAM initialization, an Ex tended Mode Register set (EMRS) cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000 or 0x20400000. 10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write access at any location in the SDRAM. 11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562(15.652 µs x 100 MHz) or 781(7.81 µs x 100 MHz). After initialization, the SDRAM devices are fully functional. Note: 1. It is strongly recommended to respect the instructions stated in Step 5 of the initialization pro- cess in order to be certain that the subsequent commands issued by the SDRAMC will be taken into account.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 23-1. SDRAM Device Initialization Sequence

23.4.2 I/O Lines

The pins used for interfacing the SDRAM Contro ller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller.

23.4.3 Interrupt

The SDRAM Controller interrupt (Refresh Error notification) is connected to the Memory Control- ler. This interrupt may be ORed with other Syst em Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller). Using the SDRAM Controller interrupt requires the AIC to be programmed first.

23.5 Functional Description

23.5.1 SDRAM Controller Write Cycle

The SDRAM Controller allows burst access or single access. In both cases, the SDRAM control- ler keeps track of the active row in each bank, th us maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfe r type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is car- ried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command SDCKE tRP tRC tMRD

6242E–ATARM–11-Sep09 AT91SAM9261S parameters, additional clock cycles ar e inserted between precharge/active (t RP) commands and active/write (tRCD) commands. For definition of these timing parameters, refer to the “SDRAMC Configuration Register” on page 218. This is described in Figure 23-2 below. Figure 23-2. Write Burst, 32-bit SDRAM Access

23.5.2 SDRAM Controller Read Cycle

The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing param- eters, additional clock cycles on SDCK are inserted between precharge and active commands RP) and between active and read command (tRCD). These two parameters are set in the config- uration register of the SDRAM Controller. After a read command, additional wait states are generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration register). For a single access or an incremented burst of unspecified length, the SDRAM Controller antici- pates the next access. While the last value of t he column is returned by the SDRAM Controller on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han- dled as an incrementing burst of unspecified length. SDCK SDCS RAS CAS SDRAMC_A[12:0] D[31:0] tRCD = 3 Dna SDWE Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl Row n col a col b col c col d col e col f col g col h col i col j col k col l

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 23-3. Read Burst, 32-bit SDRAM Access

23.5.3 Border Management

When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and ini- tiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (t RP) command and the active/read (t RCD) com- mand. This is described in Figure 23-4 below. SDCK SDCS RAS CAS SDRAMC_A[12:0] D[31:0] (Input) tRCD = 3 Dna SDWE Dnb Dnc Dnd Dne Dnf Row n col a col b col c col d col e col f CAS = 2

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 23-4. Read Burst with Boundary Row Access

23.5.4 SDRAM Controller Refresh Cycles

An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener- ated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC _TR that indicates the number of clock cycles between refresh cycles. A refresh error interrupt is generated when the previous auto-refresh command did not perform. It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR). When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to ac cess the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. See Figure 23-5. SDCK SDCS RAS CAS SDRAMC_A[12:0] D[31:0] TRP = 3 SDWE Row mcol a col a col b col c col d col e Dna Dnb Dnc Dnd TRCD = 3 CAS = 2 col b col c col d Dma Dmb Dmc Dmd Row n Dme

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 23-5. Refresh Cycle Followed by a Read Access

23.5.5 Power Management

Three low-power modes are available:  Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM Controller. Current drained by the SDRAM is very low.  Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is higher than in Self-refresh Mode.  Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are lost, but the SDRAM does not drain any current. The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the Low Power Register.

23.5.5.1 Self-refresh Mode

This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode. Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM during initialization. SDCK SDCS RAS CAS SDRAMC_A[12:0] D[31:0] (input) tRP = 3 SDWE Dnb Dnc Dnd col c col d CAS = 2 Row m col a tRC = 8 tRCD = 3 Dma Row n

6242E–ATARM–11-Sep09 AT91SAM9261S The SDRAM device must remain in self-refresh mode for a minimum period of t RAS and may remain in self-refresh mode for an indefinite period. This is described in Figure 23-6. Figure 23-6. Self-refresh Mode Behavior

23.5.5.2 Low-power Mode

This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh operations are performed by the SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is faster than in self-refresh mode. This is described in Figure 23-7. SDCK SDCS RAS CAS SDRAMC_A[12:0] Self Refresh Mode SDWE Row TXSR = 3 SDCKE Write SDRAMC_SRR SRCB = 1 Access Request to the SDRAM Controller

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 23-7. Low-power Mode Behavior

23.5.5.3 Deep Power-down Mode

This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initializa- tion sequence is done (See “SDRAM Device Initialization” on page 205). This is described in Figure 23-8. SDCK SDCS RAS CAS SDRAMC_A[12:0] D[31:0] (input) TRCD = 3 Dna Dnb Dnc Dnd Dne Dnf Row n col a col b col c col d col e col f CAS = 2 SDCKE Low Power Mode

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 23-8. Deep Power-down Mode Behavior SDCK SDCS RAS CAS SDRAMC_A[12:0] D[31:0] (input) tRP = 3 SDWE Dnb Dnc Dnd col c col d Row n CKE

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6 SDRAM Controller ( SDRAMC) User Interface

Table 23-8. Register Mapping Offset Register Name Access Reset 0x00 SDRAMC Mode Register SDRAMC_MR Read-write 0x00000000 0x04 SDRAMC Refresh Timer Register SDRAMC_TR Read-write 0x00000000 0x08 SDRAMC Configuration Regist er SDRAMC_CR Read-write 0x852372C0 0x10 SDRAMC Low Power Register SDRAMC_LPR Read-write 0x0 0x14 SDRAMC Interrupt Enable Register SDRAMC_IER Write-only – 0x18 SDRAMC Interrupt Disable Register SDRAMC_IDR Write-only – 0x1C SDRAMC Interrupt Mask Register SDRAMC_IMR Read-only 0x0 0x20 SDRAMC Interrupt Status Register SDRAMC_ISR Read-only 0x0 0x24 SDRAMC Memory Device Register SDRAMC_MDR Read 0x0 0x28 - 0xFC Reserved – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.1 SDRAMC Mode Register

Register SDRAMC_MR Address: 0xFFFFEA00 Access Type:Read-write Reset Value: 0x00000000  MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 MODE Description 000 Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. 001 The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.

010 The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed

regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.

011 The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed

regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 100 The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a write to the SDRAM. 101 The SDRAM Controller issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low- power SDRAM devices use the bank 1. 1 1 0 Deep power-down mode. Enters deep power-down mode.

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.2 SDRAMC Refresh Timer Register

Register: SDRAMC_TR Address: 0xFFFFEA04 Access Type:Read-write Reset Value: 0x00000000  COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refr esh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of length one. To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– C O U N T 76543210 COUNT

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.3 SDRAMC Configuration Register

Register: SDRAMC_CR Address: 0xFFFFEA08 Access Type:Read-write Reset Value: 0x852372C0  NC: Number of Column Bits Reset value is 8 column bits.  NR: Number of Row Bits Reset value is 11 row bits.  NB: Number of Banks Reset value is two banks. 31 30 29 28 27 26 25 24 TXSR TRAS 23 22 21 20 19 18 17 16 TRCD TRP 15 14 13 12 11 10 9 8 TRC TWR 76543210 DBW CAS NB NR NC NC Column Bits 008 019 10 1 0 11 1 1 NR Row Bits 00 1 1 01 1 2 10 1 3

6242E–ATARM–11-Sep09 AT91SAM9261S  CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed.  DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits.  TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.  TRC: Row Cycle Delay Reset value is seven cycles. This field defines the delay between a Refresh and an Activate Command in numbe r of cycles. Number of cycles is between 0 and 15.  TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15.  TRCD: Row to Column Delay Reset value is two cycles. This field defines the delay between an Activate Comman d and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15.  TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15.  TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate Command in numb er of cycles. Number of cycles is between 0 and 15 CAS CAS Latency (Cycles)

00 R e s e r v e d

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.4 SDRAMC Low Power Register

Register: SDRAMC_LPR Address: 0xFFFFEA10 Access Type:Read-write Reset Value:0 x 0  LPCB: Low-power Configuration Bits  PASR: Partial Array Self-refresh (only for low-power SDRAM) PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set according to the SDRAM device specification.  TCSR: Temperature Compensated Self -Refresh (only for low-power SDRAM) TCSR parameter is transmitted to the SDRAM during initiali zation to set the refresh interval during self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification.  DS: Drive Strength (only for low-power SDRAM) DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame- ter must be set according to the SDRAM device specification. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– T I M E O U T D S T C S R 76543210 – PASR – – LPCB

00 Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to

the SDRAM device. The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. 11 The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.

6242E–ATARM–11-Sep09 AT91SAM9261S  TIMEOUT: Time to define when low-power mode is enabled 00 The SDRAM controller activates the SDRAM low-power mo de immediately after the end of the last transfer.

01 The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last

transfer.

10 The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last

transfer. 11 Reserved.

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.5 SDRAMC Interrupt Enable Register

Register: SDRAMC_IER Address: 0xFFFFEA14 Access Type:Write-only  RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt.

23.6.6 SDRAMC Interrupt Disable Register

Register: SDRAMC_IDR Address: 0xFFFFEA18 Access Type:Write-only  RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.7 SDRAMC Interrupt Mask Register

Register: SDRAMC_IMR Address: 0xFFFFEA1C Access Type:Read-only  RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled.

23.6.8 SDRAMC Interrupt Status Register

Register: SDRAMC_ISR Address: 0xFFFFEA20 Access Type:Read-only  RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

23.6.9 SDRAMC Memory Device Register

Register: SDRAMC_MDR Address: 0xFFFFEA24 Access Type:Read-write  MD: Memory Device Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

00 SDRAM

01 Low-power SDRAM

10 Reserved

11 Reserved.

6242E–ATARM–11-Sep09 AT91SAM9261S 24. Peripheral DMA Controller (PDC)

24.1 Overview

The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link betw een the PDC and a serial peripheral is operated by the AHB to ABP bridge. The PDC contains 19 channels. The full-duplex peripherals feat ure 18 mono directional chan- nels used in pairs (transmit only or receive only). The half-duplex peripherals feature 1 bi- directional channels. The user interface of each PDC channel is integrat ed into the user interface of the peripheral it serves. The user interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans- fer and one set (pointer, counter) for next transfer. The bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive. Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is gener- ated by the peripheral itself.

6242E–ATARM–11-Sep09 AT91SAM9261S

24.2 Block Diagram

Figure 24-1. Block Diagram

24.3 Functional Description

24.3.1 Configuration

The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated periph- eral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TN PR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each type are programmed differently: the PDCFULL DUPLEX PERIPHERAL THR RHR PDC Channel A PDC Channel B Control Status & Control Control PDC Channel C HALF DUPLEX PERIPHERAL THR Status & Control RECEIVE or TRANSMIT PERIPHERAL RHR or THR Control Control RHR PDC Channel D Status & Control

6242E–ATARM–11-Sep09 AT91SAM9261S transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number of transfers left for each channel. The PDC has dedicated status registers which indica te if the transfer is enabled or disabled for each channel. The status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control Register. At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 24.3.3 and to the associated peripheral user interface.

24.3.2 Memory Pointers

Each full duplex peripheral is connected to the PDC by a receive channel and a transmit chan- nel. Both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data depending on the operating mode of the peripheral. Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new address.

24.3.3 Transfer Counters

Each channel has two 16-bit counters, one for current transfer and the other one for next trans- fer. These counters define the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed by current memory pointer starts to be trans- ferred. When the cu rrent transfer counter re aches zero, the channel checks its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. At the end of this trans- fer the PDC channel sets the appropriate flags in the Peripheral Status Register. The following list gives an overview of how status register flags behave depending on the counters’ values:  ENDRX flag is set when the PERIPH_RCR register reaches zero.  RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.  ENDTX flag is set when the PERIPH_TCR register reaches zero.  TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the Peripheral Status Register.

6242E–ATARM–11-Sep09 AT91SAM9261S

24.3.4 Data Transfers

The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the periph- eral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding Register (RHR). The read data are stored in an internal buffer and then written to memory. When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit chan- nel which then requests access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to Transmit Holding Register (THR) of its asso- ciated peripheral. The same peripheral sends data according to its mechanism.

24.3.5 PDC Flags and Peripheral Status Register

Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status Register. Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels.

24.3.5.1 Receive Transfer End

This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.

24.3.5.2 Transmit Transfer End

This flag is set when PERIPH_TCR register reaches zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.

24.3.5.3 Receive Buffer Full

This flag is set when PERIPH_RCR register reac hes zero with PERIPH_RNCR also set to zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.

24.3.5.4 Transmit Buffer Empty

This flag is set when PERIPH_TCR register reac hes zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4 Peripheral DMA Controll er (PDC) User Interface

Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.) Table 24-1. Register Mapping Offset Register Name Access Reset 0x100 Receive Pointer Register PERIPH (1)_RPR Read-write 0 0x104 Receive Counter Register PERIPH_RCR Read-write 0 0x108 Transmit Pointer Register PERIPH_TPR Read-write 0 0x10C Transmit Counter Register PERIPH_TCR Read-write 0 0x110 Receive Next Pointer Register PERIPH_RNPR Read-write 0 0x114 Receive Next Counter Register PERIPH_RNCR Read-write 0 0x118 Transmit Next Pointer Register PERIPH_TNPR Read-write 0 0x11C Transmit Next Counter Register PERIPH_TNCR Read-write 0 0x120 Transfer Control Register PERIPH_PTCR Write-only 0 0x124 Transfer Status Register PERIPH_PTSR Read-only 0

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.1 Receive Pointer Register

Name: PERIPH_RPR Access Type:Read-write  RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 76543210 RXPTR

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.2 Receive Counter Register

Name: PERIPH_RCR Access Type:Read-write  RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the receiver 1 - 65535 = Starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 76543210 RXCTR

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.3 Transmit Pointer Register

Name: PERIPH_TPR Access Type:Read-write  TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.

24.4.4 Transmit Counter Register

Name: PERIPH_TCR Access Type:Read-write  TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the transmitter 1- 65535 = Starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 76543210 TXPTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 76543210 TXCTR

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.5 Receive Next Pointer Register

Name: PERIPH_RNPR Access Type:Read-write  RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.

24.4.6 Receive Next Counter Register

Name: PERIPH_RNCR Access Type:Read-write  RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 31 30 29 28 27 26 25 24 RXNPTR 23 22 21 20 19 18 17 16 RXNPTR 15 14 13 12 11 10 9 8 RXNPTR 76543210 RXNPTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXNCTR 76543210 RXNCTR

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.7 Transmit Next Pointer Register

Name: PERIPH_TNPR Access Type:Read-write  TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.

24.4.8 Transmit Next Counter Register

Name: PERIPH_TNCR Access Type:Read-write  TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 31 30 29 28 27 26 25 24 TXNPTR 23 22 21 20 19 18 17 16 TXNPTR 15 14 13 12 11 10 9 8 TXNPTR 76543210 TXNPTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXNCTR 76543210 TXNCTR

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.9 Transfer Control Register

Name: PERIPH_PTCR Access Type:Write-only  RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables PDC receiver channel requests if RXTDIS is not set. When a half duplex peripheral is connected to the PDC, en abling the receiver channel requests automatically disables the transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.  RXTDIS: Receiver Transfer Disable 0 = No effect. 1 = Disables the PDC receiver channel requests. When a half duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmit- ter channel requests.  TXTEN: Transmitter Transfer Enable 0 = No effect. 1 = Enables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, it en ables the transmitter channel requests only if RXTEN is not set. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.  TXTDIS: Transmitter Transfer Disable 0 = No effect. 1 = Disables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, dis abling the transmitter channel requests disables the receiver channel requests. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

24.4.10 Transfer Status Register

Name: PERIPH_PTSR Access Type:Read-only  RXTEN: Receiver Transfer Enable 0 = PDC Receiver channel requests are disabled. 1 = PDC Receiver channel requests are enabled.  TXTEN: Transmitter Transfer Enable 0 = PDC Transmitter channel requests are disabled. 1 = PDC Transmitter channel requests are enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S 25. Clock Generator (CKGR)

25.1 Overview

The Clock Generator is made up of 2 PLL, a Main Oscillator, and a 32,768 Hz low-power Oscillator. It provides the following clocks:  SLCK, the Slow Clock, which is the only permanent clock within the system  MAINCK is the output of the Main Oscillator The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 26.9. However, the Clock Generator registers are named CKGR_.  PLLACK is the output of the Divider and PLL A block  PLLBCK is the output of the Divider and PLL B block

25.2 Slow Clock Crystal Oscillator

The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in Figure 25-1. Figure 25-1. Typical Slow Clock Crystal Oscillator Connection 25.3 Main Oscillator Figure 25-2 shows the Main Oscillator block diagram. XIN32 XOUT32 GNDBU 32,768 Hz Crystal

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 25-2. Main Oscillator Block Diagram

25.3.1 Main Oscillator Connections

The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 25-3 . The 1 k Ω resistor is only required for crystals with frequencies lower than 8 MHz. For further details on the electrical char- acteristics of the Main Oscillator, see the section “DC Characteristics” of the product datasheet. Figure 25-3. Typical Crystal Connection

25.3.2 Main Oscillator Startup Time

The startup time of the Main Oscillator is giv en in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the fre- quency rises.

25.3.3 Main Oscillator Control

To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. The software enable s or disables the main oscillator so as to reduce po wer consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). XIN XOUT MOSCEN Main Oscillator Counter OSCOUNT MOSCS MAINCK Main Clock Main Clock Frequency Counter MAINF MAINRDY SLCK Slow Clock Main Oscillator XIN XOUT GND AT91 Microcontroller

6242E–ATARM–11-Sep09 AT91SAM9261S When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared, indicating the main clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillat or. This startup time depends on the crystal fre- quency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscil- lator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Set- ting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.

25.3.4 Main Clock Frequency Counter

The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is know n by the system designer; how- ever, it is useful for the boot program to c onfigure the device with the correct clock speed, independently of the application. The Main Clock frequency counter starts incrementing at the Main Clock speed after the next ris- ing edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined.

25.3.5 Main Oscillator Bypass

The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XI N pin. The input characteristics of the XIN pin under these conditions are given in the product el ectrical characteristics section. The program- mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.

25.4 Divider and PLL Block

The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How- ever, the user must respect the PLL minimum input frequency when programming the divider. Figure 25-4 shows the block diagram of the divider and PLL blocks.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 25-4. Divider and PLL Block Diagram

25.4.1 PLL Filter

The PLL requires connection to an external second-order filter through the PLLRCA and/or PLL- RCB pin. Figure 25-5 shows a schematic of these filters. Figure 25-5. PLL Capacitors and Resistors Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time.

25.4.2 Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL out put is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. Divider B PLLRCB DIVB PLL B MULB PLLRCA DIVA PLL A Counter PLLBCOUNT LOCKB PLL A Counter PLLACOUNT LOCKA MULA OUTB OUTA SLCK PLLACK PLLBCK Divider A PLL B MAINCK GND PLL PLLRC R

6242E–ATARM–11-Sep09 AT91SAM9261S The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLA- COUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. During the PLLA or PLLB initialization, the PMC_PLLICPR register must be programmed correctly.

6242E–ATARM–11-Sep09 AT91SAM9261S 26. Power Management Controller (PMC)

26.1 Overview

The Power Management Controller (PMC) optimizes power consumption by controlling all sys- tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks:  MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller.  Processor Clock (PCK), must be switched off when entering processor in Idle Mode.  Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet.  UDP Clock (UDPCK), required by USB Device Port operations.  Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins.

26.2 Master Clock Controller

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a cloc k selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writi ng the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. The Master Clock divider can be programmed through the MDIV field in PMC_MCKR. Each time PMC_MCKR is written to define a ne w Master Clock, the MCKR DY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 26-1. Master Clock Controller

26.3 Processor Clock Controller

The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is ac hieved by disabling the Processor Clock and entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. Note: The ARM Wait for Interrupt mode is entered with CP15 coprocessor operation. Refer to the Atmel application note, Optimizing Power Consumption for AT91SAM9261-based Systems, lit. number 6217. When the Processor Clock is disabled, the curr ent instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.

26.4 USB Clock Controller

The USB Source Clock is always generated from the PLL B output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see Figure 26-2). When the PLL B output is stable, i.e., the LOCKB is set:  The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock Controller. Figure 26-2. USB Clock Controller SLCK Master Clock Prescaler MCK PRESCSS Master Clock Divider MAINCK PLLACK PLLBCK MDIV To the Processor Clock Controller (PCK) PMC_MCKR PMC_MCKR PMC_MCKR USB Source Clock UDP Clock (UDPCK) UDP USBDIV Divider /1,/2,/4

6242E–ATARM–11-Sep09 AT91SAM9261S

26.5 Peripheral Clock Controller

The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Periph- eral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data cor- ruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.

26.6 Programmable Clock Output Controller

The PMC controls 4 signals to be output on ex ternal pins PCKx. Ea ch signal can be indepen- dently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B out- put and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bitin PMC_SR indicates that the Programmable Clock is actu- ally what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.

26.7 Programming Sequence

1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writ- ing a value in the OSCOUNT field in the CKGR_MOR register. Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. Code Example: write_register(CKGR_MOR,0x00000701) Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles. So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.

6242E–ATARM–11-Sep09 AT91SAM9261S 2. Checking the Main Oscilla tor Frequency (Optional): In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL A and divider A: All parameters necessary to configure PLL A and divider A are located in the CKGR_PLLAR register. ICPPLLA in PMC_PLLICPR register must be set to 1 before configuring the CKGR_PLLAR register. It is important to note that Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. The DIVA field is used to control the divider A itself. The user can program a value between 0 and 255. Divider A output is divider A input divided by DIVA. By default, DIVA parameter is set to 0 which means that divider A is turned off. The OUTA field is used to select the PLL A output frequency range. The MULA field is the PLL A multiplier factor. This parameter can be programmed between 0 and 2047. If MULA is set to 0, PLL A will be turned off. Otherwise PLL A output frequency is PLL A input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register after CKGR_PLLAR register has been written. Once CKGR_PLLAR register has been written, the user is obliged to wait for the LOCKA bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following par ameters, SRCA, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLL A is not ready yet. When PLL A is locked, LOCKA will be set again. User has to wait for LOCKA bit to be set before using the PLL A output clock. Code Example: write_register(CKGR_PLLAR,0x20030605) PLL A and divider A are enabled. PLL A input clock is main clock divided by 5. PLL An out- put clock is PLL A input clock multiplied by 4. Once CKGR_PLLAR has been written, LOCKA bit will be set after six slow clock cycles. 4. Setting PLL B and divider B: All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR register. ICPPLLB in PMC_PLLICPR register must be set to 1 before configuring the CKGR_PLLBR register. The DIVB field is used to control divider B itself. A value between 0 and 255 can be pro- grammed. Divider B output is divider B input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that divider B is turned off. The OUTB field is used to select the PLL B output frequency range.

6242E–ATARM–11-Sep09 AT91SAM9261S The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 2047. If MULB is set to 0, PLL B will be turned off, otherwis e the PLL B output fre- quency is PLL B input frequency multiplied by (MULB + 1). The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR register after CKGR_PLLBR register has been written. Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR register. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in the PMC_IER register. All parameters in CKGR_PLLBR can be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is modified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB will be set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock. The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s). Code Example: write_register(CKGR_PLLBR,0x00040805) If PLL B and divider B are enabled, the PLL B in put clock is the main clock. PLL B output clock is PLL B input clock multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit will be set after eight slow clock cycles. 5. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock. The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 0 which means that master clock is equal to slow clock. The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1, 2). The Master Clock outp ut is Processor Clock divided by 1, 2 or 4, depending on the value programmed in MDIV. By default, MDIV is set to 0, which indicates that the Processor Clock is equal to the Master Clock. Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR register must not be programmed in a single write operation. The pre- ferred programming sequence for the PMC_MCKR register is as follows:  If a new value for CSS field corresponds to PLL Clock, – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register.

6242E–ATARM–11-Sep09 AT91SAM9261S  If a new value for CSS field corresponds to Main Clock or Slow Clock, – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks. Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK (LOCKA or LOCKB) goes high and MCKRDY is set. While PLLA is unlocked, the Master Clock selection is automatically changed to Slow Clock. While PLLB is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see Section 26.8.2. “Clock Switching Waveforms” on page 250. Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 6. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 4 Programmable clocks can be enabled or dis- abled. The PMC_SCSR provides a clear indi cation as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure Programmable clocks. The CSS field is used to select the Program mable clock divider sour ce. Four clock options are available: main clock, slow clock, PL LACK, PLLBCK. By default, the clock source selected is slow clock. The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 0 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrai ned to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the

6242E–ATARM–11-Sep09 AT91SAM9261S PMC_IER register. All parameters in PMC_ PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set. Code Example: write_register(PMC_PCK0,0x00000015) Programmable clock 0 is main clock divided by 32. 7. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR. Depending on the system used, 17 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Each enabled peripheral clock corresponds to Master Clock. Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled.

6242E–ATARM–11-Sep09 AT91SAM9261S

26.8 Clock Switching Details

26.8.1 Master Clock Switching Timings

Table 26-1 and Table 26-2 give the worst case timings requ ired for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional ti me of 64 clock cycles of the new selected clock has to be added. Notes: 1. PLL designates either the PLL A or the PLL B Clock. 2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT. Table 26-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock To Main Clock – 4 x SLCK + 2.5 x Main Clock 3 x PLL Clock + 4 x SLCK + 1 x Main Clock SLCK 0.5 x Main Clock + 4.5 x SLCK – 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK Table 26-2. Clock Switching Timings Between Two PLLs (Worst Case) From PLLA Clock PLLB Clock To PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock PLLB Clock 3 x PLLB Clock + 4 x SLCK + 1.5 x PLLB Clock 2.5 x PLLB Clock + 4 x SLCK + PLLBCOUNT x SLCK

6242E–ATARM–11-Sep09 AT91SAM9261S

26.8.2 Clock Switching Waveforms

Figure 26-3. Switch Master Clock from Slow Clock to PLL Clock Figure 26-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock LOCK MCKRDY Master Clock Write PMC_MCKR PLL Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 26-7. Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PCKx is disabled PCKx is enabled PLL Clock is selected

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9 Power Management Contro ller (PMC) User Interface

Table 26-3. Register Mapping Offset Register Name Access Reset Value 0x0000 System Clock Enable Register PMC_SCER Write-only – 0x0004 System Clock Disable Register PMC_SCDR Write-only – 0x0008 System Clock Status Register PMC _SCSR Read-only 0x03 0x000C Reserved – – – 0x0010 Peripheral Clock Enable Register PMC _PCER Write-only – 0x0014 Peripheral Clock Disable Register PMC_PCDR Write-only – 0x0018 Peripheral Clock Status Register PMC_PCSR Read-only 0x0 0x001C Reserved – – – 0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0 0x0024 Main Clock Frequency Register CKGR_MCFR Read-only 0x0 0x0028 PLL A Register CKGR_PLLAR ReadWrite 0x3F00 0x002C PLL B Register CKGR_PLLBR ReadWrite 0x3F00 0x0030 Master Clock Register PMC_MCKR Read-write 0x0 0x0038 Reserved – – – 0x003C Reserved – – – 0x0040 Programmable Clock 0 Register PMC_PCK0 Read-write 0x0 0x0044 Programmable Clock 1 Register PMC_PCK1 Read-write 0x0 0x0060 Interrupt Enable Register PMC_IER Write-only -- 0x0064 Interrupt Disable Register PMC_IDR Write-only -- 0x0068 Status Register PMC_SR Read-only 0x08 0x006C Interrupt Mask Register PMC_IMR Read-only 0x0 0x0070 - 0x007C Reserved – – – 0x0080 Charge Pump Current Regi ster PMC_PLLICPR Write-only -- 0x0084 - 0x00FC Reserved – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.1 PMC System Clock Enable Register

Name: PMC_SCER Address: 0xFFFFFC00 Access Type:Write-only  UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port.  PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K 3 P C K 2 P C K 1 P C K 0 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.2 PMC System Clock Disable Register

Name: PMC_SCDR Address: 0xFFFFFC04 Access Type:Write-only  PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode.  UDP: USB Device Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port.  PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K 3 P C K 2 P C K 1 P C K 0 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.3 PMC System Clock Status Register

Name: PMC_SCSR Address: 0xFFFFFC08 Access Type:Read-only  PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled.  UDP: USB Device Port Clock Status 0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled.  PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K 3 P C K 2 P C K 1 P C K 0 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.4 PMC Peripheral Clock Enable Register

Name: PMC_PCER Address: 0xFFFFFC10 Access Type:Write-only  PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Note: Programming the control bits of the Peripheral ID that ar e not implemented has no effect on the behavior of the PMC. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 - -

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.5 PMC Peripheral Clock Disable Register

Name: PMC_PCDR Address: 0xFFFFFC14 Access Type:Write-only  PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 - -

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.6 PMC Peripheral Clock Status Register

Name: PMC_PCSR Address: 0xFFFFFC18 Access Type:Read-only  PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 – –

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.7 PMC Clock Generator Main Oscillator Register

Name: CKGR_MOR Address: 0xFFFFFC20 Access Type:Read-write  MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0. When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved.  OSCBYPASS: Oscillator Bypass 0 = No effect. 1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN. When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag.  OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 OSCOUNT 76543210 –––––– O S C B Y P A S S M O S C E N

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.8 PMC Clock Generator Main Clock Frequency Register

Name: CKGR_MCFR Address: 0xFFFFFC24 Access Type: Read-only  MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.  MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MAINF 76543210 MAINF

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.9 PMC Clock Generator PLL A Register

Name: CKGR_PLLAR Address: 0xFFFFFC28 Access Type:Read-write Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.  DIVA: Divider A  PLLACOUNT: PLL A Counter Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.  OUTA: PLL A Clock Frequency Range To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char- acteristics section of the product datasheet.  MULA: PLL A Multiplier 0 = The PLL A is deactivated. 1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1. 31 30 29 28 27 26 25 24 ––1–– M U L A 23 22 21 20 19 18 17 16 MULA 15 14 13 12 11 10 9 8 OUTA PLLACOUNT 76543210 DIVA DIVA Divider Selected

0 Divider output is 0

1 Divider is bypassed

2 - 255 Divider output is the Main Clock divided by DIVA.

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.10 PMC Clock Generator PLL B Register

Name: CKGR_PLLBR Address: 0xFFFFFC2C Access Type:Read-write Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.  DIVB: Divider B  PLLBCOUNT: PLL B Counter Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.  OUTB: PLLB Clock Frequency Range To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char- acteristics section of the product datasheet.  MULB: PLL Multiplier 0 = The PLL B is deactivated. 1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.  USBDIV: Divider for USB Clock 31 30 29 28 27 26 25 24 – – USBDIV – MULB 23 22 21 20 19 18 17 16 MULB 15 14 13 12 11 10 9 8 OUTB PLLBCOUNT 76543210 DIVB DIVB Divider Selected 2 - 255 Divider output is the selected clock divided by DIVB. USBDIV Divider for USB Clock(s) 0 0 Divider output is PLL B clock output. 0 1 Divider output is PLL B clock output divided by 2. 1 0 Divider output is PLL B clock output divided by 4. 1 1 Reserved.

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.11 PMC Master Clock Register

Name: PMC_MCKR Address: 0xFFFFFC30 Access Type:Read-write  CSS: Master Clock Selection  PRES: Processor Clock Prescaler  MDIV: Master Clock Division 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – PRES CSS CSS Clock Source Selection 0 0 Slow Clock is selected 0 1 Main Clock is selected 1 0 PLL A Clock is selected 1 1 PLL B Clock is selected PRES Processor Clock 0 0 0 Selected clock 0 0 1 Selected clock divided by 2 0 1 0 Selected clock divided by 4 0 1 1 Selected clock divided by 8 1 0 0 Selected clock divided by 16 1 0 1 Selected clock divided by 32 1 1 0 Selected clock divided by 64

111 R e s e r v e d

MDIV Master Clock Division 0 0 Master Clock is Processor Clock. 0 1 Master Clock is Processor Clock divided by 2. 1 0 Master Clock is Processor Clock divided by 4. 1 1 Reserved.

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.12 PMC Programmable Clock Register

Name: PMC_PCKx Address: 0xFFFFFC40 Access Type:Read-write  CSS: Master Clock Selection  PRES: Programmable Clock Prescaler 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – PRES CSS CSS Clock Source Selection 0 0 Slow Clock is selected 0 1 Main Clock is selected 1 0 PLL A Clock is selected 1 1 PLL B Clock is selected PRES Programmable Clock 0 0 0 Selected clock 0 0 1 Selected clock divided by 2 0 1 0 Selected clock divided by 4 0 1 1 Selected clock divided by 8 1 0 0 Selected clock divided by 16 1 0 1 Selected clock divided by 32 1 1 0 Selected clock divided by 64

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.13 PMC Interrupt Enable Register

Name: PMC_IER Address: 0xFFFFFC60 Access Type:Write-only  MOSCS: Main Oscillator Status Interrupt Enable  LOCKA: PLL A Lock Interrupt Enable  LOCKB: PLL B Lock Interrupt Enable  MCKRDY: Master Clock Ready Interrupt Enable  PCKRDYx: Programmable Clock Ready x Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K R D Y 3 P C K R D Y 2 P C K R D Y 1 P C K R D Y 0 76543210 –––– M C K R D Y L O C K B L O C K A M O S C S

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.14 PMC Interrupt Disable Register

Name: PMC_IDR Address: 0xFFFFFC64 Access Type:Write-only  MOSCS: Main Oscillator Status Interrupt Disable  LOCKA: PLL A Lock Interrupt Disable  LOCKB: PLL B Lock Interrupt Disable  MCKRDY: Master Clock Ready Interrupt Disable  PCKRDYx: Programmable Clock Ready x Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K R D Y 3 P C K R D Y 2 P C K R D Y 1 P C K R D Y 0 76543210 – ––– M C K R D Y LOCKB LOCKA MOSCS

6242E–ATARM–11-Sep09 AT91SAM9261S

26.9.15 PMC Status Register

Name: PMC_SR Address: 0xFFFFFC68 Access Type:Read-only  MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized.  LOCKA: PLL A Lock Status 0 = PLL A is not locked 1 = PLL A is locked.  LOCKB: PLL B Lock Status 0 = PLL B is not locked. 1 = PLL B is locked.  MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready.  PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K R D Y 3 P C K R D Y 2 P C K R D Y 1 P C K R D Y 0 76543210 –––– M C K R D Y LOCKB LOCKA MOSCS

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26.9.16 PMC Interrupt Mask Register

Name: PMC_IMR Address: 0xFFFFFC6C Access Type:Read-only  MOSCS: Main Oscillator Status Interrupt Mask  LOCKA: PLL A Lock Interrupt Mask  LOCKB: PLL B Lock Interrupt Mask  MCKRDY: Master Clock Ready Interrupt Mask  PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled. 1 = The corresponding interrupt is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– P C K R D Y 3 P C K R D Y 2 P C K R D Y 1 P C K R D Y 0 76543210 – ––– M C K R D Y LOCKB LOCKA MOSCS

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26.9.17 PLL Charge Pump Current Register

Name: PMC_PLLICPR Address: 0xFFFFFC80 Access Type:Write-only  ICPPLLA: Charge pump current Must be set to 1.  ICPPLLB: Charge pump current Must be set to 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S 27. Advanced Interrupt Controller (AIC)

27.1 Overview

The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to sub- stantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external inter- rupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt.

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27.2 Block Diagram

Figure 27-1. Block Diagram

27.3 Application Block Diagram

Figure 27-2. Description of the Application Block

27.4 AIC Detailed Block Diagram

Figure 27-3. AIC Detailed Block Diagram AIC APB ARM Processor FIQ IRQ0-IRQn Embedded PeripheralEE PeripheralEmbedded Peripheral Embedded Up to Thirty-two Sources nFIQ nIRQ Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts) Standalone Applications RTOS Drivers Hard Real Time Tasks OS-based Applications OS Drivers General OS Interrupt Handler FIQ PIO Controller Advanced Interrupt Controller IRQ0-IRQn PIOIRQ Embedded Peripherals External Source Input Stage Internal Source Input Stage Fast Forcing Interrupt Priority Controller Fast Interrupt Controller ARM Processor nFIQ nIRQ Power Management Controller Wake UpUser Interface APB Processor Clock

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27.5 I/O Line Description

27.6 Product Dependencies

27.6.1 I/O Lines

The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control- lers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path.

27.6.2 Power Management

The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interr upt line of the processor, thus providing syn- chronization of the processor on an event.

27.6.3 Interrupt Sources

The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt . This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines . The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. Table 27-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input

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27.7 Functional Description

27.7.1 Interrupt Source Control

27.7.1.1 Interrupt Source Mode

The Advanced Interrupt Controller independently programs each interrupt source. The SRC- TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sen- sitive modes, or in positive edge-triggered or negative edge-triggered modes.

27.7.1.2 Interrupt Source Enabling

Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruc- tion. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts.

27.7.1.3 Interrupt Clearing and Setting

All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the softwa re must perform an acti on to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. ( See “Priority Controller” on page 277.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See “Fast Forcing” on page 281.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.

27.7.1.4 Interrupt Status

For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (see “Priority Controller” on page 277) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems.

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27.7.1.5 Internal Interrupt Source Input Stage

Figure 27-4. Internal Interrupt Source Input Stage

27.7.1.6 External Interrupt Source Input Stage

Figure 27-5. External Interrupt Source Input Stage Edge Detector ClearSet Source i AIC_IPR AIC_IMR AIC_IECR AIC_IDCR AIC_ISCR AIC_ICCR Fast Interrupt Controller or Priority Controller FF Level/ Edge AIC_SMRI (SRCTYPE) Edge Detector ClearSet Pos./Neg. AIC_ISCR AIC_ICCR Source i FF Level/ Edge High/Low AIC_SMRi SRCTYPE AIC_IPR AIC_IMR AIC_IECR AIC_IDCR Fast Interrupt Controller or Priority Controller

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27.7.2 Interrupt Latencies

Global interrupt latencies depend on several parameters, including:  The time the software masks the interrupts.  Occurrence, either at the processor level or at the AIC level.  The execution time of the instruction in progress when the interrupt occurs.  The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resync hronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro- cessor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.

27.7.2.1 External Interrupt Edge Triggered Source

Figure 27-6. External Interrupt Edge Triggered Source

27.7.2.2 External Interrupt Level Sensitive Source

Figure 27-7. External Interrupt Level Sensitive Source Maximum FIQ Latency = 4 Cycles Maximum IRQ Latency = 4 Cycles nFIQ nIRQ MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) Maximum IRQ Latency = 3 Cycles Maximum FIQ Latency = 3 cycles MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ nFIQ

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27.7.2.3 Internal Interrupt Edge Triggered Source

Figure 27-8. Internal Interrupt Edge Triggered Source

27.7.2.4 Internal Interrupt Level Sensitive Source

Figure 27-9. Internal Interrupt Level Sensitive Source

27.7.3 Normal Interrupt

27.7.3.1 Priority Controller

An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writ- ing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have hap- pened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. MCK nIRQ Peripheral Interrupt Becomes Active Maximum IRQ Latency = 4.5 Cycles MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active

6242E–ATARM–11-Sep09 AT91SAM9261S The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling.

27.7.3.2 Interrupt Nesting

The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priori ty interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service rou- tine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels.

27.7.3.3 Interrupt Vectoring

The interrupt handler addresses corresponding to each interrupt source can be stored in the reg- isters AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the cur- rent interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus acces- sible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by support- ing the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical inte rrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral han- dling) to be handled efficiently and independently of the application running under an operating system.

27.7.3.4 Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits.

6242E–ATARM–11-Sep09 AT91SAM9261S It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_i rq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, dec- rementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: – Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. – De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. – Automatically clears the interrupt, if it has been programmed to be edge-triggered. – Pushes the current level and the current interrupt number on to the stack. – Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branc hing to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re- assertion of the nIRQ to be taken into account by the core. This can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can th en proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: If the interrupt is programmed to be level sensitiv e, the source of the interrupt must be cleared dur- ing this phase. 7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indi- cate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the inter- rupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.

6242E–ATARM–11-Sep09 AT91SAM9261S Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked).

27.7.4 Fast Interrupt

27.7.4.1 Fast Interrupt Source

The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt so urce 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller.

27.7.4.2 Fast Interrupt Control

The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The fi eld SRCTYPE of AIC_SMR0 enable s programming the fast inter- rupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.

27.7.4.3 Fast Interrupt Vectoring

The fast interrupt handler address can be stor ed in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Reg- ister). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast inter- rupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically per- forms the clear of the fast interrupt source if it is programmed in edge-triggered mode.

27.7.4.4 Fast Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: LDR PC, [PC, # -&F20] 3. The user does not need nested fast interrupts. When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In

6242E–ATARM–11-Sep09 AT91SAM9261S the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save regis- ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The “F” bit in SPSR is significan t. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction.

27.7.4.5 Fast Forcing

The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabl ed by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FF DR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC _FFSR) that controls the feature for each inter- nal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt s ource is still active but the source c annot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level- sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Reg- ister (AIC_IPR).

6242E–ATARM–11-Sep09 AT91SAM9261S The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 27-10. Fast Forcing

27.7.5 Protect Mode

The Protect Mode permits reading the Interrupt Vector Register without performing the associ- ated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's IC E, stops the applica- tions and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences:  If an enabled interrupt with a higher priority than the current one is pending, it is stacked.  If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. Source 0 _ FIQ Input Stage Automatic Clear Input Stage Automatic Clear Source n AIC_IPR AIC_IMR AIC_FFSR AIC_IPR AIC_IMR Priority Manager nFIQ nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. Read FVR if Fast Forcing is disabled on Sources 1 to 31.

6242E–ATARM–11-Sep09 AT91SAM9261S An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following opera- tions within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.

27.7.6 Spurious Interrupt

The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when:  An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.  An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.)  An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The pr ogrammer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt.

27.7.7 General Interrupt Mask

The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to thei r inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilit ates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.

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27.8 Advanced Interrupt Controll er (AIC) User Interface

27.8.1 Base Address

The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring fea- ture, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 3. Values in the Version Register vary with the version of the IP block implementation. Table 27-2. Register Mapping Offset Register Name Access Reset 0x00 Source Mode Register 0 AIC_SMR0 Read-write 0x0 0x04 Source Mode Register 1 AIC_SMR1 Read-write 0x0 0x7C Source Mode Register 31 AIC_SMR31 Read-write 0x0 0x80 Source Vector Register 0 AIC_SVR0 Read-write 0x0 0x84 Source Vector Register 1 AIC_SVR1 Read-write 0x0 0xFC Source Vector Register 31 AIC_SVR31 Read-write 0x0 0x100 Interrupt Vector Register AIC_IVR Read-only 0x0 0x104 FIQ Interrupt Vector Register AIC_FVR Read-only 0x0 0x108 Interrupt Status Register AIC_ISR Read-only 0x0 0x10C Interrupt Pending Register (2) AIC_IPR Read-only 0x0 (1) 0x110 Interrupt Mask Register (2) AIC_IMR Read-only 0x0 0x114 Core Interrupt Status Register AIC_CISR Read-only 0x0 0x118 - 0x11C Reserved --- --- --- 0x120 Interrupt Enable Command Register (2) AIC_IECR Write-only --- 0x124 Interrupt Disable Command Register (2) AIC_IDCR Write-only --- 0x128 Interrupt Clear Command Register (2) AIC_ICCR Write-only --- 0x12C Interrupt Set Command Register (2) AIC_ISCR Write-only --- 0x130 End of Interrupt Command Register AIC_EOICR Write-only --- 0x134 Spurious Interrupt Vector Register AIC_SPU Read-write 0x0 0x138 Debug Control Register AIC_DCR Read-write 0x0 0x13C Reserved --- --- --- 0x140 Fast Forcing Enable Register (2) AIC_FFER Write-only --- 0x144 Fast Forcing Disable Register (2) AIC_FFDR Write-only --- 0x148 Fast Forcing Status Register (2) AIC_FFSR Read-only 0x0 0x14C - 0x1E0 Reserved --- --- --- 0x1EC - 0x1FC Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S

27.8.2 AIC Source Mode Register

Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access Type:Read-write Reset Value: 0x0  PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx.  SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – SRCTYPE – – PRIOR SRCTYPE Internal Interrupt Sources External Interrupt Sources 0 0 High level Sensitive Low level Sensitive 0 1 Positive edge triggered Negative edge triggered 1 0 High level Sensitive High level Sensitive 1 1 Positive edge triggered Positive edge triggered

6242E–ATARM–11-Sep09 AT91SAM9261S

27.8.3 AIC Source Vector Register

Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access Type:Read-write Reset Value: 0x0  VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.

27.8.4 AIC Interrupt Vector Register

Name: AIC_IVR Address: 0xFFFFF100 Access Type:Read-only Reset Value: 0x0  IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 31 30 29 28 27 26 25 24 VECTOR 23 22 21 20 19 18 17 16 VECTOR 15 14 13 12 11 10 9 8 VECTOR 76543210 VECTOR 31 30 29 28 27 26 25 24 IRQV 23 22 21 20 19 18 17 16 IRQV 15 14 13 12 11 10 9 8 IRQV 76543210 IRQV

6242E–ATARM–11-Sep09 AT91SAM9261S

27.8.5 AIC FIQ Vector Register

Name: AIC_FVR Address: 0xFFFFF104 Access Type:Read-only Reset Value: 0x0  FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.

27.8.6 AIC Interrupt Status Register

Name: AIC_ISR Address: 0xFFFFF108 Access Type:Read-only Reset Value: 0x0  IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 31 30 29 28 27 26 25 24 FIQV 23 22 21 20 19 18 17 16 FIQV 15 14 13 12 11 10 9 8 FIQV 76543210 FIQV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––– I R Q I D

6242E–ATARM–11-Sep09 AT91SAM9261S

27.8.7 AIC Interrupt Pending Register

Name: AIC_IPR Address: 0xFFFFF10C Access Type:Read-only Reset Value: 0x0  FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending.

27.8.8 AIC Interrupt Mask Register

Name: AIC_IMR Address: 0xFFFFF110 Access Type:Read-only Reset Value: 0x0  FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

6242E–ATARM–11-Sep09 AT91SAM9261S

27.8.9 AIC Core Interrupt Status Register

Name: AIC_CISR Address: 0xFFFFF114 Access Type:Read-only Reset Value: 0x0  NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active.  NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active.

27.8.10 AIC Interrupt Enable Command Register

Name: AIC_IECR Address: 0xFFFFF120 Access Type: Write-only  FIQ, SYS, PID2-PID31: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

6242E–ATARM–11-Sep09 AT91SAM9261S

27.8.11 AIC Interrupt Disable Command Register

Name: AIC_IDCR Address: 0xFFFFF124 Access Type: Write-only  FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt.

27.8.12 AIC Interrupt Clear Command Register

Name: AIC_ICCR Address: 0xFFFFF128 Access Type: Write-only  FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

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27.8.13 AIC Interrupt Set Command Register

Name: AIC_ISCR Address: 0xFFFFF12C Access Type: Write-only  FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt.

27.8.14 AIC End of Interrupt Command Register

Name: AIC_EOICR Address: 0xFFFFF130 Access Type: Write-only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

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27.8.15 AIC Spurious Interrupt Vector Register

Name: AIC_SPU Address: 0xFFFFF134 Access Type: Read-write Reset Value: 0x0  SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.

27.8.16 AIC Debug Control Register

Name: AIC_DCR Address: 0xFFFFF138 Access Type: Read-write Reset Value: 0x0  PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled.  GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. 31 30 29 28 27 26 25 24 SIVR 23 22 21 20 19 18 17 16 SIVR 15 14 13 12 11 10 9 8 SIVR 76543210 SIVR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

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27.8.17 AIC Fast Forcing Enable Register

Name: AIC_FFER Address: 0xFFFFF140 Access Type: Write-only  SYS, PID2-PID31: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the corresponding interrupt.

27.8.18 AIC Fast Forcing Disable Register

Name: AIC_FFDR Address: 0xFFFFF144 Access Type: Write-only  SYS, PID2-PID31: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS – 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS –

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27.8.19 AIC Fast Forcing Status Register

Name: AIC_FFSR Address: 0xFFFFF148 Access Type: Read-only  SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt. 1 = The Fast Forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS –

6242E–ATARM–11-Sep09 AT91SAM9261S 28. Debug Unit (DBGU)

28.1 Overview

The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communica- tions. The Debug Unit two-pin UART can be used stand alone for general purpose serial communication. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the sta- tus of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of t he device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via th e In-circuit Emulator. Th is permits protection of the code, stored in ROM.

6242E–ATARM–11-Sep09 AT91SAM9261S

28.2 Block Diagram

Figure 28-1. Debug Unit Functional Block Diagram Figure 28-2. Debug Unit Application Example Peripheral DMA Controller Baud Rate Generator DCC Handler ICE Access Handler Transmit Receive Chip ID Interrupt Control Peripheral Bridge Parallel Input/ Output DTXD DRXD Power Management Controller ARM Processor force_ntrst COMMRX COMMTX MCK nTRST Power-on Reset dbgu_irq APB Debug Unit Table 28-1. Debug Unit Pin Description Pin Name Description Type DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Debug Unit RS232 Drivers Programming Tool Trace Console Debug Console Boot Program Debug Monitor Trace Manager

6242E–ATARM–11-Sep09 AT91SAM9261S

28.3 Product Dependencies

28.3.1 I/O Lines

Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.

28.3.2 Power Management

Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.

28.3.3 Interrupt Source

Depending on product integration, the Debug Unit interrupt line is connected to one of the inter- rupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 28-1 . This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.

28.4 UART Operations

The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit charac- ter handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not imple- mented. However, all the implemented features are compatible with those of a standard USART.

28.4.1 Baud Rate Generator

The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allow able baud rate is Master Clock divided by (16 x 65536). Baud Rate MCK

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 28-3. Baud Rate Generator

28.4.2 Receiver

28.4.2.1 Receiver Rese t, Enable and Disable

After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writ ing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immedi ately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in it s reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.

28.4.2.2 Start Detection and Data Sampling

The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a rece ived character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical mid- point of each bit. It is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. MCK 16-bit Counter Baud Rate Clock CD CD OUT Divide by 16 Receiver Sampling Clock

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 28-4. Start Bit Detection Figure 28-5. Character Reception

28.4.2.3 Receiver Ready

When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY sta- tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 28-6. Receiver Ready

28.4.2.4 Receiver Overrun

If DBGU_RHR has not been read by the software (o r the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a ne w character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 28-7. Receiver Overrun

28.4.2.5 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity Sampling Clock DRXD True Start Detection Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 DRXD True Start Detection Sampling Parity Bit Stop Bit Example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period D0 D1 D2 D3 D4 D5 D6 D7 PS S D0 D1 D2 D3 D4 D5 D6 D7 PDRXD Read DBGU_RHR RXRDY D0 D1 D2 D3 D4 D5 D6 D7 PS S D0 D1 D2 D3 D4 D5 D6 D7 PDRXD RSTSTA RXRDY OVRE stop stop

6242E–ATARM–11-Sep09 AT91SAM9261S bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 28-8. Parity Error

28.4.2.6 Receiver Framing Error

When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 28-9. Receiver Framing Error

28.4.3 Transmitter

28.4.3.1 Transmitter Reset, Enable and Disable

After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a ch aracter to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being pro- cessed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.

28.4.3.2 Transmit Format

The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifte d out as shown on the following figure. The field stopD0 D1 D2 D3 D4 D5 D6 D7 PSDRXD RSTSTA RXRDY PARE Wrong Parity Bit D0 D1 D2 D3 D4 D5 D6 D7 PSDRXD RSTSTA RXRDY FRAME Stop Bit Detected at 0 stop

6242E–ATARM–11-Sep09 AT91SAM9261S PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 28-10. Character Transmission

28.4.3.3 Transmitter Control

When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Regis- ter DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 28-11. Transmitter Control

28.4.4 Peripheral Data Controller

Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. D0 D1 D2 D3 D4 D5 D6 D7 DTXD Start Bit Parity Bit Stop Bit Example: Parity enabled Baud Rate Clock DBGU_THR Shift Register DTXD TXRDY TXEMPTY Data 0 Data 1 Data 0 Data 0 Data 1 Data 1S S PP Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR stopstop

6242E–ATARM–11-Sep09 AT91SAM9261S The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers t he PDC channel data transfer of the transmit- ter. This results in a write of a data in DBGU_THR.

28.4.5 Test Modes

The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transm itter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 28-12. Test Modes

28.4.6 Debug Communication Channel Support

The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Com- munication Channel of the ARM Processor and are driven by the In-circuit Emulator. Receiver Transmitter Disabled RXD TXD Receiver Transmitter Disabled RXD TXD VDD Disabled Receiver Transmitter Disabled RXD TXD Disabled Automatic Echo Local Loopback Remote Loopback VDD

6242E–ATARM–11-Sep09 AT91SAM9261S The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions ar e used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits han- dling under interrupt a debug link between a debug monitor running on the target system and a debugger.

28.4.7 Chip Identifier

The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields:  EXT - shows the use of the extension identifier register  NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size  ARCH - identifies the set of embedded peripherals  SRAMSIZ - indicates the size of the embedded SRAM  EPROC - indicates the embedded ARM processor  VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0.

28.4.8 ICE Access Prevention

The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via th e register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5 Debug Unit (DBGU) User Interface

Table 28-2. Register Mapping Offset Register Name Access Reset 0x0000 Control Register DBGU_CR Write-only – 0x0004 Mode Register DBGU_MR Read-write 0x0 0x0008 Interrupt Enable Register DBGU_IER Write-only – 0x000C Interrupt Disable Register DBGU_IDR Write-only – 0x0010 Interrupt Mask Register DBGU_IMR Read-only 0x0 0x0014 Status Register DBGU_SR Read-only – 0x0018 Receive Holding Register DBGU_RHR Read-only 0x0 0x001C Transmit Holding Register DBGU_THR Write-only – 0x0020 Baud Rate Generator Register DBGU_BRGR Read-write 0x0 0x0024 - 0x003C Reserved – – – 0x0040 Chip ID Register DBGU_CIDR Read-only – 0x0044 Chip ID Extension Register DBGU_EXID Read-only – 0x0048 Force NTRST Register DBGU_FNR Read-write 0x0 0x004C - 0x00FC Reserved – – – 0x0100 - 0x0124 PDC Area – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.1 Debug Unit Control Register

Name: DBGU_CR Address: 0xFFFFF200 Access Type: Write-only  RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.  RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.  RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.  RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.  TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.  TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is bei ng processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.  RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXDIS TXEN RXDIS RXEN RSTTX RSTRX ––

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.2 Debug Unit Mode Register

Name: DBGU_MR Address: 0xFFFFF204 Access Type: Read-write  PAR: Parity Type  CHMODE: Channel Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE –– PAR – 76543210 PAR Parity Type 0 0 0 Even parity

001 O d d p a r i t y

0 1 0 Space: parity forced to 0 0 1 1 Mark: parity forced to 1 1 x x No parity CHMODE Mode Description

00 N o r m a l M o d e

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.3 Debug Unit Interrupt Enable Register

Name: DBGU_IER Address: 0xFFFFF208 Access Type: Write-only  RXRDY: Enable RXRDY Interrupt  TXRDY: Enable TXRDY Interrupt  ENDRX: Enable End of Receive Transfer Interrupt  ENDTX: Enable End of Transmit Interrupt  OVRE: Enable Overrun Error Interrupt  FRAME: Enable Framing Error Interrupt  PARE: Enable Parity Error Interrupt  TXEMPTY: Enable TXEMPTY Interrupt  TXBUFE: Enable Buffer Empty Interrupt  RXBUFF: Enable Buffer Full Interrupt  COMMTX: Enable COMMTX (from ARM) Interrupt  COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– RXBUFF TXBUFE – TXEMPTY – 76543210 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.4 Debug Unit Interrupt Disable Register

Name: DBGU_IDR Address: 0xFFFFF20C Access Type: Write-only  RXRDY: Disable RXRDY Interrupt  TXRDY: Disable TXRDY Interrupt  ENDRX: Disable End of Receive Transfer Interrupt  ENDTX: Disable End of Transmit Interrupt  OVRE: Disable Overrun Error Interrupt  FRAME: Disable Framing Error Interrupt  PARE: Disable Parity Error Interrupt  TXEMPTY: Disable TXEMPTY Interrupt  TXBUFE: Disable Buffer Empty Interrupt  RXBUFF: Disable Buffer Full Interrupt  COMMTX: Disable COMMTX (from ARM) Interrupt  COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– RXBUFF TXBUFE – TXEMPTY – 76543210 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.5 Debug Unit Interrupt Mask Register

Name: DBGU_IMR Address: 0xFFFFF210 Access Type: Read-only  RXRDY: Mask RXRDY Interrupt  TXRDY: Disable TXRDY Interrupt  ENDRX: Mask End of Receive Transfer Interrupt  ENDTX: Mask End of Transmit Interrupt  OVRE: Mask Overrun Error Interrupt  FRAME: Mask Framing Error Interrupt  PARE: Mask Parity Error Interrupt  TXEMPTY: Mask TXEMPTY Interrupt  TXBUFE: Mask TXBUFE Interrupt  RXBUFF: Mask RXBUFF Interrupt  COMMTX: Mask COMMTX Interrupt  COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– RXBUFF TXBUFE – TXEMPTY – 76543210 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.6 Debug Unit Status Register

Name: DBGU_SR Address: 0xFFFFF214 Access Type: Read-only  RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.  TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.  ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.  ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.  OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA.  FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA.  PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA.  TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– RXBUFF TXBUFE – TXEMPTY – 76543210 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S  TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active.  RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active.  COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active.  COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active.

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.7 Debug Unit Receiver Holding Register

Name: DBGU_RHR Address: 0xFFFFF218 Access Type: Read-only  RXCHR: Received Character Last received character if RXRDY is set.

28.5.8 Debug Unit Transmit Holding Register

Name: DBGU_THR Address: 0xFFFFF21C Access Type: Write-only  TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXCHR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXCHR

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.9 Debug Unit Baud Ra te Generator Register

Name: DBGU_BRGR Address: 0xFFFFF220 Access Type: Read-write  CD: Clock Divisor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 76543210 CD CD Baud Rate Clock

0 Disabled

2 to 65535 MCK / (CD x 16)

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.10 Debug Unit Chip ID Register

Name: DBGU_CIDR Address: 0xFFFFF240 Access Type:Read-only  VERSION: Version of the Device Current version of the device.  EPROC: Embedded Processor  NVPSIZ: Nonvolatile Program Memory Size 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH SRAMSIZ 15 14 13 12 11 10 9 8 NVPSIZ2 NVPSIZ 76543210 EPROC VERSION EPROC Processor 0 0 1 ARM946ES 0 1 0 ARM7TDMI

100 A R M 9 2 0 T

0000 N o n e

0100 R e s e r v e d

0110 R e s e r v e d

1000 R e s e r v e d

1011 R e s e r v e d

6242E–ATARM–11-Sep09 AT91SAM9261S  NVPSIZ2 Second Nonvolatile Program Memory Size  SRAMSIZ: Internal SRAM Size

1101 R e s e r v e d

1111 R e s e r v e d

0000 R e s e r v e d

NVPSIZ (Continued) Size

6242E–ATARM–11-Sep09 AT91SAM9261S  ARCH: Architecture Identifier  NVPTYP: Nonvolatile Program Memory Type 1100 1 2 8 K b y t e s 1101 2 5 6 K b y t e s 1110 9 6 K b y t e s 1111 5 1 2 K b y t e s ARCH ArchitectureHex Bin 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 0111 0001 AT91SAM7XCxx Series 0x72 0111 0010 AT91SAM7SExx Series 0x73 0111 0011 AT91SAM7Lxx Series 0x75 0111 0101 AT91SAM7Xxx Series 0x92 1001 0010 AT91x92 Series 0xF0 1111 0000 AT75Cxx Series NVPTYP Memory

000 R O M

0 0 1 ROMless or on-chip Flash 1 0 0 SRAM emulating ROM 0 1 0 Embedded Flash Memory 011 ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size SRAMSIZ (Continued) Size

6242E–ATARM–11-Sep09 AT91SAM9261S  EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.

6242E–ATARM–11-Sep09 AT91SAM9261S

28.5.11 Debug Unit Chip ID Extension Register

Name: DBGU_EXID Address: 0xFFFFF244 Access Type: Read-only  EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.

28.5.12 Debug Unit Force NTRST Register

Name: DBGU_FNR Address: 0xFFFFF248 Access Type:Read-write  FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low. 31 30 29 28 27 26 25 24 EXID 23 22 21 20 19 18 17 16 EXID 15 14 13 12 11 10 9 8 EXID 76543210 EXID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654321 0

6242E–ATARM–11-Sep09 AT91SAM9261S 29. Peripheral Input/Output Controller (PIO)

29.1 Overview

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features:  An input change interrupt enabling level change detection on any I/O line.  A glitch filter providing rejection of pulses lower than one-half of clock cycle.  Multi-drive capability similar to an open drain I/O line.  Control of the pull-up of the I/O line.  Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

6242E–ATARM–11-Sep09 AT91SAM9261S

29.2 Block Diagram

Figure 29-1. Block Diagram Figure 29-2. Application Block Diagram Embedded Peripheral Embedded Peripheral PIO Interrupt PIO Controller Up to 32 pins PMC Up to 32 peripheral IOs Up to 32 peripheral IOs PIO Clock APB AIC Data, Enable PIN 31 PIN 1 PIN 0 Data, Enable On-Chip Peripherals PIO Controller On-Chip Peripheral Drivers Control & Command Driver Keyboard Driver Keyboard Driver General Purpose I/Os External Devices

6242E–ATARM–11-Sep09 AT91SAM9261S

29.3 Product Dependencies

29.3.1 Pin Multiplexing

Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Con- troller can control how the pin is driven by the product.

29.3.2 External Interrupt Lines

The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs.

29.3.3 Power Management

The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of t he features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.

29.3.4 Interrupt Generation

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the produc t description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.

6242E–ATARM–11-Sep09 AT91SAM9261S

29.4 Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic asso- ciated to each I/O is represented in Figure 29-3 . In this description each signal shown represents but one of up to 32 possible indexes. Figure 29-3. I/O Line Control Logic Glitch Filter Peripheral B Input Peripheral A Input PIO_IFDR[0] PIO_IFSR[0] PIO_IFER[0] Edge Detector PIO_PDSR[0] PIO_ISR[0] PIO_IDR[0] PIO_IMR[0] PIO_IER[0] PIO Interrupt (Up to 32 possible inputs) PIO_ISR[31] PIO_IMR[31] PIO_IER[31] Pad PIO_PUDR[0] PIO_PUSR[0] PIO_PUER[0] PIO_MDDR[0] PIO_MDSR[0] PIO_MDER[0] PIO_CODR[0] PIO_ODSR[0] PIO_SODR[0] PIO_PDR[0] PIO_PSR[0] PIO_PER[0] PIO_BSR[0] PIO_ABSR[0] PIO_ASR[0] Peripheral B Output Enable Peripheral A Output Enable Peripheral B Output Peripheral A Output PIO_ODR[0] PIO_OSR[0] PIO_OER[0] PIO_OWDR[0] PIO_OWSR[0] PIO_OWER[0]

6242E–ATARM–11-Sep09 AT91SAM9261S

29.4.1 Pull-up Resistor Control

Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull- up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Readi ng a 1 in PIO_PUSR means the pull-up is dis- abled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.

29.4.2 I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two periph eral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The regis- ter PIO_PSR (PIO Status Register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the co rresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Regist er). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.

29.4.3 Peripheral A or B Selection

The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Regis- ter). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corre- sponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR an d PIO_BSR manages PIO_ABSR regardless of th e configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR.

29.4.4 Output Control

When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).

6242E–ATARM–11-Sep09 AT91SAM9261S The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manage s PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configura- tion of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

29.4.5 Synchronous Data Output

Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

29.4.6 Multi Drive Control (Open Drain)

Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.

29.4.7 Output Line Timings

Figure 29-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is va lid only if the corresponding bit in PIO_OWSR is set. Figure 29-4 also shows when the feedback in PIO_PDSR is available.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 29-4. Output Line Timings

29.4.8 Inputs

The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg- ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

29.4.9 Input Glitch Filtering

Optional input glitch filters are independently programmable on each I/O line. When the glitch fil- ter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Mast er Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 29-5. The glitch filters are controlled by the regist er set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. 2 cycles APB Access 2 cycles APB Access MCK Write PIO_SODR Write PIO_ODSR at 1 PIO_ODSR PIO_PDSR Write PIO_CODR Write PIO_ODSR at 0

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 29-5. Input Glitch Filter Timing

29.4.10 Input Change Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is cont rolled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, con- trolled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to gen- erate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 29-6. Input Change Interrupt Timings

29.5 I/O Lines Programming Example

The programing example as shown in Table 29-1 below is used to define the following configuration.  4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor MCK Pin Level PIO_PDSR if PIO_IFSR = 0 PIO_PDSR if PIO_IFSR = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle MCK Pin Level Read PIO_ISR APB Access PIO_ISR APB Access

6242E–ATARM–11-Sep09 AT91SAM9261S  Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor  Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts  Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter  I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor  I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor  I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 29-1. Programming Example Register Value to be Written PIO_PER 0x0000 FFFF PIO_PDR 0x0FFF 0000 PIO_OER 0x0000 00FF PIO_ODR 0x0FFF FF00 PIO_IFER 0x0000 0F00 PIO_IFDR 0x0FFF F0FF PIO_SODR 0x0000 0000 PIO_CODR 0x0FFF FFFF PIO_IER 0x0F00 0F00 PIO_IDR 0x00FF F0FF PIO_MDER 0x0000 000F PIO_MDDR 0x0FFF FFF0 PIO_PUDR 0x00F0 00F0 PIO_PUER 0x0F0F FF0F PIO_ASR 0x0F0F 0000 PIO_BSR 0x00F0 0000 PIO_OWER 0x0000 000F PIO_OWDR 0x0FFF FFF0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6 Parallel Input/Output Cont roller (PIO) User Interface

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control- ler User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not mul- tiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 29-2. Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only – 0x0004 PIO Disable Register PIO_PDR Write-only – 0x0008 PIO Status Register PIO_PSR Read-only (1) 0x000C Reserved 0x0010 Output Enable Register PIO_OER Write-only – 0x0014 Output Disable Register PIO_ODR Write-only – 0x0018 Output Status Regist er PIO_OSR Read-only 0x0000 0000 0x001C Reserved 0x0020 Glitch Input Filter Enab le Register PIO_IFER Write-only – 0x0024 Glitch Input Filter Disab le Register PIO_IFDR Write-only – 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000 0x002C Reserved 0x0030 Set Output Data Register PIO_SODR Write-only – 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or (2) Read-write 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only – 0x0044 Interrupt Disable Register PIO_IDR Write-only – 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 0x004C Interrupt Status Register (4) PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only – 0x0054 Multi-driver Disable Register PIO_MDDR Write-only – 0x0058 Multi-driver Status Re gister PIO_MDSR Read-only 0x00000000 0x005C Reserved 0x0060 Pull-up Disable Register PIO_PUDR Write-only – 0x0064 Pull-up Enable Register PIO_PUER Write-only – 0x0068 Pad Pull-up Status Regi ster PIO_PUSR Read-only 0x00000000 0x006C Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S Notes: 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read-write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O line s. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the stat us by writing 1 in the first register and sets the status by writing 1 in the second register. 0x0070 Peripheral A Select Register (5) PIO_ASR Write-only – 0x0074 Peripheral B Select Register (5) PIO_BSR Write-only – 0x0078 AB Status Register (5) PIO_ABSR Read-only 0x00000000 0x007C to 0x009C Reserved 0x00A0 Output Write Enab le PIO_OWER Write-only – 0x00A4 Output Write Disab le PIO_OWDR Write-only – 0x00A8 Output Write Status Re gister PIO_OWSR Read-only 0x00000000 0x00AC Reserved Table 29-2. Register Mapping (Continued) Offset Register Name Access Reset

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.1 PIO Controller PIO Enable Register

Name: PIO_PER Addresses: 0xFFFFF400 (PIOA), 0xFFFFF600 (PIOB), 0xFFFFF800 (PIOC) Access Type:Write-only  P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

29.6.2 PIO Controller PIO Disable Register

Name: PIO_PDR Addresses: 0xFFFFF404 (PIOA), 0xFFFFF604 (PIOB), 0xFFFFF804 (PIOC) Access Type:Write-only  P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.3 PIO Controller PIO Status Register

Name: PIO_PSR Addresses: 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC) Access Type:Read-only  P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive).

29.6.4 PIO Controller Output Enable Register

Name: PIO_OER Addresses: 0xFFFFF410 (PIOA), 0xFFFFF610 (PIOB), 0xFFFFF810 (PIOC) Access Type:Write-only  P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.5 PIO Controller Output Disable Register

Name: PIO_ODR Addresses: 0xFFFFF414 (PIOA), 0xFFFFF614 (PIOB), 0xFFFFF814 (PIOC) Access Type:Write-only  P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line.

29.6.6 PIO Controller Output Status Register

Name: PIO_OSR Addresses: 0xFFFFF418 (PIOA), 0xFFFFF618 (PIOB), 0xFFFFF818 (PIOC) Access Type:Read-only  P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.7 PIO Controller Input Filter Enable Register

Name: PIO_IFER Addresses: 0xFFFFF420 (PIOA), 0xFFFFF620 (PIOB), 0xFFFFF820 (PIOC) Access Type:Write-only  P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line.

29.6.8 PIO Controller Input Filter Disable Register

Name: PIO_IFDR Addresses: 0xFFFFF424 (PIOA), 0xFFFFF624 (PIOB), 0xFFFFF824 (PIOC) Access Type:Write-only  P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.9 PIO Controller Input Filter Status Register

Name: PIO_IFSR Addresses: 0xFFFFF428 (PIOA), 0xFFFFF628 (PIOB), 0xFFFFF828 (PIOC) Access Type:Read-only  P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line.

29.6.10 PIO Controller Set Output Data Register

Name: PIO_SODR Addresses: 0xFFFFF430 (PIOA), 0xFFFFF630 (PIOB), 0xFFFFF830 (PIOC) Access Type:Write-only  P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.11 PIO Controller Clear Output Data Register

Name: PIO_CODR Addresses: 0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC) Access Type:Write-only  P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line.

29.6.12 PIO Controller Output Data Status Register

Name: PIO_ODSR Addresses: 0xFFFFF438 (PIOA), 0xFFFFF638 (PIOB), 0xFFFFF838 (PIOC) Access Type:Read-only or Read-write  P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.13 PIO Controller Pin Data Status Register

Name: PIO_PDSR Addresses: 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC) Access Type:Read-only  P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1.

29.6.14 PIO Controller Interrupt Enable Register

Name: PIO_IER Addresses: 0xFFFFF440 (PIOA), 0xFFFFF640 (PIOB), 0xFFFFF840 (PIOC) Access Type:Write-only  P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.15 PIO Controller Interrupt Disable Register

Name: PIO_IDR Addresses: 0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC) Access Type:Write-only  P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line.

29.6.16 PIO Controller Interrupt Mask Register

Name: PIO_IMR Addresses: 0xFFFFF448 (PIOA), 0xFFFFF648 (PIOB), 0xFFFFF848 (PIOC) Access Type:Read-only  P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.17 PIO Controller Interrupt Status Register

Name: PIO_ISR Addresses: 0xFFFFF44C (PIOA), 0xFFFFF64C (PIOB), 0xFFFFF84C (PIOC) Access Type:Read-only  P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

29.6.18 PIO Multi-driver Enable Register

Name: PIO_MDER Addresses: 0xFFFFF450 (PIOA), 0xFFFFF650 (PIOB), 0xFFFFF850 (PIOC) Access Type:Write-only  P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.19 PIO Multi-driver Disable Register

Name: PIO_MDDR Addresses: 0xFFFFF454 (PIOA), 0xFFFFF654 (PIOB), 0xFFFFF854 (PIOC) Access Type:Write-only  P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line.

29.6.20 PIO Multi-driver Status Register

Name: PIO_MDSR Addresses: 0xFFFFF458 (PIOA), 0xFFFFF658 (PIOB), 0xFFFFF858 (PIOC) Access Type:Read-only  P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.21 PIO Pull Up Disable Register

Name: PIO_PUDR Addresses: 0xFFFFF460 (PIOA), 0xFFFFF660 (PIOB), 0xFFFFF860 (PIOC) Access Type:Write-only  P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line.

29.6.22 PIO Pull Up Enable Register

Name: PIO_PUER Addresses: 0xFFFFF464 (PIOA), 0xFFFFF664 (PIOB), 0xFFFFF864 (PIOC) Access Type:Write-only  P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.23 PIO Pull Up Status Register

Name: PIO_PUSR Addresses: 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC) Access Type:Read-only  P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line.

29.6.24 PIO Peripheral A Select Register

Name: PIO_ASR Addresses: 0xFFFFF470 (PIOA), 0xFFFFF670 (PIOB), 0xFFFFF870 (PIOC) Access Type:Write-only  P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.25 PIO Peripheral B Select Register

Name: PIO_BSR Addresses: 0xFFFFF474 (PIOA), 0xFFFFF674 (PIOB), 0xFFFFF874 (PIOC) Access Type:Write-only  P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function.

29.6.26 PIO Peripheral A B Status Register

Name: PIO_ABSR Addresses: 0xFFFFF478 (PIOA), 0xFFFFF678 (PIOB), 0xFFFFF878 (PIOC) Access Type:Read-only  P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.27 PIO Output Write Enable Register

Name: PIO_OWER Addresses: 0xFFFFF4A0 (PIOA), 0xFFFFF6A0 (PIOB), 0xFFFFF8A0 (PIOC) Access Type:Write-only  P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line.

29.6.28 PIO Output Write Disable Register

Name: PIO_OWDR Addresses: 0xFFFFF4A4 (PIOA), 0xFFFFF6A4 (PIOB), 0xFFFFF8A4 (PIOC) Access Type:Write-only  P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S

29.6.29 PIO Output Write Status Register

Name: PIO_OWSR Addresses: 0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC) Access Type:Read-only  P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

6242E–ATARM–11-Sep09 AT91SAM9261S 30. Serial Peripheral Interface (SPI)

30.1 Overview

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com- munication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asse rts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines:  Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).  Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.  Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.  Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

6242E–ATARM–11-Sep09 AT91SAM9261S

30.2 Block Diagram

Figure 30-1. Block Diagram SPI Interface Interrupt Control PIO PDC PMC MCK SPI Interrupt SPCK MISO MOSI NPCS0/NSS NPCS1 NPCS2 NPCS3 APB

6242E–ATARM–11-Sep09 AT91SAM9261S

30.3 Application Block Diagram

Figure 30-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK MISO MOSI NPCS0 NPCS1 NPCS2 SPCK MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 2 NC NPCS3

6242E–ATARM–11-Sep09 AT91SAM9261S

30.4 Signal Description

30.5 Product Dependencies

30.5.1 I/O Lines

The pins used for interfacing the compliant ex ternal devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.

30.5.2 Power Management

The SPI may be clocked through the Power Management Controller (PMC), thus the program- mer must first configure the PMC to enable the SPI clock.

30.5.3 Interrupt

The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI. Table 30-1. Signal Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input

6242E–ATARM–11-Sep09 AT91SAM9261S

30.6 Functional Description

30.6.1 Modes of Operation

The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the re ceiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.

30.6.2 Data Transfer

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine th e edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. Table 30-2 shows the four modes and corresponding parameter settings. Figure 30-3 and Figure 30-4 show examples of data transfers. Table 30-2. SPI Bus Protocol Mode SPI Mode CPOL NCPHA 00 1 10 0 21 1 31 0

6242E–ATARM–11-Sep09 AT91SAM9261S

30.6.3 Master Mode Operations

When configured in Master Mode, the SPI operates on the clock generated by the internal pro- grammable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Regis- ter, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Trans- mit Data Register). The written data is immediat ely transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in t he Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 30-5, shows a block diagram of the SPI when operating in Master Mode. Figure 30-6 on page 353 shows a flow chart describing how transfers are handled.

6242E–ATARM–11-Sep09 AT91SAM9261S

30.6.3.1 Master Mode Block Diagram

Figure 30-5. Master Mode Block Diagram Shift Register SPCK MOSILSB MSBMISO SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0..3 CPOL NCPHA BITS MCK Baud Rate Generator SPI_CSR0..3 SCBR NPCS3 NPCS0 NPCS2 NPCS1 NPCS0 PS SPI_MR PCS SPI_TDR PCS MODF Current Peripheral SPI_RDR PCS SPI_CSR0..3 CSAAT PCSDEC MODFDIS MSTR

6242E–ATARM–11-Sep09 AT91SAM9261S

30.6.3.2 Master Mode Flow Diagram

Figure 30-6. Master Mode Flow Diagram SPI Enable CSAAT ? PS ? NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 TDRE ? NPCS = 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT CSAAT ? TDRE ? PS ? SPI_TDR(PCS) = NPCS ? no yes SPI_MR(PCS) = NPCS ? no NPCS = 0xF Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = 0xF Delay DLYBCS NPCS = SPI_MR(PCS), SPI_TDR(PCS) Fixed peripheral Variable peripheral - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.

6242E–ATARM–11-Sep09 AT91SAM9261S

30.6.3.3 Clock Generation

The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.

30.6.3.4 Transfer Delays

Figure 30-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms:  The delay between chip selects, programmable only once for all the chip selects by writing the DL YBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.  The delay before SPCK, independently programmable for each chip select by writing the field DL YBS. Allows the start of SPCK to be delayed after the chip select has been asserted.  The delay between consecutive transfers, independently programmable for each chip select by writing the DL YBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 30-7. Programmable Delays

30.6.3.5 Peripheral Selection

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways:  Fixed Peripheral Select: SPI exchanges data with only one peripheral DLYBCS DLYBS DLYBCT DLYBCT Chip Select 1 Chip Select 2 SPCK

6242E–ATARM–11-Sep09 AT91SAM9261S  Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by se tting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro- gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the Lisps and th e PCS and LASTXFER fields in the MSBs, how- ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.

30.6.3.6 Peripheral Chip Select Decoding

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external l ogic. This can be enabled by writing the PCS- DEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.

30.6.3.7 Peripheral Deselection

When operating normally, as soon as the transfer of the last data written in SPI_TDR is com- pleted, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 30-8 shows different peripheral Deselection cases and the effect of the CSAAT bit. Figure 30-8. Peripheral Deselection

30.6.3.8 Mode Fault Detection

A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be con- figured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabl ed until re-enabled by writing t he SPIEN bit in the SPI_CR (Con- trol Register) at 1. By default, the Mode Fault detection circuitr y is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).

30.6.4 SPI Slave Mode

When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS DLYBCT PCS=A A DLYBCS DLYBCT A PCS = A AA DLYBCT AA CSAAT = 0 DLYBCT AA CSAAT = 1 A

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7 Serial Peripheral Inte rface (SPI) User Interface

Table 30-3. Register Mapping Offset Register Name Access Reset 0x00 Control Register SPI_CR Write-only --- 0x04 Mode Register SPI_MR Read-write 0x0 0x08 Receive Data Register SPI_RDR Read-only 0x0 0x0C Transmit Data Register SPI_TDR Write-only --- 0x10 Status Register SPI_SR Read-only 0x000000F0 0x14 Interrupt Enable Register SPI_IER Write-only --- 0x18 Interrupt Disable Register SPI_IDR Write-only --- 0x1C Interrupt Mask Register SPI_IMR Read-only 0x0 0x20 - 0x2C Reserved 0x30 Chip Select Register 0 SPI_CSR0 Read-write 0x0 0x34 Chip Select Register 1 SPI_CSR1 Read-write 0x0 0x38 Chip Select Register 2 SPI_CSR2 Read-write 0x0 0x3C Chip Select Register 3 SPI_CSR3 Read-write 0x0 0x004C - 0x00F8 Reserved – – – 0x004C - 0x00FC Reserved – – – 0x100 - 0x124 Reserved for the PDC

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.1 SPI Control Register

Name: SPI_CR Addresses: 0xFFFC8000 (0), 0xFFFCC000 (1) Access Type: Write-only  SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data.  SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.  SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset.  LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted afte r the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 S W R S T ––––– S P I D I S S P I E N

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.2 SPI Mode Register

Name: SPI_MR Addresses: 0xFFFC8004 (0), 0xFFFCC004 (1) Access Type: Read/Write  MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.  PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.  PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14.  MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled.  LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for te sting in Master Mode only. (MISO is internally connected on MOSI.) 31 30 29 28 27 26 25 24 DL YBCS 23 22 21 20 19 18 17 16 –––– P C S 15 14 13 12 11 10 9 8 76543210 LLB – – MODFDIS – PCSDEC PS MSTR

6242E–ATARM–11-Sep09 AT91SAM9261S  PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS.  DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: Delay Between Chip Selects DLYBCS

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.3 SPI Receive Data Register

Name: SPI_RDR Addresses: 0xFFFC8008 (0), 0xFFFCC008 (1) Access Type: Read-only  RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.  PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– P C S 15 14 13 12 11 10 9 8 RD 76543210 RD

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.4 SPI Transmit Data Register

Name: SPI_TDR Addresses: 0xFFFC800C (0), 0xFFFCC00C (1) Access Type: Write-only  TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.  PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS  LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted afte r the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– P C S 15 14 13 12 11 10 9 8 TD 76543210 TD

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.5 SPI Status Register

Name: SPI_SR Addresses: 0xFFFC8010 (0), 0xFFFCC010 (1) Access Type: Read-only  RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.  TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.  MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.  OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.  ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).  ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).  RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF

6242E–ATARM–11-Sep09 AT91SAM9261S  TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0.  NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read.  TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.  SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.6 SPI Interrupt Enable Register

Name: SPI_IER Addresses: 0xFFFC8014 (0), 0xFFFCC014 (1) Access Type: Write-only 0 = No effect. 1 = Enables the corresponding interrupt.  RDRF: Receive Data Register Full Interrupt Enable  TDRE: SPI Transmit Data Regi ster Empty Interrupt Enable  MODF: Mode Fault Error Interrupt Enable  OVRES: Overrun Error Interrupt Enable  ENDRX: End of Receive Buffer Interrupt Enable  ENDTX: End of Transmit Buffer Interrupt Enable  RXBUFF: Receive Buffer Full Interrupt Enable  TXBUFE: Transmit Buffer Empty Interrupt Enable  NSSR: NSS Rising Interrupt Enable  TXEMPTY: Transmission Registers Empty Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.7 SPI Interrupt Disable Register

Name: SPI_IDR Addresses: 0xFFFC8018 (0), 0xFFFCC018 (1) Access Type: Write-only 0 = No effect. 1 = Disables the corresponding interrupt.  RDRF: Receive Data Register Full Interrupt Disable  TDRE: SPI Transmit Data Register Empty Interrupt Disable  MODF: Mode Fault Error Interrupt Disable  OVRES: Overrun Error Interrupt Disable  ENDRX: End of Receive Buffer Interrupt Disable  ENDTX: End of Transmit Buffer Interrupt Disable  RXBUFF: Receive Buffer Full Interrupt Disable  TXBUFE: Transmit Buffer Empty Interrupt Disable  NSSR: NSS Rising Interrupt Disable  TXEMPTY: Transmission Registers Empty Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.8 SPI Interrupt Mask Register

Name: SPI_IMR Addresses: 0xFFFC801C (0), 0xFFFCC01C (1) Access Type: Read-only 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.  RDRF: Receive Data Register Full Interrupt Mask  TDRE: SPI Transmit Data Register Empty Interrupt Mask  MODF: Mode Fault Error Interrupt Mask  OVRES: Overrun Error Interrupt Mask  ENDRX: End of Receive Buffer Interrupt Mask  ENDTX: End of Transmit Buffer Interrupt Mask  RXBUFF: Receive Buffer Full Interrupt Mask  TXBUFE: Transmit Buffer Empty Interrupt Mask  NSSR: NSS Rising Interrupt Mask  TXEMPTY: Transmission Registers Empty Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF

6242E–ATARM–11-Sep09 AT91SAM9261S

30.7.9 SPI Chip Select Register

Name: SPI_CSR0... SPI_CSR3 Addresses: 0xFFFC8030 (0), 0xFFFCC030 (1) Access Type: Read/Write Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans- lated value unless the register is written.  CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.  NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.  CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.  BITS: Bits Per Transfer (See the (Note:) below the register table; Section 30.7.9 “SPI Chip Select Register”.) The BITS field determines the number of data bits transferred. Reserved values should not be used. 31 30 29 28 27 26 25 24 DL YBCT 23 22 21 20 19 18 17 16 DL YBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS CSAAT – NCPHA CPOL BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15

6242E–ATARM–11-Sep09 AT91SAM9261S  SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.  DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay:  DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 1000 16

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

Delay Between Consecutive Transfers 32 DLYBCT×

6242E–ATARM–11-Sep09 AT91SAM9261S 31. Two-wire Interface (TWI)

31.1 Description

The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-ori- ented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clo ck (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as master transmitter or master receiver with sequential or single-byte access. A configurable baud rate generator per- mits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 31-1 lists the compatibility level of the Atmel Two-wire Interface and a full I²C compatible device. Notes: 1. START + b000000001 + Ack + Sr 2. A repeated start condition is only sup ported in Master Receiver mode. See Section 31.6.5 “Internal Address” on page 376

31.2 List of Abbreviations

Table 31-1. Atmel TWI Compatibility with I²C Standard I2C Standard Atmel TWI Standard Mode Speed (100 KHz) Supported Fast Mode Speed (400 KHz) Supported 7 or 10 bits Slave Addressing Supported START BYTE (1) Not Supported Repeated Start (Sr) Condition Not Fully Supported (2) ACK and NACK Management Supported Slope control and input filtering (Fast mode) Not Supported Clock stretching Supported Multi Master Capability Not Supported Table 31-2. Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge PS t o p SS t a r t Sr Repeated Start SADR Slave Address ADR Any address except SADR RR e a d WW r i t e

6242E–ATARM–11-Sep09 AT91SAM9261S

31.3 Block Diagram

Figure 31-1. Block Diagram

31.4 Application Block Diagram

Figure 31-2. Application Block Diagram

31.4.1 I/O Lines Description

31.5 Product Dependencies

31.5.1 I/O Lines

Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 31-2 on page 372 ). When the bus is free, both lines are APB Bridge PMC MCK Two-wire Interface PIO AIC TWI Interrupt TWCK TWD Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I²C RTC I²C LCD Controller Slave 1 Slave 2 Slave 3 VDD I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp Table 31-3. I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output

6242E–ATARM–11-Sep09 AT91SAM9261S high. The output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PI O lines. To enable the TWI, the programmer must perform the following step:  Program the PIO controller to dedicate TWD and TWCK as peripheral lines. The user must not program TWD and TWCK as open-drain. It is already done by the hardware.

31.5.2 Power Management

 Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock.

31.5.3 Interrupt

The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI.

31.6 Functional Description

31.6.1 Transfer format

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 31-4 on page 373). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 31-3 on page 373).  A high-to-low transition on the TWD line while TWCK is high defines the START condition.  A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 31-3. START and STOP Conditions Figure 31-4. Transfer Format

31.6.2 Modes of Operation

The TWI has two modes of operation: TWD TWCK Start Stop TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop

6242E–ATARM–11-Sep09 AT91SAM9261S  Master transmitter mode  Master receiver mode The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Gener- ator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.

31.6.3 Master Transmitter Mode

After the master initiates a Start condition when writing into the Tran smit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowl- edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. T he master polls the data line during this clock pulse and sets the Not Acknowledge bit ( NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set un til a new write in the TWI_THR. When no more data is written into the TWI_THR, the master generates a stop condition to end the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one. See Figure 31-5, Figure 31-6, and Figure 31-7. Figure 31-5. Master Write with One Data Byte Figure 31-6. Master Write with Multiple Data Byte TXCOMP TXRDY Write THR (DATA) STOP sent automaticaly (ACK received and TXRDY = 1) TWD A DATA AS DADR W P A DATA n AS DADR W DATA n+5 A P DATA n+x A TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) TWD

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-7. Master Write with One Byte Internal Address and Multiple Data Bytes

31.6.4 Master Receiver Mode

The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this ca se (MREAD = 1 in TWI_MMR). During the acknowl- edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. T he master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowle dge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 31-9. When the RXRDY bit is set in the status register, a character has been received in the receive-holding reg- ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 31-8. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to- Figure 31-8. Master Read with One Data Byte A IADR(7:0) A DATA n AS DADR W DATA n+5 A P DATA n+x A TXCOMP TXRDY TWD Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) AS DADR R DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR TWD

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-9. Master Read with Multiple Data Bytes

31.6.5 Internal Address

The TWI interface can perform various transfe r formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 31.6.5.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page loca- tion in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I²C fully-compatible devices. See Figure 31-10, Figure 31-11 and Figure 31-12. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to In the figures below the following abbreviations are used: NAS DADR R DATA n A A DATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD TXCOMP Write START Bit RXRDY Write STOP Bit after next-to-last data read Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) S Start P Stop W Write R Read A Acknowledge N Not Acknowledge D A D R Device Address I A D R Internal Address

6242E–ATARM–11-Sep09 AT91SAM9261S

31.6.6 Read/Write Flowcharts

The following flowcharts shown in Figure 31-13 , Figure 31-14 on page 379 , Figure 31-15 on page 380, Figure 31-16 on page 381, Figure 31-17 on page 382 and Figure 31-18 on page 383 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 31-13. TWI Write Operation with Single Data Byte without Internal Address Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Ye s Ye s BEGIN No No

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-14. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Load transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Set the internal address TWI_IADR = address Ye s Ye s No No

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-15. TWI Write Operation with Multiple Data Bytes with or without Internal Address Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 Internal address size = 0? Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Data to send? Read Status register TXCOMP = 1? END BEGIN Set the internal address TWI_IADR = addressYe s TWI_THR = data to send Ye s Ye s Ye s No No No Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once)

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-16. TWI Read Operation with Single Data Byte without Internal Address Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Read Status register TXCOMP = 1? END BEGIN Ye s Ye s Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Read Receive Holding Register No No

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-17. TWI Read Operation with Single Data Byte and Internal Address Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Read Status register TXCOMP = 1? END BEGIN Ye s Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Ye s Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register RXRDY = 1? Read Receive Holding register No No

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 31-18. TWI Read Operation with Multiple Data Bytes with or without Internal Address Internal address size = 0? Start the transfer TWI_CR = START Stop the transfer TWI_CR = STOP Read Status register RXRDY = 1? Last data to read but one? Read status register TXCOMP = 1? END Set the internal address TWI_IADR = address Ye s Ye s Ye s No Ye s Read Receive Holding register (TWI_RHR) No Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) No Read Status register RXRDY = 1? Ye s Read Receive Holding register (TWI_RHR) No

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7 Universal Synchronous Async hronous Receiver Transmitter (USART) User Interface

Table 31-4. Register Mapping Offset Register Name Access Reset 0x0000 Control Register TWI_CR Write-only N/A 0x0004 Master Mode Register TWI_MMR Read-write 0x0000 0x0008 Reserved - - - 0x000C Internal Address Register TWI_IADR Read-write 0x0000 0x0010 Clock Waveform Generator Register TWI_CWGR Read-write 0x0000 0x0020 Status Register TWI_SR Read-only 0x0008 0x0024 Interrupt Enable Re gister TWI_IER Write-only N/A 0x0028 Interrupt Disable Register TWI_IDR Write-only N/A 0x002C Interrupt Mask Register TWI_IMR Read-only 0x0000 0x0030 Receive Holding Register TWI_RHR Read-only 0x0000 0x0034 Transmit Holding Register TWI_THR Read-write 0x0000

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.1 TWI Control Register

Register Name: TWI_CR Access Type: Write-only  START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).  STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.  MSEN: TWI Master Transfer Enabled 0 = No effect. 1 = If MSDIS = 0, the master data transfer is enabled.  MSDIS: TWI Master Transfer Disabled 0 = No effect. 1 = The master data transfer is disabled, all pending data is tr ansmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.  SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SWRST – – – MSDIS MSEN STOP START

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.2 TWI Master Mode Register

Register Name:T W I _ M M R Address Type: Read-write  IADRSZ: Internal Device Address Size  MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction.  DADR: Device Address The device address is used to access slave devices in read or write mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –D A D R 15 14 13 12 11 10 9 8 ––– M R E A D –– I A D R S Z 76543210 Table 31-5. IADRSZ[9:8] 0 0 No internal device address (Byte command protocol) 0 1 One-byte internal device address 1 0 Two-byte internal device address 1 1 Three-byte internal device address

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.3 TWI Internal Address Register

Register Name:T W I _ I A D R Access Type: Read-write  IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. – Low significant byte address in 10-bit mode addresses. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IADR 15 14 13 12 11 10 9 8 IADR 76543210 IADR

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.4 TWI Clock Waveform Generator Register

Register Name: TWI_CWGR Access Type: Read-write  CLDIV: Clock Low Divider The SCL low period is defined as follows:  CHDIV: Clock High Divider The SCL high period is defined as follows:  CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHDIV 76543210 CLDIV Tlow CLDIV( 2CKDIV×() 3)+ TMCK×= Thigh CHDIV( 2CKDIV×() 3 )+ TMCK×=

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.5 TWI Status Register

Register Name:T W I _ S R Access Type: Read-only  TXCOMP: Transmission Completed 0 = During the length of the current frame. 1 = When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).  RXRDY: Receive Hold ing Register Ready 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read.  TXRDY: Transmit Holding Register Ready 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).  NACK: Not Acknowledged 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– T X R D Y R X R D Y T X C O M P

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.6 TWI Interrupt Enable Register

Register Name:T W I _ I E R Access Type: Write-only  TXCOMP: Transmission Completed  RXRDY: Receive Hold ing Register Ready  TXRDY: Transmit Holding Register Ready  NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt.

31.7.7 TWI Interrupt Disable Register

Register Name:T W I _ I D R Access Type: Write-only  TXCOMP: Transmission Completed  RXRDY: Receive Hold ing Register Ready  TXRDY: Transmit Holding Register Ready  NACK: Not Acknowledge 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– T X R D Y R X R D Y T X C O M P 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– T X R D Y R X R D Y T X C O M P

6242E–ATARM–11-Sep09 AT91SAM9261S

31.7.8 TWI Interrupt Mask Register

Register Name:T W I _ I M R Access Type: Read-only  TXCOMP: Transmission Completed  RXRDY: Receive Hold ing Register Ready  TXRDY: Transmit Holding Register Ready  NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.

31.7.9 TWI Receive Holding Register

Register Name: TWI_RHR Access Type: Read-only  RXDATA: Receive Holding Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– T X R D Y R X R D Y T X C O M P 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXDATA

6242E–ATARM–11-Sep09 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S 32. Universal Synchronous Asynchronous Receiver Transmitter (USART)

32.1 Overview

The Universal Synchronous Asynchronous Rece iver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitt er timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit han- dling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer manage- ment without any intervention of the processor.

6242E–ATARM–11-Sep09 AT91SAM9261S

32.2 Block Diagram

Figure 32-1. USART Block Diagram Peripheral DMA Controller Channel Channel AIC Receiver USART Interrupt RXD TXD SCK USART PIO Controller CTS RTS Transmitter Baud Rate Generator User Interface PMC MCK SLCK DIV MCK/DIV APB

6242E–ATARM–11-Sep09 AT91SAM9261S

32.3 Application Block Diagram

Figure 32-2. Application Block Diagram Smart Card Slot USART RS485 Drivers Differential Bus IrDA Transceivers Field Bus Driver EMV Driver IrDA Driver IrLAP RS232 Drivers Serial Port Serial Driver PPP

6242E–ATARM–11-Sep09 AT91SAM9261S

32.4 I/O Lines Description

Table 32-1. I/O Line Description Name Description Type Active Level SCK Serial Clock I/O TXD Transmit Serial Data I/O RXD Receive Serial Data Input CTS Clear to Send Input Low RTS Request to Send Output Low

6242E–ATARM–11-Sep09 AT91SAM9261S

32.5 Product Dependencies

32.5.1 I/O Lines

The pins used for interfacing the USART may be multiplexed with the PIO lines. The program- mer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is di sabled, the use of an internal pull up is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also be enabled.

32.5.2 Power Management

The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before usin g the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled.

32.5.3 Interrupt

The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6 Functional Description

The USART is capable of managing several ty pes of serial synchronous or asynchronous communications. It supports the following communication modes:  5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication  High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication  RS485 with driver control signal  ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit  InfraRed IrDA Modulation and Demodulation  Test modes – Remote loopback, local loopback, automatic echo

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.1 Baud Rate Generator

The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between:  the Master Clock MCK  a division of the Master Clock, the divider being product dependent, but generally set to 8  the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal pro- vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 32-3. Baud Rate Generator

32.6.1.1 Baud Rate in Asynchronous Mode

If the USART is programmed to operate in as ynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiv er as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi- ble clock and that OVER is programmed at 1. MCK/DIV 16-bit Counter Baud Rate Clock CD CD Sampling Divider Sampling Clock Reserved MCK SCK USCLKS OVER SCK SYNC SYNC USCLKS = 3 FIDI Baudrate SelectedClock

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.1.2 Baud Rate Calculation Example

Table 32-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. The baud rate is calculated with the following formula: The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.

32.6.1.3 Fractional Baud Rate in Asynchronous Mode

The Baud Rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the Table 32-2. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error MHz Bit/s Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% BaudRate MCK CD 16×⁄= Error 1 ExpectedBaudRate ⎛⎞–=

6242E–ATARM–11-Sep09 AT91SAM9261S clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: The modified architecture is presented below: Figure 32-4. Fractional Baud Rate Generator

32.6.1.4 Baud Rate in Synchronous Mode

If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the inte rnal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.

32.6.1.5 Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula: Baudrate SelectedClock

82 Over–() CD FP

USCLKS = 3 FIDIglitch-free logic Modulus Control FP FP BaudRate SelectedClock B Di

6242E–ATARM–11-Sep09 AT91SAM9261S where:  B is the bit rate  Di is the bit-rate adjustment factor  Fi is the clock frequency division factor  f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 32-3. Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 32-4. Table 32-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. If the USART is configured in ISO7816 Mode, th e clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 32-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Table 32-3. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 D i ( d e c i m a l ) 1 2 4 8 1 63 21 2 2 0 Table 32-4. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 32-5. Possible Values for the Fi/Di Ratio Fi/Di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 32-5. Elementary Time Unit (ETU)

32.6.2 Receiver and Transmitter Control

After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regard- less of what the receiver or the transmitter is performing, the communi cation is immediately stopped. The user can also independently disable the receiv er or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally.

32.6.3 Synchronous and Asynchronous Modes

32.6.3.1 Transmitter Operations

The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 da ta bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US _MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The num- ber of stop bits is selected by the NBSTOP fiel d in US_MR. The 1.5 stop bit is supported in asynchronous mode only.

1 ETU

FI_DI_RATIO ISO7816 Clock Cycles

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 32-6. Character Transmit The characters are sent by writing in the Tran smit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 32-7. Transmitter Status

32.6.3.2 Asynchronous Receiver

If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over- samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL , MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Start Bit Write US_THR D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit TXRDY TXEMPTY

6242E–ATARM–11-Sep09 AT91SAM9261S transmitter can occur. Moreover, as soon as the st op bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 32-8 and Figure 32-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 32-8. Asynchronous Start Detection Figure 32-9. Asynchronous Character Reception

32.6.3.3 Synchronous Receiver

In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 32-10 illustrates a character reception in synchronous mode. Sampling Clock (x16) RXD Start Detection Sampling Baud Rate Clock RXD Start Rejection Sampling 12345678 12345670 1234 12345678 9 1 01 11 21 31 41 51 6 D0 Sampling D0 D1 D2 D3 D4 D5 D6 D7 RXD Parity Bit Stop Bit Example: 8-bit, Parity Enabled Baud Rate Clock Start Detection samples samples samples samples samples samples samples samples samples samples

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 32-10. Synchronous Mode Character Reception

32.6.3.4 Receiver Operations

When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Regist er (US_CSR) rises. If a character is com- pleted while the RXRDY is set, the OVRE (Ove rrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 32-11. Receiver Status D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Sampling Parity Bit Stop Bit Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR RXRDY OVRE D0 D1 D2 D3 D4 D5 D6 D7Start Bit Parity Bit Stop Bit RSTSTA = 1 Read US_RHR

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.3.5 Parity

The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 408. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a num- ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 32-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 32-12 illustrates the parity bit status setting and clearing. Table 32-6. Parity Bit Examples Character Hexa Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 32-12. Parity Error

32.6.3.6 Multidrop Mode

If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is trans mitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at

32.6.3.7 Transmitter Timeguard

The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Regis- ter (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 32-13, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Bad Parity Bit Stop Bit Baud Rate Clock Write US_CR PARE RXRDY RSTSTA = 1

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 32-13. Timeguard Operations Table 32-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate.

32.6.3.8 Receiver Time-out

The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Regist er (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit per iod and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:  Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Start Bit TG = 4 Write US_THR D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit TXRDY TXEMPTY TG = 4 Table 32-7. Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.3.9 Framing Error

The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 32-15. Framing Error Status

32.6.3.10 Transmit Break

The user can request the transmitter to generate a break condition on the TXD line. A break con- dition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 56000 18 1 170 57600 17 1 138 200000 5 328 Table 32-8. Maximum Time-out Period (Continued) Baud Rate Bit Time Time-out D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR FRAME RXRDY RSTSTA = 1

6242E–ATARM–11-Sep09 AT91SAM9261S The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPB RK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 32-16 illustrates the effect of both the Start Break (STTBRK ) and Stop Break (STPBRK) commands on the TXD line. Figure 32-16. Break Transmission

32.6.3.11 Receive Break

The receiver detects a break condition when all data, parity and stop bits are low. This corre- sponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.

32.6.3.12 Hardware Handshaking

The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 32-17. D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR TXRDY TXEMPTY STPBRK = 1STTBRK = 1 Break Transmission End of Break

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.4 ISO7816 Mode

The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T =

32.6.4.1 ISO7816 Mode Overview

The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 399). The USART connects to a smart card as shown in Figure 32-20. The TXD line becomes bidirec- tional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is con- sidered as the master of the communication as it generates the clock. Figure 32-20. Connection of a Smart Card to the USART When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 425 and “PAR: Parity Type” on page 426. The USART cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this for- mat and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR).

32.6.4.2 Protocol T = 0

In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 32-21. Smart Card SCK CLK TXD I/O USART

6242E–ATARM–11-Sep09 AT91SAM9261S If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 32-22. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Reg- ister (US_SR) so that the software can handle the error. Figure 32-21. T = 0 Protocol without Parity Error Figure 32-22. T = 0 Protocol with Parity Error

32.6.4.3 Receive Error Counter

The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field.

32.6.4.4 Receive NACK Inhibit

The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INAC K bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous receiv ed character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise.

32.6.4.5 Transmit Character Repetition

When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the U SART repeats the character as many times as the value loaded in MAX_ITERATION. D0 D1 D2 D3 D4 D5 D6 D7 RXD Parity Bit Baud Rate Clock Start Bit Guard Time 1 Next Start Bit Guard Time 2 D0 D1 D2 D3 D4 D5 D6 D7 I/O Parity Bit Baud Rate Clock Start Bit Guard Time 1 Start Bit Guard Time 2 D0 D1 Error Repetition

6242E–ATARM–11-Sep09 AT91SAM9261S When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1.

32.6.4.6 Disable Successive Receive NACK

The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.

32.6.4.7 Protocol T = 1

When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR).

32.6.5 IrDA Mode

The USART features an IrDA mode supplying half-duplex point-to-point wireless communica- tion. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 32-23. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting t he USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 32-23. Connection to IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals the following needs to be done:  Disable TX and Enable RX IrDA Transceivers RXD RX TXD TX USART Demodulator Modulator Receiver Transmitter

6242E–ATARM–11-Sep09 AT91SAM9261S  Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption).  Receive data

32.6.5.1 IrDA Modulation

For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 32-9. Figure 32-24 shows an example of character transmission. Figure 32-24. IrDA Modulation

32.6.5.2 IrDA Baud Rate

Table 32-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 32-9. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.53 µs 19.2 Kb/s 9.77 µs 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Bit Period Bit Period3 Start Bit Data Bits Stop Bit 0 00 0 01 11 11Transmitter Output TXD Table 32-10. IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.5.3 IrDA Demodulator

The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 32-25 illustrates the operations of the IrDA demodulator. Figure 32-25. IrDA Demodulator Operations As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 Table 32-10. IrDA Baud Rate Error (Continued) Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time MCK RXD Receiver Input Pulse Rejected 65432 6 165432 0 Pulse Accepted Counter Value

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.6 RS485 Mode

The USART features the RS485 mode to enable li ne driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The differenc e is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 32-26. Figure 32-26. Typical Connection to a RS485 Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Regis- ter (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPT Y bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. Figure 32-27 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 32-27. Example of RTS Drive with Timeguard USART RTS TXD RXD Differential Bus D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock TG = 4 Write US_THR TXRDY TXEMPTY RTS

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.7 Test Modes

The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are dis- connected or not and reconfigured for loopback internally or externally.

32.6.7.1 Normal Mode

Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 32-28. Normal Mode Configuration

32.6.7.2 Automatic Echo Mode

Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 32-29. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 32-29. Automatic Echo Mode Configuration

32.6.7.3 Local Loopback Mode

Local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in Figure 32-30. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 32-30. Local Loopback Mode Configuration Receiver Transmitter RXD TXD Receiver Transmitter RXD TXD Receiver Transmitter RXD TXD

6242E–ATARM–11-Sep09 AT91SAM9261S

32.6.7.4 Remote Loopback Mode

Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 32-31. The transmitter and the receiver are disabled an d have no effect. This mode allows bit-by-bit retransmission. Figure 32-31. Remote Loopback Mode Configuration Receiver Transmitter RXD TXD

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7 Universal Synchronous Async hronous Receiver Transmitter (USART) User Interface

Table 32-12. Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read-write – 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only – 0x0018 Receiver Holding Register US_RHR Read-only 0x0 0x001C Transmitter Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read-write 0x0 0x0024 Receiver Time-out Register US_RTOR Read-write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read-write 0x0 0x2C - 0x3C Reserved – – – 0x0040 FI DI Ratio Regist er US_FIDI Read-write 0x174 0x0044 Number of Errors Register US_NER Read-only – 0x0048 Reserved – – – 0x004C IrDA Filter Regi ster US_IF Read-write 0x0 0x5C - 0xFC Reserved – – – 0x100 - 0x128 Reserved for PDC Registers – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.1 USART Control Register

Name: US_CR Addresses: 0xFFFB0000 (0), 0xFFFB4000 (1), 0xFFFB8000 (2) Access Type:Write-only  RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.  RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter.  RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0.  RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver.  TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0.  TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA 76543210 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –

6242E–ATARM–11-Sep09 AT91SAM9261S  RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVREand RXBRK in US_CSR.  STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans- mitted. No effect if a break is already being transmitted.  STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.  STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.  SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.  RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.  RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR.  RETTO: Rearm Time-out 0: No effect 1: Restart Time-out  RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0.  RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1.

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.2 USART Mode Register

Name: US_MR Addresses: 0xFFFB0004 (0), 0xFFFB4004 (1), 0xFFFB8004 (2) Access Type:Read-write  USART_MODE  USCLKS: Clock Selection  CHRL: Character Length. 31 30 29 28 27 26 25 24 – – – FILTER – MAX_ITERATION 23 22 21 20 19 18 17 16 – – DSNACK INACK OVER CLKO MODE9 MSBF 15 14 13 12 11 10 9 8 CHMODE NBSTOP PAR SYNC 76543210 CHRL USCLKS USART_MODE USART_MODE Mode of the USART

0000 N o r m a l

0001 R S 4 8 5

0 0 1 0 Hardware Handshaking 0 1 0 0 IS07816 Protocol: T = 0 0 1 1 0 IS07816 Protocol: T = 1

1000 I r D A

00 M C K

0 1 MCK/DIV (DIV = 8)

10 R e s e r v e d

11 S C K

6242E–ATARM–11-Sep09 AT91SAM9261S  SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.  PAR: Parity Type  NBSTOP: Number of Stop Bits  CHMODE: Channel Mode  MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first.  MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length.  CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. PAR Parity Type 0 0 0 Even parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo. Receiver input is connected to the TXD pin. 1 0 Local Loopback. Transmitter output is connected to the Receiver Input. 1 1 Remote Loopback. RXD pin is internally connected to the TXD pin.

6242E–ATARM–11-Sep09 AT91SAM9261S  OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling.  INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated.  DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value spec ified in the MAX_ITERATION field. These parity errors gener- ate a NACK on the ISO line. As soon as this value is r eached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.  MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0.  FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.3 USART Interrupt Enable Register

Name: US_IER Addresses: 0xFFFB0008 (0), 0xFFFB4008 (1), 0xFFFB8008 (2) Access Type:Write-only  RXRDY: RXRDY Interrupt Enable  TXRDY: TXRDY Interrupt Enable  RXBRK: Receiver Break Interrupt Enable  ENDRX: End of Receive Transfer Interrupt Enable  ENDTX: End of Transmit Interrupt Enable  OVRE: Overrun Error Interrupt Enable  FRAME: Framing Error Interrupt Enable  PARE: Parity Error Interrupt Enable  TIMEOUT: Time-out Interrupt Enable  TXEMPTY: TXEMPTY Interrupt Enable  ITER: Iteration Interrupt Enable  TXBUFE: Buffer Empty Interrupt Enable  RXBUFF: Buffer Full Interrupt Enable  NACK: Non Acknowledge Interrupt Enable  CTSIC: Clear to Send Input Change Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.4 USART Interrupt Disable Register

Name: US_IDR Addresses: 0xFFFB000C (0), 0xFFFB400C (1), 0xFFFB800C (2) Access Type:Write-only  RXRDY: RXRDY Interrupt Disable  TXRDY: TXRDY Interrupt Disable  RXBRK: Receiver Bre ak Interrupt Disable  ENDRX: End of Receive Transfer Interrupt Disable  ENDTX: End of Transmit Interrupt Disable  OVRE: Overrun Error Interrupt Disable  FRAME: Framing Error Interrupt Disable  PARE: Parity Error Interrupt Disable  TIMEOUT: Time-out Interrupt Disable  TXEMPTY: TXEMPTY Interrupt Disable  ITER: Iteration Interrupt Enable  TXBUFE: Buffer Empty Interrupt Disable  RXBUFF: Buffer Full Interrupt Disable  NACK: Non Acknowledge Interrupt Disable  CTSIC: Clear to Send Input Change Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.5 USART Interrupt Mask Register

Name: US_IMR Addresses: 0xFFFB0010 (0), 0xFFFB4010 (1), 0xFFFB8010 (2) Access Type:Read-only  RXRDY: RXRDY Interrupt Mask  TXRDY: TXRDY Interrupt Mask  RXBRK: Receiver Break Interrupt Mask  ENDRX: End of Receive Transfer Interrupt Mask  ENDTX: End of Transmit Interrupt Mask  OVRE: Overrun Error Interrupt Mask  FRAME: Framing Error Interrupt Mask  PARE: Parity Error Interrupt Mask  TIMEOUT: Time-out Interrupt Mask  TXEMPTY: TXEMPTY Interrupt Mask  ITER: Iteration Interrupt Enable  TXBUFE: Buffer Empty Interrupt Mask  RXBUFF: Buffer Full Interrupt Mask  NACK: Non Acknowledge Interrupt Mask  CTSIC: Clear to Send Input Change Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.6 USART Channel Status Register

Name: US_CSR Addresses: 0xFFFB0014 (0), 0xFFFB4014 (1), 0xFFFB8014 (2) Access Type:Read-only  RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read.  TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR.  RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA.  ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active.  ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active.  OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S  FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA.  PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA.  TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).  TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register.  ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA.  TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active.  RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active.  NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK.  CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR.  CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1.

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.7 USART Receive Holding Register

Name: US_RHR Addresses: 0xFFFB0018 (0), 0xFFFB4018 (1), 0xFFFB8018 (2) Access Type:Read-only  RXCHR: Received Character Last character received if RXRDY is set.  RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXCHR

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.8 USART Transmit Holding Register

Name: US_THR Addresses: 0xFFFB001C (0), 0xFFFB401C (1), 0xFFFB801C (2) Access Type:Write-only  TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.  TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXCHR

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.9 USART Baud Rate Generator Register

Name: US_BRGR Addresses: 0xFFFB0020 (0), 0xFFFB4020 (1), 0xFFFB8020 (2) Access Type:Read-write  CD: Clock Divider  FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 76543210 CD CD USART_MODE ≠ ISO7816 USART_MODE = ISO7816 SYNC = 0 SYNC = 1 OVER = 0 OVER = 1

0 Baud Rate Clock Disabled

1 to 65535 Baud Rate = Selected Clock/16/CD Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.10 USART Receiver Time-out Register

Name: US_RTOR Addresses: 0xFFFB0024 (0), 0xFFFB4024 (1), 0xFFFB8024 (2) Access Type:Read-write  TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TO 76543210 TO

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.11 USART Transmitter Timeguard Register

Name: US_TTGR Addresses: 0xFFFB0028 (0), 0xFFFB4028 (1), 0xFFFB8028 (2) Access Type:Read-write  TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TG

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.12 USART FI DI RATIO Register

Name: US_FIDI Addresses: 0xFFFB0040 (0), 0xFFFB4040 (1), 0xFFFB8040 (2) Access Type:Read-write Reset Value: 0x174  FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 FI_DI_RATIO

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.13 USART Number of Errors Register

Name: US_NER Addresses: 0xFFFB0044 (0), 0xFFFB4044 (1), 0xFFFB8044 (2) Access Type:Read-only  NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 NB_ERRORS

6242E–ATARM–11-Sep09 AT91SAM9261S

32.7.14 USART IrDA FILTER Register

Name: US_IF Addresses: 0xFFFB004C (0), 0xFFFB404C (1), 0xFFFB804C (2) Access Type:Read-write  IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 IRDA_FILTER

6242E–ATARM–11-Sep09 AT91SAM9261S 33. Synchronous Serial Controller (SSC)

33.1 Overview

The Atmel Synchronous Serial Controller (SSC ) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be pro- grammed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following:  CODEC’s in master or slave mode  DAC through dedicated serial interface, particularly I2S  Magnetic card reader

6242E–ATARM–11-Sep09 AT91SAM9261S

33.2 Block Diagram

Figure 33-1. Block Diagram

33.3 Application Block Diagram

Figure 33-2. Application Block Diagram SSC Interface PIO PDC APB Bridge MCK System Bus Peripheral Bus TF TK TD RF RK RD Interrupt Control SSC Interrupt PMC Interrupt Management Power Management Test Management SSC Serial AUDIO OS or RTOS Driver Codec Frame Management Line Interface Time Slot Management

6242E–ATARM–11-Sep09 AT91SAM9261S

33.4 Pin Name List

33.5 Product Dependencies

33.5.1 I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO contro ller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.

33.5.2 Power Management

The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock.

33.5.3 Interrupt

The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configur ing the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser- vice routine can get the interrupt origin by reading the SSC interrupt status register.

33.6 Functional Description

This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by pro- gramming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro- grammed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfer s. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. Table 33-1. I/O Lines Description Pin Name Pin Description Type RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 33-3. SSC Functional Block Diagram

33.6.1 Clock Management

The transmitter clock can be generated by:  an external clock received on the TK I/O pad  the receiver clock  the internal clock divider The receiver clock can be generated by:  an external clock received on the RK I/O pad  the transmitter clock  the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. Interrupt Control AIC User Interface APB MCK Receive Clock Controller Start Selector TX Clock RK Input RF TF Clock Output Controller Frame Sync Controller Transmit Clock Controller Transmit Shift RegisterStart Selector Transmit Sync Holding Register Transmit Holding Register Load Shift RX clock TX clockTK Input TF TX PDC RF RD RF RK Clock Output Controller Frame Sync Controller Receive Shift Register Receive Sync Holding Register Receive Holding Register Load Shift TD TF TK RX Clock RX PDC Receiver PDC Transmitter Clock Divider

6242E–ATARM–11-Sep09 AT91SAM9261S

33.6.1.1 Clock Divider

Figure 33-4. Divided Clock Block Diagram The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Mas- ter Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50 % duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 33-5. Divided Clock Generation

33.6.1.2 Transmitter Clock Management

The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transm itter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. Table 33-2. Maximum Minimum MCK / 2 MCK / 8190 MCK Divided Clock Clock Divider / 2 12-bit Counter SSC_CMR Master Clock Divided Clock DIV = 1 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/2 Divided Clock Frequency = MCK/6

6242E–ATARM–11-Sep09 AT91SAM9261S The transmitter can also drive the TK I/O pad continuously or be limited to the actual data trans- fer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredict- able results. Figure 33-6. Transmitter Clock Management

33.6.1.3 Receiver Clock Management

The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. TK (pin) Receiver Clock Divider Clock CKS CKO Data Transfer CKI CKG Transmitter Clock Clock Output MUX Tri_state Controller Tri-state Controller INV MUX

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 33-7. Receiver Clock Management

33.6.1.4 Serial Clock Ratio Considerations

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: – Master Clock divided by 2 if Receiver Frame Synchro is input – Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: – Master Clock divided by 6 if Transmit Frame Synchro is input – Master Clock divided by 2 if Transmit Frame Synchro is output

33.6.2 Transmitter Operations

A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 449. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 451. To transmit data, the transmitter uses a shift re gister clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. RK (pin) Transmitter Clock Divider Clock CKS CKO Data Transfer CKI CKG Receiver Clock Clock Output MUX Tri-state Controller Tri-state Controller INV MUX

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 33-8. Transmitter Block Diagram

33.6.3 Receiver Operations

A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 449. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 451. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the sta- tus flag RXRDY is set in SSC_SR and the data c an be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Transmit Shift RegisterStart Selector SSC_TSHRSSC_THR Transmitter Clock TD SSC_TFMR.FSLENSSC_TFMR.DATLEN SSC_CR.TXEN SSC_CR.TXDIS SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB SSC_SR.TXEN SSC_TFMR.DATDEF SSC_TFMR.MSBF SSC_TCMR.STTDLY SSC_TFMR.FSDEN RF TF

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 33-9. Receiver Block Diagram

33.6.4 Start

The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Sele ction (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable:  Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled.  Synchronously with the transmitter/receiver  On detection of a falling/rising edge on TF/RF  On detection of a low level/high level on TF/RF  On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Receive Shift RegisterStart Selector SSC_RHRSSC_RSHR Receiver Clock RD SSC_RFMR.FSLEN SSC_RFMR.DATLEN RF SSC_CR.RXEN SSC_CR.RXDIS SSC_SR.RXEN SSC_RFMR.MSBF SSC_RCMR.STTDLY SSC_RFMR.DATNBTF

6242E–ATARM–11-Sep09 AT91SAM9261S

33.6.5 Frame Sync

The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.  Programmable low or high levels during data transfer are supported.  Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.

33.6.5.1 Frame Sync Data

Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Trans- mit Register, then shifted out.

33.6.5.2 Frame Sync Edge Detection

The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corres ponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF).

33.6.6 Receive Compare Modes

Figure 33-12. Receive Compare Modes CMP0 CMP3CMP2CMP1 Ignored B0 B2B1 Start RK RD (Input) FSLEN Up to 16 Bits (4 in This Example) STDL Y DATLEN

6242E–ATARM–11-Sep09 AT91SAM9261S

33.6.6.1 Compare Functions

Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR.

33.6.7 Data Format

The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select:  the event that starts the data transfer (START)  the delay in number of bit periods between the start event and the first data bit (STTDL Y)  the length of the data (DATLEN)  the number of data to be transferred for each start event (DATNB).  the length of synchronization transferred for each start event (FSLEN)  the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to tr ansfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.

6242E–ATARM–11-Sep09 AT91SAM9261S Note: 1. STTDL Y is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 33-15. Receive Frame Format in Continuous Mode Note: 1. STTDL Y is set to 0.

33.6.8 Loop Mode

The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.

33.6.9 Interrupt

Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Reg- ister) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Figure 33-16. Interrupt Block Diagram Data DATLEN Data DATLEN Start = Enable Receiver To SSC_RHR To SSC_RHR RD SSC_IMR PDC Interrupt Control SSC Interrupt Set RXRDY OVRUN RXSYNC Receiver Transmitter TXRDY TXEMPTY TXSYNC TXBUFE ENDTX RXBUFF ENDRX Clear SSC_IER SSC_IDR

6242E–ATARM–11-Sep09 AT91SAM9261S

33.7 SSC Application Examples

The SSC can support several serial communica tion modes used in audio or high speed serial links. Some standard applications are shown in t he following figures. All se rial link applications supported by the SSC are not listed here. Figure 33-17. Audio Application Block Diagram Figure 33-18. Codec Application Block Diagram SSC RK RF RD TD TF TK Clock SCK Word Select WS Data SD I2S RECEIVER Clock SCK Word Select WS Data SD Right ChannelLeft Channel MSB MSB LSB SSC RK RF RD TD TF TK Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out Serial Data In CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out Serial Data In First Time Slot Dstart Dend

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 33-19. Time Slot Application Block Diagram SSC RK RF RD TD TF TK SCLK FSYNC Data Out Data in CODEC First Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out Serial Data in CODEC Second Time Slot First Time Slot Second Time Slot Dstart Dend

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8 Synchronous Serial Contro ller (SSC) User Interface

Table 33-4. Register Mapping Offset Register Name Access Reset 0x0 Control Register SSC_CR Write-only – 0x4 Clock Mode Register SSC_CMR Read-write 0x0 0x8 Reserved – – – 0xC Reserved – – – 0x10 Receive Clock Mode Register SSC_RCMR Read-write 0x0 0x14 Receive Frame Mode Register SSC_RFMR Read-write 0x0 0x18 Transmit Clock Mode Register SSC_TCMR Read-write 0x0 0x1C Transmit Frame Mode Register SSC_TFMR Read-write 0x0 0x20 Receive Holding Register SSC_RHR Read-only 0x0 0x24 Transmit Holding Register SSC_THR Write-only – 0x28 Reserved – – – 0x2C Reserved – – – 0x30 Receive Sync. Holding Register SSC_RSHR Read-only 0x0 0x34 Transmit Sync. Holding Register SSC_TSHR Read-write 0x0 0x38 Receive Compare 0 Register SSC_RC0R Read-write 0x0 0x3C Receive Compare 1 Register SSC_RC1R Read-write 0x0 0x40 Status Register SSC_SR Read-only 0x000000CC 0x44 Interrupt Enable Register SSC_IER Write-only – 0x48 Interrupt Disable Register SSC_IDR Write-only – 0x4C Interrupt Mask Register SSC_IMR Read-only 0x0 0x50-0xFC Reserved – – – 0x100- 0x124 Reserved for Peripheral Data Controller (PDC) – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.1 SSC Control Register

Name: SSC_CR Addresses: 0xFFFBC000 (0), 0xFFFC0000 (1), 0xFFFC4000 (2) Access Type:Write-only  RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set.  RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception.  TXEN: Transmit Enable 0 = No effect. 1 = Enables Transmit if TXDIS is not set.  TXDIS: Transmit Disable 0 = No effect. 1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.  SWRST: Software Reset 0 = No effect. 1 = Performs a software reset. Has priority on any other bit in SSC_CR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 S W R S T ––––– T X D I S T X E N 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.2 SSC Clock Mode Register

Name: SSC_CMR Addresses: 0xFFFBC004 (0), 0xFFFC0004 (1), 0xFFFC4004 (2) Access Type:Read-write  DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– D I V 76543210 DIV

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.3 SSC Receive Clock Mode Register

Name: SSC_RCMR Addresses: 0xFFFBC010 (0), 0xFFFC0010 (1), 0xFFFC4010 (2) Access Type:Read-write  CKS: Receive Clock Selection  CKO: Receive Clock Output Mode Selection  CKI: Receive Clock Inversion 0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out- put is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDL Y 15 14 13 12 11 10 9 8 – – – STOP START 76543210 CKG CKI CKO CKS CKS Selected Receive Clock 0x0 Divided Clock 0x1 TK Clock signal 0x2 RK pin 0x3 Reserved CKO Receive Clock Output Mode RK pin 0x0 None Input-only 0x1 Continuous Receive Clock Output 0x2 Receive Clock only during data transfers Output 0x3-0x7 Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S  CKG: Receive Clock Gating Selection  START: Receive Start Selection  STOP: Receive Stop Selection 0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.  STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception.  PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 Transmit start 0x2 Detection of a low level on RF signal 0x3 Detection of a high level on RF signal 0x4 Detection of a falling edge on RF signal 0x5 Detection of a rising edge on RF signal 0x6 Detection of any level change on RF signal 0x7 Detection of any edge on RF signal 0x8 Compare 0 0x9-0xF Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.4 SSC Receive Frame Mode Register

Name: SSC_RFMR Addresses: 0xFFFBC014 (0), 0xFFFC0014 (1), 0xFFFC4014 (2) Access Type:Read-write  DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.  LOOP: Loop Mode 0 = Normal operating mode. 1 = RD is driven by TD, RF is driven by TF and TK drives RK.  MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is sampled first in the bit stream. 1 = The most significant bit of the data register is sampled first in the bit stream.  DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).  FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – FSOS FSLEN 15 14 13 12 11 10 9 8 ––– – D A T N B 765 43210 MSBF – LOOP DATLEN

6242E–ATARM–11-Sep09 AT91SAM9261S  FSOS: Receive Frame Sync Output Selection  FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None Input-only 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Reserved Undefined FSEDGE Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.5 SSC Transmit Clock Mode Register

Name: SSC_TCMR Addresses: 0xFFFBC018 (0), 0xFFFC0018 (1), 0xFFFC4018 (2) Access Type:Read-write  CKS: Transmit Clock Selection  CKO: Transmit Clock Output Mode Selection  CKI: Transmit Clock Inversion 0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDL Y 15 14 13 12 11 10 9 8 –––– S T A R T 76543210 CKG CKI CKO CKS CKS Selected Transmit Clock 0x0 Divided Clock 0x1 RK Clock signal 0x2 TK Pin 0x3 Reserved CKO Transmit Clock Output Mode TK pin 0x0 None Input-only 0x1 Continuous Transmit Clock Output 0x2 Transmit Clock only during data transfers Output 0x3-0x7 Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S  CKG: Transmit Clock Gating Selection  START: Transmit Start Selection  STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit- ted instead of the end of TAG.  PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmi t Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. CKG Transmit Clock Gating 0x0 None, continuous clock 0x1 Transmit Clock enabled only if TF Low 0x2 Transmit Clock enabled only if TF High 0x3 Reserved START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 Receive start 0x2 Detection of a low level on TF signal 0x3 Detection of a high level on TF signal 0x4 Detection of a falling edge on TF signal 0x5 Detection of a rising edge on TF signal 0x6 Detection of any level change on TF signal 0x7 Detection of any edge on TF signal 0x8 - 0xF Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.6 SSC Transmit Frame Mode Register

Name: SSC_TFMR Addresses: 0xFFFBC01C (0), 0xFFFC001C (1), 0xFFFC401C (2) Access Type:Read-write  DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.  DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of tran smission. Note that if the pin is defined as multi-drive by th e PIO Controller, the pin is enabled only if the SCC TD output is 1.  MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is shifted out first in the bit stream. 1 = The most significant bit of the data register is shifted out first in the bit stream.  DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).  FSLEN: Transmit Frame Syn Length This field defines the length of the Transmit Frame Sync sig nal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FSDEN FSOS FSLEN 15 14 13 12 11 10 9 8 ––– – D A T N B 765 4 3210 MSBF – DATDEF DATLEN

6242E–ATARM–11-Sep09 AT91SAM9261S  FSOS: Transmit Frame Sync Output Selection  FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.  FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None Input-only 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Reserved Undefined FSEDGE Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.7 SSC Receive Holding Register

Name: SSC_RHR Addresses: 0xFFFBC020 (0), 0xFFFC0020 (1), 0xFFFC4020 (2) Access Type:Read-only  RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.

33.8.8 SSC Transmit Holding Register

Name: SSC_THR Addresses: 0xFFFBC024 (0), 0xFFFC0024 (1), 0xFFFC4024 (2) Access Type:Write-only  TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 31 30 29 28 27 26 25 24 RDAT 23 22 21 20 19 18 17 16 RDAT 15 14 13 12 11 10 9 8 RDAT 76543210 RDAT 31 30 29 28 27 26 25 24 TDAT 23 22 21 20 19 18 17 16 TDAT 15 14 13 12 11 10 9 8 TDAT 76543210 TDAT

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.9 SSC Receive Synchronization Holding Register

Name: SSC_RSHR Addresses: 0xFFFBC030 (0), 0xFFFC0030 (1), 0xFFFC4030 (2) Access Type:Read-only  RSDAT: Receive Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RSDAT 76543210 RSDAT

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.10 SSC Transmit Synchronization Holding Register

Name: SSC_TSHR Addresses: 0xFFFBC034 (0), 0xFFFC0034 (1), 0xFFFC4034 (2) Access Type:Read-write  TSDAT: Transmit Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TSDAT 76543210 TSDAT

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.11 SSC Receive Compare 0 Register

Name: SSC_RC0R Addresses: 0xFFFBC038 (0), 0xFFFC0038 (1), 0xFFFC4038 (2) Access Type:Read-write  CP0: Receive Compare Data 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CP0 76543210 CP0

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.12 SSC Receive Compare 1 Register

Name: SSC_RC1R Addresses: 0xFFFBC03C (0), 0xFFFC003C (1), 0xFFFC403C (2) Access Type:Read-write  CP1: Receive Compare Data 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CP1 76543210 CP1

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.13 SSC Status Register

Name: SSC_SR Addresses: 0xFFFBC040 (0), 0xFFFC0040 (1), 0xFFFC4040 (2) Access Type:Read-only  TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.  TXEMPTY: Transmit Empty 0 = Data remains in SSC_THR or is currently transmitted from TSR. 1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.  ENDTX: End of Transmission 0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.  TXBUFE: Transmit Buffer Empty 0 = SSC_TCR or SSC_TNCR have a value other than 0. 1 = Both SSC_TCR and SSC_TNCR have a value of 0.  RXRDY: Receive Ready 0 = SSC_RHR is empty. 1 = Data has been received and loaded in SSC_RHR.  OVRUN: Receive Overrun 0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.  ENDRX: End of Reception 0 = Data is written on the Receive Counter Register or Receive Next Counter Register. 1 = End of PDC transfer when Receive Counter Register has arrived at zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– R X S Y N T XSYN CP1 CP0 76543210 RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S  RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. C P 0 : C o m p a r e 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. C P 1 : C o m p a r e 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register.  TXSYN: Transmit Sync 0 = A Tx Sync has not occurred since the last read of the Status Register. 1 = A Tx Sync has occurred since the last read of the Status Register.  RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register.  TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled.  RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled.

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.14 SSC Interrupt Enable Register

Name: SSC_IER Addresses: 0xFFFBC044 (0), 0xFFFC0044 (1), 0xFFFC4044 (2) Access Type:Write-only  TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt.  TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.  ENDTX: End of Transmission Interrupt Enable 0 = No effect. 1 = Enables the End of Transmission Interrupt.  TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Buffer Empty Interrupt  RXRDY: Receive Ready Interrupt Enable 0 = No effect. 1 = Enables the Receive Ready Interrupt.  OVRUN: Receive Overrun Interrupt Enable 0 = No effect. 1 = Enables the Receive Overrun Interrupt.  ENDRX: End of Reception Interrupt Enable 0 = No effect. 1 = Enables the End of Reception Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– R X S Y N T XSYN CP1 CP0 76543210 RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S  RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt.  CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt.  CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt.  TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt.  RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt.

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.15 SSC Interrupt Disable Register

Name: SSC_IDR Addresses: 0xFFFBC048 (0), 0xFFFC0048 (1), 0xFFFC4048 (2) Access Type:Write-only  TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt.  TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.  ENDTX: End of Transmission Interrupt Disable 0 = No effect. 1 = Disables the End of Transmission Interrupt.  TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Buffer Empty Interrupt.  RXRDY: Receive Ready Interrupt Disable 0 = No effect. 1 = Disables the Receive Ready Interrupt.  OVRUN: Receive Overrun Interrupt Disable 0 = No effect. 1 = Disables the Receive Overrun Interrupt.  ENDRX: End of Reception Interrupt Disable 0 = No effect. 1 = Disables the End of Reception Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– R X S Y N T XSYN CP1 CP0 76543210 RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S  RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt.  CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt.  CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt.  TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt.  RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt.

6242E–ATARM–11-Sep09 AT91SAM9261S

33.8.16 SSC Interrupt Mask Register

Name: SSC_IMR Addresses: 0xFFFBC04C (0), 0xFFFC004C (1), 0xFFFC404C (2) Access Type:Read-only  TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.  TXEMPTY: Transmit Empty Interrupt Mask 0 = The Transmit Empty Interrupt is disabled. 1 = The Transmit Empty Interrupt is enabled.  ENDTX: End of Transmission Interrupt Mask 0 = The End of Transmission Interrupt is disabled. 1 = The End of Transmission Interrupt is enabled.  TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The Transmit Buffer Empty Interrupt is disabled. 1 = The Transmit Buffer Empty Interrupt is enabled.  RXRDY: Receive Ready Interrupt Mask 0 = The Receive Ready Interrupt is disabled. 1 = The Receive Ready Interrupt is enabled.  OVRUN: Receive Overrun Interrupt Mask 0 = The Receive Overrun Interrupt is disabled. 1 = The Receive Overrun Interrupt is enabled.  ENDRX: End of Reception Interrupt Mask 0 = The End of Reception Interrupt is disabled. 1 = The End of Reception Interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– R X S Y N T XSYN CP1 CP0 76543210 RXBUF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY

6242E–ATARM–11-Sep09 AT91SAM9261S  RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled.  CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled.  CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled.  TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled.  RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled.

6242E–ATARM–11-Sep09 AT91SAM9261S 34. Timer Counter (TC)

34.1 Overview

The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 34-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2 Table 34-1. Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 SLCK

6242E–ATARM–11-Sep09 AT91SAM9261S

34.2 Block Diagram

Figure 34-1. Timer Counter Block Diagram Timer/Counter Channel 0 Timer/Counter Channel 1 Timer/Counter Channel 2 SYNC Parallel I/O Controller TC1XC1S TC0XC0S TC2XC2S INT0 INT1 INT2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA0 TIOA1 Advanced Interrupt Controller TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Timer Counter TIOA TIOB TIOA TIOB TIOA TIOB SYNC SYNC TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 TIMER_CLOCK1 Table 34-2. Signal Name Description Block/Channel Signal Name Description Channel Signal XC0, XC1, XC2 External Clock Inputs TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT Interrupt Signal Output SYNC Synchronization Input Signal

6242E–ATARM–11-Sep09 AT91SAM9261S

34.3 Pin Name List

34.4 Product Dependencies

34.4.1 I/O Lines

The pins used for interfacing the compliant ex ternal devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions.

34.4.2 Power Management

The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock.

34.4.3 Interrupt

The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. Table 34-3. TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O

6242E–ATARM–11-Sep09 AT91SAM9261S

34.5 Functional Description

34.5.1 TC Description

The three channels of the Timer Counter are independent and identical in operation. The regis- ters for channel programming are listed in Table 34-4 on page 497. 34.5.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Regis- ter, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.

34.5.3 Clock Selection

At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to t he internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 34-2 on page 485. Each channel can independently select an internal or external clock source for its counter:  Internal clock signals: TIMER_CL OCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5  External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validat ed when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 34-3 on page 485 Note: In all cases, if an external clock is used, the du ration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the mas- ter clock

6242E–ATARM–11-Sep09 AT91SAM9261S

34.5.4 Clock Control

The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 34-4.  The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.  The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 34-4. Clock Control

34.5.5 TC Operating Modes

Each channel can independently operate in two different modes:  Capture Mode provides measurement on signals.  Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.

34.5.6 Trigger

A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: QS R S R Q CLKSTA CLKEN CLKDIS Stop Event Disable EventCounter Clock Selected Clock Trigger

6242E–ATARM–11-Sep09 AT91SAM9261S  Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.  SYNC: Each channel has a synchronization si gnal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.  Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.

34.5.7 Capture Operating Mode

This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on TIOA and TIOB sig nals which are considered as inputs. Figure 34-5 shows the configuration of the TC channel when programmed in Capture Mode.

34.5.8 Capture Registers A and B

Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.

34.5.9 Trigger Conditions

In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trig- ger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the ed ge (rising, falling or both) det ected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 34-5. Capture Mode TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 TCCLKS CLKI QS R S R Q CLKSTA CLKEN CLKDIS BURST TIOB Register C Capture Register A Capture Register B Compare RC = 16-bit Counter ABETRG SWTRG ETRGEDG CPCTRG TC1_IMR Trig LDRBS LDRAS ETRGS TC1_SR LOVRS COVFS SYNC MTIOB TIOA MTIOA LDRA LDBSTOP If RA is not loaded or RB is Loaded If RA is Loaded LDBDIS CPCS INT Edge Detector Edge Detector LDRB Edge Detector CLK OVF RESET Timer/Counter Channel

6242E–ATARM–11-Sep09 AT91SAM9261S

34.5.10 Waveform Operating Mode

Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 34-6 shows the configuration of the TC channel when programmed in Waveform Operat- ing Mode.

34.5.11 Waveform Selection

Depending on the WAVSEL parameter in TC_C MR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 34-6. Waveform Mode TCCLKS CLKI QS R S R Q CLKSTA CLKEN CLKDIS CPCDIS BURST TIOB Register A Register B Register C Compare RA = Compare RB = Compare RC = CPCSTOP 16-bit Counter EEVT EEVTEDG SYNC SWTRG ENETRG WAVSEL TC1_IMR Trig ACPC ACPA AEEVT ASWTRG BCPC BCPB BEEVT BSWTRG TIOA MTIOA TIOB MTIOB CPAS COVFS ETRGS TC1_SR CPCS CPBS CLK OVFRESET Output Controller Output Controller INT Edge Detector Timer/Counter Channel TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 WAVSEL

6242E–ATARM–11-Sep09 AT91SAM9261S

34.5.11.1 WAVSEL = 00

When WAVSEL = 00, the value of TC_CV is incr emented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 34-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 34-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 34-7. WAVSEL= 00 without trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Examples

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 34-8. WAVSEL= 00 with trigger

34.5.11.2 WAVSEL = 10

When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then auto- matically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 34-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 34-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 34-9. WAVSEL = 10 Without Trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Examples Counter cleared by trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 34-10. WAVSEL = 10 With Trigger

34.5.11.3 WAVSEL = 01

When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 34-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trig- ger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples Counter cleared by trigger

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 34-11. WAVSEL = 01 Without Trigger Figure 34-12. WAVSEL = 01 With Trigger

34.5.11.4 WAVSEL = 11

When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 34-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trig- ger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPC- DIS = 1). Time Counter Value RC RB RA TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples Time Counter Value TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples Counter decremented by trigger Counter incremented by trigger RC RB RA

6242E–ATARM–11-Sep09 AT91SAM9261S

34.5.12 External Event/Trigger Conditions

An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL.

34.5.13 Output Controller

The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6 Timer Counter (TC) User Interface

Notes: 1. Channel index ranges from 0 to 2. 2. Read-only if WAVE = 0 Table 34-4. Register Mapping Offset(1) Register Name Access Reset 0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only – 0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read-write 0 0x00 + channel * 0x40 + 0x08 Reserved 0x00 + channel * 0x40 + 0x0C Reserved 0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0 0x00 + channel * 0x40 + 0x14 Register A TC_RA Read-write (2) 0 0x00 + channel * 0x40 + 0x18 Register B TC_RB Read-write (2) 0 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read-write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read-write 0 0xFC Reserved – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.1 TC Block Control Register

Register Name:TC_BCR Address: 0xFFFA00C0 Access Type:Write-only  SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.2 TC Block Mode Register

Register Name:TC_BMR Address: 0xFFFA00C4 Access Type:Read-write  TC0XC0S: External Clock Signal 0 Selection  TC1XC1S: External Clock Signal 1 Selection  TC2XC2S: External Clock Signal 2 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – TC2XC2S TC1XC1S TC0XC0S TC0XC0S Signal Connected to XC0

00 T C L K 0

10 T I O A 1

11 T I O A 2

TC1XC1S Signal Connected to XC1

00 T C L K 1

10 T I O A 0

TC2XC2S Signal Connected to XC2

00 T C L K 2

11 T I O A 1

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.3 TC Channel Control Register

Register Name:TC_CCRx [x=0..2] Addresses: 0xFFFA0000 (0)[0], 0xFFFA0040 (0)[1], 0xFFFA0080 (0)[2] Access Type:Write-only  CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.  CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.  SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– S W T R G C L K D I S C L K E N

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.4 TC Channel Mode Register: Capture Mode

Register Name:TC_CMRx [x=0..2] (WAVE = 0) Addresses: 0xFFFA0004 (0)[0], 0xFFFA0044 (0)[1], 0xFFFA0084 (0)[2] Access Type:Read-write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – – LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG – – – ABETRG ETRGEDG 76543210 LDBDIS LDBSTOP BURST CLKI TCCLKS TCCLKS Clock Selected 0 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5

101 X C 0

110 X C 1

111 X C 2

0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock.

6242E–ATARM–11-Sep09 AT91SAM9261S  LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs.  ETRGEDG: External Trigger Edge Selection  ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. W A V E 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled).  LDRA: RA Loading Selection  LDRB: RB Loading Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge LDRA Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA LDRB Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.5 TC Channel Mode Register: Waveform Mode

Register Name:TC_CMRx [x=0..2] (WAVE = 1) Addresses: 0xFFFA0004 (0)[0], 0xFFFA0044 (0)[1], 0xFFFA0084 (0)[2] Access Type:Read-write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE WAVSEL ENETRG EEVT EEVTEDG 76543210 CPCDIS CPCSTOP BURST CLKI TCCLKS TCCLKS Clock Selected 0 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock.

6242E–ATARM–11-Sep09 AT91SAM9261S  CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC.  EEVTEDG: External Ev ent Edge Selection  EEVT: External Event Selection Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse- quently no IRQs.  ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock.  WAVSEL: Waveform Selection W A V E 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge EEVT Signal selected as exte rnal event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output WAVSEL Effect 0 0 UP mode without automatic trigger on RC Compare 1 0 UP mode with automatic trigger on RC Compare 0 1 UPDOWN mode without automat ic trigger on RC Compare 1 1 UPDOWN mode with automatic trigger on RC Compare

6242E–ATARM–11-Sep09 AT91SAM9261S  ACPA: RA Compare Effect on TIOA  ACPC: RC Compare Effect on TIOA  AEEVT: External Event Effect on TIOA  ASWTRG: Software Trigger Effect on TIOA  BCPB: RB Compare Effect on TIOB ACPA Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle AEEVT Effect 0 0 none 0 1 set 1 0 clear 11 t o g g l e ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPB Effect 0 0 none 0 1 set 1 0 clear 11 t o g g l e

6242E–ATARM–11-Sep09 AT91SAM9261S  BCPC: RC Compare Effect on TIOB  BEEVT: External Event Effect on TIOB  BSWTRG: Software Trigger Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BSWTRG Effect 0 0 none 01 s e t 1 0 clear 11 t o g g l e

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.6 TC Counter Value Register

Register Name:TC_CVx [x=0..2] Addresses: 0xFFFA0010 (0)[0], 0xFFFA0050 (0)[1], 0xFFFA0090 (0)[2] Access Type:Read-only  CV: Counter Value CV contains the counter value in real time.

34.6.7 TC Register A

Register Name:TC_RAx [x=0..2] Addresses: 0xFFFA0014 (0)[0], 0xFFFA0054 (0)[1], 0xFFFA0094 (0)[2] Access Type:Read-only if WAVE = 0, Read-write if WAVE = 1  RA: Register A RA contains the Register A value in real time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CV 76543210 CV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RA 76543210 RA

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.8 TC Register B

Register Name:TC_RBx [x=0..2] Addresses: 0xFFFA0018 (0)[0], 0xFFFA0058 (0)[1], 0xFFFA0098 (0)[2] Access Type:Read-only if WAVE = 0, Read-write if WAVE = 1  RB: Register B RB contains the Register B value in real time.

34.6.9 TC Register C

Register Name:TC_RCx [x=0..2] Addresses: 0xFFFA001C (0)[0], 0xFFFA005C (0)[1], 0xFFFA009C (0)[2] Access Type:Read-write  RC: Register C RC contains the Register C value in real time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RB 76543210 RB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RC 76543210 RC

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.10 TC Status Register

Register Name:TC_SRx [x=0..2] Addresses: 0xFFFA0020 (0)[0], 0xFFFA0060 (0)[1], 0xFFFA00A0 (0)[2] Access Type:Read-only  COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.  LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta- tus Register, if WAVE = 0.  CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.  CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.  CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.  LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.  LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– M T I O B M T I O A C L K S T A 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

6242E–ATARM–11-Sep09 AT91SAM9261S  ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.  CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled.  MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.  MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.11 TC Interrupt Enable Register

Register Name:TC_IERx [x=0..2] Addresses: 0xFFFA0024 (0)[0], 0xFFFA0064 (0)[1], 0xFFFA00A4 (0)[2] Access Type:Write-only  COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt.  LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt.  CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt.  CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt.  CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt.  LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt.  LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt.  ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.12 TC Interrupt Disable Register

Register Name:TC_IDRx [x=0..2] Addresses: 0xFFFA0028 (0)[0], 0xFFFA0068 (0)[1], 0xFFFA00A8 (0)[2] Access Type:Write-only  COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt.  LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0).  CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1).  CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1).  CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt.  LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0).  LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

6242E–ATARM–11-Sep09 AT91SAM9261S  ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt.

6242E–ATARM–11-Sep09 AT91SAM9261S

34.6.13 TC Interrupt Mask Register

Register Name:TC_IMRx [x=0..2] Addresses: 0xFFFA002C (0)[0], 0xFFFA006C (0)[1], 0xFFFA00AC (0)[2] Access Type:Read-only  COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled.  LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled.  CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled.  CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled.  CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled.  LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled.  LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled.  ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

6242E–ATARM–11-Sep09 AT91SAM9261S 35. MultiMedia Card Interface (MCI)

35.1 Overview

The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V2.2 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimi zing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Cloc k divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology.

6242E–ATARM–11-Sep09 AT91SAM9261S

35.2 Block Diagram

Figure 35-1. Block Diagram Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy.

35.3 Application Block Diagram

Figure 35-2. Application Block Diagram MCDA3 (1) MCDA2 (1) MCDA1 (1) MCDA0 (1) MCCDA (1) MCCK (1) MCI Interface Interrupt Control PDC MCI Interrupt PIO APB Bridge PMC MCK APB 2345617 MMC 2345617 8 SDCard Physical Layer MCI Interface Application Layer ex: File System, Audio, Security, etc.

6242E–ATARM–11-Sep09 AT91SAM9261S

35.4 Pin Name List

Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy.

35.5 Product Dependencies

35.5.1 I/O Lines

The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins.

35.5.2 Power Management

The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock.

35.5.3 Interrupt

The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI.

35.6 Bus Topology

Figure 35-3. Multimedia Memory Card Bus Topology The MultiMedia Card communication is based on a 7- pin serial bus interface. It has three com- munication lines and four supply lines. Table 35-1. I/O Lines Description Pin Name(2) Pin Description Type (1) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard MCCK Clock I/O CLK of an MMC or SD Card MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT0 of an MMC DAT[0..3] of an SD Card Table 35-2. Bus Topology Pin Number Name Type (1) Description MCI Pin Name(2) (Slot z)

1 RSV NC Not connected -

2 CMD I/O/PP/OD Command/response MCCDz

3 VSS1 S Supply voltage ground VSS

4 VDD S Supply voltage VDD

6242E–ATARM–11-Sep09 AT91SAM9261S Notes: 1. I: Input, O: Output, PP : Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Figure 35-4. MMC Bus Connections (One Slot) Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 35-5. SD Memory Card Bus Topology The SD Memory Card bus includes the signals listed in Table 35-3.

5 CLK I/O Clock MCCK

6 VSS2 S Supply voltage ground VSS

7 DAT[0] I/O/PP Data 0 MCDz0

Table 35-3. SD Memory Card Bus Signals Pin Number Name Type (1) Description MCI Pin Name(2) (Slot z)

1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3

2 CMD PP Command/response MCCDz

Table 35-2. Bus Topology (Continued) Pin Number Name Type (1) Description MCI Pin Name(2) (Slot z) 234561 7 23456 1 7 23456 17 MCCDA MCDA0 MCCK MMC1 MMC2 MMC3 MCI 2345617 8 SD CARD

6242E–ATARM–11-Sep09 AT91SAM9261S Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Figure 35-6. SD Card Bus Connections with One Slot Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs.

35.7 MultiMedia Card Operations

After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens:  Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.  Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.  Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a sess ion address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, resp onses and data blocks is descr ibed in the MultiMedia-Card System Specification. See also Table 35-4 on page 520. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their infor- mation directly within the command or response structure. In this case, no data token is present

7 DAT[0] I/O/PP Data line Bit 0 MCDz0

8 DAT[1] I/O/PP Data line Bit 1 MCDz1

9 DAT[2] I/O/PP Data line Bit 2 MCDz2

Table 35-3. SD Memory Card Bus Signals (Continued) Pin Number Name Type (1) Description MCI Pin Name(2) (Slot z) 2345617 MCDA0 - MCDA3 MCCDA MCCK SD CARD9

6242E–ATARM–11-Sep09 AT91SAM9261S in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined:  Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.  Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop co mmand follows on the CMD line similarly to the sequential read. The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.

35.7.1 Command - Response Operation

After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 35-4 and Table 35-5. Note: bcr means broadcast command with response. Host Command N ID Cycles CID CMD S T Content CRC E Z ****** Z S T Content Z Z Z Table 35-4. ALL_SEND_CID Command Description CMD Index Type Argument Resp Abbreviation Command

Description

CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Table 35-5. Fields and Values for MCI_CMDR Command Register Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1

6242E–ATARM–11-Sep09 AT91SAM9261S The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps:  Fill the argument register (MCI_ARGR) with the command argument.  Set the command register (MCI_CMDR) (see Table 35-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is assert ed when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) Table 35-5. Fields and Values for MCI_CMDR Command Register (Continued) Field Value

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 35-7. Command/Response Functional Flow Diagram Note: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification).

35.7.2 Data Transfer Operation

The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined in the mode register MCI_MR. This field determines the size of the data block.

35.7.3 Read Operation

The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 35-8) , a polling method is used to wait for the end of read. Similarly, RETURN OK RETURN ERROR(1) Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR CMDRDY Status error flags? Read response if required Ye s Wait for command ready status flag Check error bits in the status register (1)

6242E–ATARM–11-Sep09 AT91SAM9261S the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. Figure 35-8. Read Functional Flow Diagram Note: It is assumed that this command has been correctly sent (see Figure 35-7). Read status register MCI_SR Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) Read with PDC Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16) Number of words to read = 0 ? Poll the bit RXRDY = 0? Read data = MCI_RDR Number of words to read = Number of words to read -1 Send READ_SINGLE_BLOCK command(1) Yes Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLength << 16) Configure the PDC channel MCI_RPR = Data Buffer Address MCI_RCR = BlockLength/4 MCI_PTCR = RXTEN Send READ_SINGLE_BLOCK command(1) Read status register MCI_SR Poll the bit ENDRX = 0? Yes RETURN RETURN YesNo No No Yes No Number of words to read = BlockLength/4

6242E–ATARM–11-Sep09 AT91SAM9261S

35.7.4 Write Operation

In write operation, the MCI Mode Register (MC I_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPAD V is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart shows how to write a singl e block with or without use of PDC facilities (see Figure 35-9) . Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR).

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 35-9. Write Functional Flow Diagram Note: It is assumed that this command has been correctly sent (see Figure 35-7). Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) Write using PDC Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length MCI_MR |= (BlockLenght <<16) Send WRITE_SINGLE_BLOCK command(1) Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length MCI_MR |= (BlockLength << 16) Configure the PDC channel MCI_TPR = Data Buffer Address to write MCI_TCR = BlockLength/4 Send WRITE_SINGLE_BLOCK command(1) Read status register MCI_SR Poll the bit NOTBUSY= 0? Yes RETURN No Yes No Read status register MCI_SR Number of words to write = 0 ? Poll the bit TXRDY = 0? MCI_TDR = Data to write Number of words to write = Number of words to write -1 Yes RETURN No Yes No Number of words to write = BlockLength/4 MCI_PTCR = TXTEN

6242E–ATARM–11-Sep09 AT91SAM9261S

35.8 SD Card Operations

The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) Card commands. SD cards are based on the Multi Media Card (MMC ) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MultiMedia Card with some additions.SD is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association. The SD Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The communication protocol is defined as a part of this specification. The main dif- ference between the SD Card and the MultiMedia Card is the initialization process. The SD Card Register (MCI_SDCR) allows selection of the Card Slot and the data bus width. The SD Card bus allows dynamic configuration of the number of data lines. After power up, by default, the SD Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines).

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9 MultiMedia Card Inte rface (MCI) User Interface

Note: 1. The response register can be read by N accesses at th e same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. Table 35-6. Register Mapping Offset Register Register Name Access Reset 0x00 Control Register MCI_CR Write-only – 0x04 Mode Register MCI_MR Read-write 0x0 0x08 Data Timeout Register MCI_DTOR Read-write 0x0 0x0C SD Card Register MCI_SDCR Read-write 0x0 0x10 Argument Register MCI_ARGR Read-write 0x0 0x14 Command Register MCI_CMDR Write-only – 0x18 - 0x1C Reserved – – – 0x20 Response Register (1) MCI_RSPR Read-only 0x0 0x24 Response Register (1) MCI_RSPR Read-only 0x0 0x28 Response Register (1) MCI_RSPR Read-only 0x0 0x2C Response Register (1) MCI_RSPR Read-only 0x0 0x30 Receive Data Register MCI_RDR Read-only 0x0 0x34 Transmit Data Register MCI_TDR Write-only – 0x38 - 0x3C Reserved – – – 0x40 Status Register MCI_SR Read-only 0xC0E5 0x44 Interrupt Enable Register MCI_IER Write-only – 0x48 Interrupt Disable Register MCI_IDR Write-only – 0x4C Interrupt Mask Register MCI_IMR Read-only 0x0 0x50-0xFC Reserved – – – 0x100-0x124 Reserved for the PDC – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.1 MCI Control Register

Name: MCI_CR Address: 0xFFFA8000 Access Type: Write-only  MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0.  MCIDIS: Multi-Media Interface Disable 0 = No effect. 1 = Disables the Multi-Media Interface.  PWSEN: Power Save Mode Enable 0 = No effect. 1 = Enables the Power Saving Mode if PWSDIS is 0. Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field (Mode Register MCI_MR).  PWSDIS: Power Save Mode Disable 0 = No effect. 1 = Disables the Power Saving Mode.  SWRST: Software Reset 0 = No effect. 1 = Resets the MCI. A software triggered hardware reset of the MCI interface is performed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SWRST – – – PWSDIS PWSEN MCIDIS MCIEN

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.2 MCI Mode Register

Name: MCI_MR Address: 0xFFFA8004 Access Type: Read/write  CLKDIV: Clock Divider Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).  PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from 0 before enabling the Power Save Mode in the MCI_CR (MCI_PWSEN bit).  PDCPADV: PDC Padding Value 0 = 0x00 value is used when padding data in write transfer (not only PDC transfer). 1 = 0xFF value is used when padding data in write transfer (not only PDC transfer).  PDCMODE: PDC-oriented Mode 0 = Disables PDC transfer 1 = Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer has been completed.  BLKLEN: Data Block Length This field determines the size of the data block. Bits 16 and 17 must be set to 0 31 30 29 28 27 26 25 24 – – BLKLEN 23 22 21 20 19 18 17 16 BLKLEN 0 0 15 14 13 12 11 10 9 8 PDCMODE PDCPADV – – – PWSDIV 76543210 CLKDIV

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.3 MCI Data Timeout Register

Name: MCI_DTOR Address: 0xFFFA8008 Access Type: Read/write  DTOCYC: Data Timeout Cycle Number Defines a number of Master Clock cycles with DTOMUL.  DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the MCI waits between two data block transfers. It equals (DTOCYC x Multiplier). Multiplier is defined by DTOMUL as shown in the following table: If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the MCI Status Register (MCI_SR) raises. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – DTOMUL DTOCYC DTOMUL Multiplier 000 1 001 1 6 010 1 2 8 011 2 5 6 1 0 0 1024 1 0 1 4096 1 1 0 65536 1 1 1 1048576

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.4 MCI SDCard Register

Name: MCI_SDCR Address: 0xFFFA800C Access Type: Read/write  SDCSEL: SDCard Slot  SDCBUS: SDCard Bus Width 0 = 1-bit data bus 1 = 4-bit data bus 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 S D C B U S ––––– S D C S E L SDCSEL SDCard Slot 00 Slot A is selected.

01 Reserved

11 Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.5 MCI Argument Register

Name: MCI_ARGR Address: 0xFFFA8010 Access Type: Read/write  ARG: Command Argument 31 30 29 28 27 26 25 24 ARG 23 22 21 20 19 18 17 16 ARG 15 14 13 12 11 10 9 8 ARG 76543210 ARG

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.6 MCI Command Register

Name: MCI_CMDR Address: 0xFFFA8014 Access Type: Write-only This register is write-protected while CMDRDY is 0 in MCI_SR. If an Interrupt command is sen t, this register is only write- able by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.  CMDNB: Command Number MultiMedia Card bus command numbers are defined in the MultiMedia Card specification.  RSPTYP: Response Type  SPCMD: Special Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – TRTYP TRDIR TRCMD 15 14 13 12 11 10 9 8 – – – MAXLAT OPDCMD SPCMD 76543210 RSPTYP CMDNB RSP Response Type 0 0 No response. 0 1 48-bit response. 1 0 136-bit response. 1 1 Reserved. SPCMD Command 0 0 0 Not a special CMD.

001 Initialization CMD:

74 clock cycles for initialization sequence. 010 Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 011 R e s e r v e d .

100 Interrupt command:

Corresponds to the Interrupt Mode (CMD40).

101 Interrupt response:

Corresponds to the Interrupt Mode (CMD40).

6242E–ATARM–11-Sep09 AT91SAM9261S  OPDCMD: Open Drain Command 0 = Push pull command 1 = Open drain command  MAXLAT: Max Latency for Command to Response 0 = 5-cycle max latency 1 = 64-cycle max latency  TRCMD: Transfer Command  TRDIR: Transfer Direction 0 = Write 1 = Read  TRTYP: Transfer Type TRCMD Transfer Type 0 0 No data transfer 0 1 Start data transfer 1 0 Stop data transfer 0 0 0 MMC/SDCard Single Block 0 0 1 MMC/SDCard Multiple Block

010 M M C S t r e a m

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.7 MCI Response Register

Name: MCI_RSPR Address: 0xFFFA8020 Access Type: Read-only  RSP: Response Note: The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. 31 30 29 28 27 26 25 24 RSP 23 22 21 20 19 18 17 16 RSP 15 14 13 12 11 10 9 8 RSP 76543210 RSP

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.8 MCI Receive Data Register

Name: MCI_RDR Address: 0xFFFA8030 Access Type: Read-only  DATA: Data to Read 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 76543210 DATA

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.9 MCI Transmit Data Register

Name: MCI_TDR Address: 0xFFFA8034 Access Type: Write-only  DATA: Data to Write 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 76543210 DATA

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.10 MCI Status Register

Name: MCI_SR Address: 0xFFFA8040 Access Type: Read-only  CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent. Cleared when writing in the MCI_CMDR.  RXRDY: Receiver Ready 0 = Data has not yet been received since the last read of MCI_RDR. 1 = Data has been received since the last read of MCI_RDR.  TXRDY: Transmit Ready 0= The last data written in MCI_TDR has not yet been transferred in the Shift Register. 1= The last data written in MCI_TDR has been transferred in the Shift Register.  BLKE: Data Block Ended This flag must be used only for Write Operations. 0 = A data block transfer is not yet finished. Cleared when reading the MCI_SR. 1 = A data block transfer has ended, including the CRC16 Status transmission. In PDC mode (PDCMODE=1), the flag is set when the CRC Status of the last block has been transmitted (TXBUFE already set). Otherwise (PDCMODE=0), the flag is set for each transmitted CRC Status. Refer to the MMC or SD Specification for more details concerning the CRC Status.  DTIP: Data Transfer in Progress 0 = No data transfer in progress. 1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.  NOTBUSY: MCI Not Busy This flag must be used only for Write Operations. A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 T X B U F E R X B U F F –––––– 76543210 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

6242E–ATARM–11-Sep09 AT91SAM9261S The NOTBUSY flag allows to deal with these different states. 0 = The MCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The MCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior.  ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in MCI_RCR or MCI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in MCI_RCR or MCI_RNCR.  ENDTX: End of TX Buffer 0 = The Transmit Counter Register has not reached 0 since the last write in MCI_TCR or MCI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in MCI_TCR or MCI_TNCR. Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller.  RXBUFF: RX Buffer Full 0 = MCI_RCR or MCI_RNCR has a value other than 0. 1 = Both MCI_RCR and MCI_RNCR have a value of 0.  TXBUFE: TX Buffer Empty 0 = MCI_TCR or MCI_TNCR has a value other than 0. 1 = Both MCI_TCR and MCI_TNCR have a value of 0. Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller.  RINDE: Response Index Error 0 = No error. 1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the MCI_CMDR.  RDIRE: Response Direction Error 0 = No error. 1 = The direction bit from card to host in the response has not been detected.  RCRCE: Response CRC Error 0 = No error. 1 = A CRC7 error has been detected in the response. Cleared when writing in the MCI_CMDR.  RENDE: Response End Bit Error 0 = No error. 1 = The end bit of the response has not been detected. Cleared when writing in the MCI_CMDR.

6242E–ATARM–11-Sep09 AT91SAM9261S  RTOE: Response Time-out Error 0 = No error. 1 = The response time-out set by MAXLAT in the MCI_CMDR has been exceeded. Cleared when writing in the MCI_CMDR.  DCRCE: Data CRC Error 0 = No error. 1 = A CRC16 error has been detected in the last data block. Cleared by reading in the MCI_SR register.  DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in MCI_DTOR has been exceeded. Cleared by reading in the MCI_SR register.  OVRE: Overrun 0 = No error. 1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command.  UNRE: Underrun 0 = No error. 1 = At least one 8-bit data has been sent without valid inform ation (not written). Cleared when sending a new data transfer command.  RXBUFF: RX Buffer Full 0 = MCI_RCR or MCI_RNCR has a value other than 0. 1 = Both MCI_RCR and MCI_RNCR have a value of 0.  TXBUFE: TX Buffer Empty 0 = MCI_TCR or MCI_TNCR has a value other than 0. 1 = Both MCI_TCR and MCI_TNCR have a value of 0.

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.11 MCI Interrupt Enable Register

Name: MCI_IER Address: 0xFFFA8044 Access Type: Write-only  CMDRDY: Command Ready Interrupt Enable  RXRDY: Receiver Ready Interrupt Enable  TXRDY: Transmit Ready Interrupt Enable  BLKE: Data Block Ended Interrupt Enable  DTIP: Data Transfer in Progress Interrupt Enable  NOTBUSY: Data Not Busy Interrupt Enable  ENDRX: End of Receive Buffer Interrupt Enable  ENDTX: End of Transmit Buffer Interrupt Enable  RXBUFF: Receive Buffer Full Interrupt Enable  TXBUFE: Transmit Buffer Empty Interrupt Enable  RINDE: Response Index Error Interrupt Enable  RDIRE: Response Direction Error Interrupt Enable  RCRCE: Response CRC Error Interrupt Enable  RENDE: Response End Bit Error Interrupt Enable  RTOE: Response Time-out Error Interrupt Enable  DCRCE: Data CRC Error Interrupt Enable  DTOE: Data Time-out Error Interrupt Enable  OVRE: Overrun Interrupt Enable  UNRE: UnderRun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 T X B U F E R X B U F F –––––– 76543210 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.12 MCI Interrupt Disable Register

Name: MCI_IDR Address: 0xFFFA8048 Access Type: Write-only  CMDRDY: Command Ready Interrupt Disable  RXRDY: Receiver Ready Interrupt Disable  TXRDY: Transmit Ready Interrupt Disable  BLKE: Data Block Ended Interrupt Disable  DTIP: Data Transfer in Progress Interrupt Disable  NOTBUSY: Data Not Busy Interrupt Disable  ENDRX: End of Receive Buffer Interrupt Disable  ENDTX: End of Transmit Buffer Interrupt Disable  RXBUFF: Receive Buffer Full Interrupt Disable  TXBUFE: Transmit Buffer Empty Interrupt Disable  RINDE: Response Index Error Interrupt Disable  RDIRE: Response Direction Error Interrupt Disable  RCRCE: Response CRC Error Interrupt Disable  RENDE: Response End Bit Error Interrupt Disable  RTOE: Response Time-out Error Interrupt Disable  DCRCE: Data CRC Error Interrupt Disable  DTOE: Data Time-out Error Interrupt Disable  OVRE: Overrun Interrupt Disable  UNRE: UnderRun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 T X B U F E R X B U F F –––––– 76543210 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

6242E–ATARM–11-Sep09 AT91SAM9261S

35.9.13 MCI Interrupt Mask Register

Name: MCI_IMR Address: 0xFFFA804C Access Type: Read-only  CMDRDY: Command Ready Interrupt Mask  RXRDY: Receiver Ready Interrupt Mask  TXRDY: Transmit Ready Interrupt Mask  BLKE: Data Block Ended Interrupt Mask  DTIP: Data Transfer in Progress Interrupt Mask  NOTBUSY: Data Not Busy Interrupt Mask  ENDRX: End of Receive Buffer Interrupt Mask  ENDTX: End of Transmit Buffer Interrupt Mask  RXBUFF: Receive Buffer Full Interrupt Mask  TXBUFE: Transmit Buffer Empty Interrupt Mask  RINDE: Response Index Error Interrupt Mask  RDIRE: Response Direction Error Interrupt Mask  RCRCE: Response CRC Error Interrupt Mask  RENDE: Response End Bit Error Interrupt Mask  RTOE: Response Time-out Error Interrupt Mask  DCRCE: Data CRC Error Interrupt Mask  DTOE: Data Time-out Error Interrupt Mask  OVRE: Overrun Interrupt Mask  UNRE: UnderRun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 T X B U F E R X B U F F –––––– 76543210 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

6242E–ATARM–11-Sep09 AT91SAM9261S 36. USB Host Port (UHP)

36.1 Overview

The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides sev- eral high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology. The USB Host Port controller is fully complia nt with the OpenHCI spec ification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification OHCI USB stack driver can be easily ported to AT MEL’s architecture in the same way all exist- ing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses.

36.2 Block Diagram

Figure 36-1. Block Diagram Access to the USB host operational registers is achieved through the AHB bus slave interface. The OpenHCI host controller initializes master DMA transfers through the ASB bus master inter- face as follows:  Fetches endpoint descriptors and transfer descriptors  Access to endpoint data from system memory PORT S/M PORT S/M USB transceiver USB transceiver DP DM DP DM Embedded USB v2.0 Full-speed Transceiver Root Hub and Host SIE List Processor Block FIFO 64 x 8 HCI Slave Block OHCI Registers OHCI Root Hub RegistersAHB ED & TD Regsisters Control HCI Master Block Data uhp_int MCK UHPCK AHB Slave Master

6242E–ATARM–11-Sep09 AT91SAM9261S  Access to the HC communication area  Write status and retire transfer Descriptor Memory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. Warning: A pull-down must be connected to DP on the board. Otherwise the USB host will per- manently detect a device connection on this port. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate pads to external over current protection.

36.3 Product Dependencies

36.3.1 I/O Lines

DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceiv- ers are controlled by the USB host controller.

36.3.2 Power Management

The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain).

36.3.3 Interrupt

The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP.

36.4 Functional Description

Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.

36.4.1 Host Controller Interface

There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operatio nal registers located on the USB Host Controller. The Host Controller is the target for all co mmunications on this channel. The operational regis- ters contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second com- munication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descrip tor lists, the head pointer to the done queue and status information associated with start-of-frame processing.

6242E–ATARM–11-Sep09 AT91SAM9261S The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. Figure 36-2. USB Host Communication Channels

36.4.2 Host Controller Driver

Figure 36-3. USB Host Drivers Operational Registers Mode HCCA Status Event Frame Int Ratio Control Bulk Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 31 Done . . . . . . Open HCI Shared RAM Device Register in Memory Space Device Enumeration = Transfer Descriptor = Endpoint Descriptor . . . Host Controller Hardware HUB Driver Host Controller Driver USB Driver Mini Driver Class Driver Class Driver User Application Kernel Drivers User Space Hardware

6242E–ATARM–11-Sep09 AT91SAM9261S USB Handling is done through several layers as follows:  Host controller hardware and serial engine: Transmits and receives USB data on the bus.  Host controller driver: Drives the Host controller hardware and handles the USB protocol.  USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface.  Mini driver: Handles device specific commands.  Class driver: Handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver.

36.5 Typical Connection

Figure 36-4. Board Schematic to Interface UHP Device Controller As device connection is automatically detected by the USB host port logic, a pull-down must be connected on DP and DM on the board. Otherwise the USB host permanently detects a device connection on this port. A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT). REXTHDMA or HDMB HDPA or HDPB 15kΩ15kΩ 10nF100nF10μF 5V 0.20A Type A Connector REXT

6242E–ATARM–11-Sep09 AT91SAM9261S 37. USB Device Port (UDP)

37.1 Overview

The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandator y for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Note: 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode. Suspend and resume are automatically detected by the USB device, which notifies the proces- sor by raising an interrupt. Depending on the product, an external signal can be used to send a wake up to the USB host controller. Table 37-1. USB Endpoint Description Endpoint Number Mn emonic Dual-Bank (1) Max. Endpoint Size Endpoint Type

0 EP0 No 8 Control/Bulk/Interrupt

1 EP1 Y es 64 Bulk/Iso/Interrupt

2 EP2 Y es 64 Bulk/Iso/Interrupt

3 EP3 No 64 Control/Bulk/Interrupt

4 EP4 Y es 256 Bulk/Iso/Interrupt

5 EP5 Y es 256 Bulk/Iso/Interrupt

6242E–ATARM–11-Sep09 AT91SAM9261S

37.2 Block Diagram

Figure 37-1. Block Diagram Access to the UDP is via the APB bus interface. Read and write to the data FI FO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The external_resume signal is optional. It allo ws the UDP peripheral to wake up once in system mode. The host is then notified that the device asks for a resume. This optional feature must also be negotiated with the host during the enumeration.

37.3 Product Dependencies

For further details on the USB Device hardware implementation, see the specific Product Prop- erties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pullup on DP must be disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pullup.

37.3.1 I/O Lines

DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral. Atmel Bridge

12 MHz

W r a p p e r W r a p p e r U s e r I n t e r f a c e Serial Interface Engine SIE MCK Master Clock Domain Dual Port RAM FIFO UDPCK Recovered 12 MHz Domain udp_int USB Device Embedded USB Transceiver DP DM external_resume APB to MCU Bus txoen eopn txd rxdm rxd rxdp

6242E–ATARM–11-Sep09 AT91SAM9261S To reserve an I/O line to check VBUS, the program mer must first program the PIO controller to assign this I/O in input PIO mode.

37.3.2 Power Management

The USB device peripheral requires a 48 MHz cl ock. This clock must be generated by a PLL with an accuracy of ± 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to inter- face with the bus USB signals (recovered 12 MHz domain). WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.

37.3.3 Interrupt

The USB device interface has an interrupt line co nnected to the Advanced Interrupt Controller (AIC). Handling the USB device interrupt requires programming the AIC before configuring the UDP.

6242E–ATARM–11-Sep09 AT91SAM9261S

37.4 Typical Connection

Figure 37-2. Board Schematic to Interface Device Peripheral

37.4.1 USB Device Transceiver

The USB device transceiver is embedded in the product. A few discrete components are required as follows:  the application detects all device states as defined in chapter 9 of the USB specification; –V B U S m o n i t o r i n g  to reduce power consumption the host is disconnected  for line termination.

37.4.2 VBUS Monitoring

VBUS monitoring is required to detect host connection. VBUS monitoring is done using a stan- dard PIO with internal pullup disabled. When the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pull- up resistor. When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to over consumption. A solution is to connect 330 K Ω pulldowns on DP and DM. These pulldowns do not alter DDP and DDM signal integrity. A termination serial resistor must be connected to DP and DM. The resistor value is defined in the electrical specification of the product (R EXT). REXT REXT DDM DDP PIO 27 K 47 K 330 K Type B Connector 5V Bus Monitoring 330 K

6242E–ATARM–11-Sep09 AT91SAM9261S

37.5 Functional Description

37.5.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of commu- nication flows. Figure 37-3. Example of USB V2.0 Full-speed Communication Control The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB v. 2.0 specifications). 37.5.1.1 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device.

37.5.1.2 USB Bus Transactions

Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across the bus in packets: EP0 USB Host V2.0 Software Client 1 Software Client 2 Data Flow: Bulk Out Transfer Data Flow: Bulk In Transfer Data Flow: Control Transfer Data Flow: Control Transfer EP1 EP2 USB Device 2.0 Block 1 USB Device 2.0 Block 2 EP5 EP4 EP0 Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer USB Device endpoint configuration requires that in the first instance Control Transfer must be EP0. Table 37-2. USB Communication Flow Transfer Direction Bandwidth Supported Endpoint Size Error Detection Retrying Control Bidirectional Not guaranteed 8, 16, 32, 64 Y es Automatic Isochronous Unidirectional Guaranteed 256 Y es No Interrupt Unidirectional Not guaranteed ≤ 64 Y es Y es Bulk Unidirectional Not guaranteed 8, 16, 32, 64 Y es Y es

6242E–ATARM–11-Sep09 AT91SAM9261S 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction

37.5.1.3 USB Transfer Event Definitions

As indicated below, transfers are sequential events carried out on the USB bus. Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. Table 37-3. USB Transfer Events Control Transfers(1) (3)  Setup transaction > Data IN transactions > Status OUT transaction  Setup transaction > Data OUT transactions > Status IN transaction  Setup transaction > Status IN transaction Interrupt IN Transfer (device toward host)  Data IN transaction > Data IN transaction Interrupt OUT Transfer (host toward device)  Data OUT transaction > Data OUT transaction Isochronous IN Transfer(2) (device toward host)  Data IN transaction > Data IN transaction Isochronous OUT Transfer(2) (host toward device)  Data OUT transaction > Data OUT transaction Bulk IN Transfer (device toward host)  Data IN transaction > Data IN transaction Bulk OUT Transfer (host toward device)  Data OUT transaction > Data OUT transaction

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 37-4. Control Read and Write Sequences Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 37.5.2 Handling Transactions with USB V2.0 Device Peripheral

37.5.2.1 Setup Transaction

Setup is a special type of host-to-device transaction used during control transfers. Control trans- fers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more argu- ments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint:  The USB device automatically acknowledges the setup packet  RXSETUP is set in the UDP_CSRx register  An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. Control Read Setup TX Data OUT TX Data OUT TX Data Stage Control Write Setup Stage Setup Stage Setup TX Setup TXNo Data Control Data IN TX Data IN TX Status Stage Status Stage Status IN TX Status OUT TX Status IN TX Data Stage Setup Stage Status Stage

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 37-5. Setup Transaction Followed by a Data OUT Transaction

37.5.2.2 Data IN Transaction

Data IN transactions are used in control, is ochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes.

37.5.2.3 Using Endpoints Without Ping-pong Attributes

To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 6. The microcontroller notifi es the USB peripheral it has finished by setting the TXPK- TRDY in the endpoint’s UDP_CSRx register. 7. The application clears the TXCOMP in the endpoint’s UDP_CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. RX_Data_BKO (UDP_CSRx) ACK PIDData OUTData OUT PID NAK PID ACK PIDData SetupSetup PID USB Bus Packets RXSETUP Flag Set by USB Device Cleared by Firmware Set by USB Device Peripheral FIFO (DPR) Content Data Setup DataXX XX OUT Interrupt Pending Setup Received Setup Handled by Firmware Data Out Received Data OUTData OUT PID

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 37-6. Data IN Transfer for Non Ping-pong Endpoint

37.5.2.4 Using Endpoints With Ping-pong Attribute

The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk trans- fer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 37-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: USB Bus Packets Data IN 2Data IN NAKACKData IN 1 FIFO (DPR) Content Data IN 2Load In ProgressData IN 1 Cleared by Firmware DPR access by the firmware Payload in FIFO TXCOMP Flag (UDP_CSRx) TXPKTRDY Flag (UDP_CSRx) PID Data IN Data IN PIDPID PID PID ACK PID Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus Interrupt Pending Interrupt Pending Set by the firmware Set by the firmware Cleared by Firmware Cleared by HwCleared by Hw DPR access by the hardware USB Device USB Bus ReadWrite Read and Write at the Same Time 1st Data Payload 2nd Data Payload 3rd Data Payload 3rd Data Payload 2nd Data Payload 1st Data Payload Data IN Packet Data IN Packet Data IN Packet Microcontroller Endpoint 1 Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 1

6242E–ATARM–11-Sep09 AT91SAM9261S 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleare d, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCO MP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the end- point’s UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay- load to be sent Figure 37-8. Data IN Transfer for Ping-pong Endpoint Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the bandwidth. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Data INData IN Read by USB Device Read by USB DeviceBank 1 Bank 0 FIFO (DPR) TXCOMP Flag (UDP_CSRx) Interrupt Cleared by Firmware Set by USB Device TXPKTRDY Flag (UDP_MCSRx) ACKPID Data IN PID ACKPID Set by Firmware, Data Payload Written in FIFO Bank 1 Cleared by USB Device, Data Payload Fully Transmitted Data IN PID USB Bus Packets Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 0 Written by FIFO (DPR) Microcontroller Written by MicrocontrollerWritten by Microcontroller Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 Interrupt Pending

6242E–ATARM–11-Sep09 AT91SAM9261S

37.5.2.5 Data OUT Transaction

Data OUT transactions are used in control, isochronous, bulk and interru pt transfers and con- duct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes.

37.5.2.6 Data OUT Transaction Without Ping-pong Attributes

To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notifie d that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FI FO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its mem- ory. Data received is available by reading the endpoint’s UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 37-9. Data OUT Transfer for Non Ping-pong Endpoints An interrupt is pending while the flag RX_DAT A_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would acce pt the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.

37.5.2.7 Using Endpoints With Ping-pong Attributes

During isochronous transfer, using an endpoint wit h ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the micr ocontroller must read the previous data pay- ACK PID Data OUTNAK PIDPIDPIDPIDPID Data OUT2ACKData OUT Data OUT 1USB Bus Packets RX_DATA_BK0 Set by USB Device Cleared by Firmware, Data Payload Written in FIFO FIFO (DPR) Content Written by USB Device Microcontroller Read Data OUT 1 Data OUT 1 Data OUT 2 Host Resends the Next Data Payload Microcontroller Transfers Data Host Sends Data Payload Data OUT2 Data OUT2 Host Sends the Next Data Payload Written by USB Device (UDP_CSRx) Interrupt Pending

6242E–ATARM–11-Sep09 AT91SAM9261S load sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 37-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notifi ed that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FI FO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_FDRx register. USB Device USB Bus ReadWrite Write and Read at the Same Time 1st Data Payload 2nd Data Payload 3rd Data Payload 3rd Data Payload 2nd Data Payload 1st Data Payload Data IN Packet Data IN Packet Data IN Packet Microcontroller Endpoint 1 Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 1

6242E–ATARM–11-Sep09 AT91SAM9261S 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 37-11. Data OUT Transfer for Ping-pong Endpoint Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alter- natively RX_DATA_BK0 then RX_DATA_BK1. Th is situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set.

37.5.2.8 Stall Handshake

A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)  A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)  To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. A P Data OUT PID ACK Data OUT 3Data OUTData OUT 2Data OUTData OUT 1PID Data OUT 3Data OUT 1Data OUT1 Data OUT 2 Data OUT 2 PID PID PID ACK Cleared by Firmware USB Bus Packets RX_DATA_BK0 Flag RX_DATA_BK1 Flag Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 FIFO (DPR) Bank 0 Bank 1 Write by USB Device Write In Progress Read By Microcontroller Read By Microcontroller Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data PayloadCleared by Firmware Write by USB Device FIFO (DPR) (UDP_CSRx) (UDP_CSRx) Interrupt Pending Interrupt Pending

6242E–ATARM–11-Sep09 AT91SAM9261S

37.5.2.9 Transmit Data Cancellation

Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability, refer to Table 37-1 ”USB Endpoint Description”.

37.5.2.10 Endpoints Without Dual-Banks

There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.  TXPKTRDY is not set: – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.)  TXPKTRDY has already been set: – Clear TXPKTRDY so that no packet is ready to be sent – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.)

37.5.2.11 Endpoints With Dual-Banks

There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.  TXPKTRDY is not set: – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.)  TXPKTRDY has already been set: – Clear TXPKTRDY and read it back until actually read at 0. – Set TXPKTRDY and read it back until actually read at 1. – Clear TXPKTRDY so that no packet is ready to be sent. – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.)

6242E–ATARM–11-Sep09 AT91SAM9261S

37.5.3 Controlling Device States

A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Speci- fication, Rev 2.0. Figure 37-14. USB Device State Diagram Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the US B device enters Suspend Mode. Accepting Sus- pend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host. Attached Suspended Suspended Suspended Suspended Hub Reset or Deconfigured Hub Configured Bus Inactive Bus Activity Bus Inactive Bus Activity Bus Inactive Bus Activity Bus Inactive Bus Activity Reset Reset Address Assigned Device Deconfigured Device Configured Powered Default Address Configured Power Interruption

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37.5.3.1 Not Powered State

Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UD P, disabling UDPCK and disabl ing the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors.

37.5.3.2 Entering Attached State

When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub down- stream port, the device connects a 1.5 K Ω pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 K Ω resistor to 3.3V and DM is pulled down by the 15 K Ω resistor of the host. To enable integrated pullup, the UDP_PUP_ON bit in the USB_PUCR Bus Matrix register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pullup connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled.

37.5.3.3 From Powered State to Default State

After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must:  Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer.  Configure the interrupt mask register which has been reset by the USB reset detection  Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset.

37.5.3.4 From Default State to Address State

After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register.

37.5.3.5 From Address State to Configured State

Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register.

6242E–ATARM–11-Sep09 AT91SAM9261S

37.5.3.6 Entering in Suspend State

When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an exam- ple, the microcontroller switches to slow clock, disables the PL L and main osc illator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be s witched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP.

37.5.3.7 Receiving a Host Resume

In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may gen- erate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clea ring the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register.

37.5.3.8 Sending a Device Remote Wakeup

In Suspend state it is possible to wake up the host sending an external resume.  The device must wait at least 5 ms after being entered in suspend before sending an external resume.  The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host.  The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DM at 3.3V and DP tied to GND), it is possible to use a transistor to connect a pullup on DM. The K state is obt ained by disabling the pullup on DP and enabling the pullup on DM. This should be under the control of the application.

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 37-15. Board Schematic to Drive a K State 3V3 PIO 1.5 K 0: Force Wake UP (K State) 1: Normal Mode DM

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6 USB Device Port (UDP) User Interface

WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register. Notes: 1. Reset values are not defined for UDP_ISR. 2. See Warning above the ”Register Mapping” on this page. Table 37-4. Register Mapping Offset Register Name Access Reset 0x000 Frame Number Register UDP_FRM_NUM Read-only 0x0000_0000 0x004 Global State Register UDP_GLB_STAT Read-write 0x0000_0000 0x008 Function Address Register UDP_FADDR Read-write 0x0000_0100 0x00C Reserved – – – 0x010 Interrupt Enable Register UDP_IER Write-only 0x014 Interrupt Disable Register UDP_IDR Write-only 0x018 Interrupt Mask Register UDP_IMR Read-only 0x0000_1200 0x01C Interrupt Status Register UDP_ISR Read-only – (1) 0x020 Interrupt Clear Register UDP_ICR Write-only 0x024 Reserved – – – 0x028 Reset Endpoint Register UDP_RST_EP Read-write 0x0000_0000 0x02C Reserved – – – 0x030 + 0x4 * ( ept_num - 1 ) Endpoint Control and Status Register UDP_CSR Read-write 0x0000_0000 0x050 + 0x4 * ( ept_num - 1 ) Endpoint FIFO Data Register UDP_FDR Read-write 0x0000_0000 0x070 Reserved – – – 0x074 Transceiver Control Register UDP_TXVC (2) Read-write 0x0000_0000 0x078 - 0xFC Reserved – – –

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.1 UDP Frame Number Register

Name: UDP_FRM_NUM Address: 0xFFFA4000 Access Type: Read-only  FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet).  FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID.  FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interfac e, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 FRM_NUM

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37.6.2 UDP Global State Register

Name: UDP_GLB_STAT Address: 0xFFFA4004 Access Type: Read-write This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.  FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR regis- ter must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.  CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

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37.6.3 UDP Function Address Register

Name: UDP_FADDR Address: 0xFFFA4008 Access Type: Read-write  FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0.  FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –F A D D

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37.6.4 UDP Interrupt Enable Register

Name: UDP_IER Address: 0xFFFA4010 Access Type: Write-only  EP0INT: Enable Endpoint 0 Interrupt  EP1INT: Enable Endpoint 1 Interrupt  EP2INT: Enable Endpoint 2Interrupt  EP3INT: Enable Endpoint 3 Interrupt  EP4INT: Enable Endpoint 4 Interrupt  EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt.  RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt.  RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt.  SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt.  WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP – SOFINT – RXRSM RXSUSP 76543210 – – EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

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37.6.5 UDP Interrupt Disable Register

Name: UDP_IDR Address: 0xFFFA4014 Access Type: Write-only  EP0INT: Disable Endpoint 0 Interrupt  EP1INT: Disable Endpoint 1 Interrupt  EP2INT: Disable Endpoint 2 Interrupt  EP3INT: Disable Endpoint 3 Interrupt  EP4INT: Disable Endpoint 4 Interrupt  EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt.  RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt.  RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt.  SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt  WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP – SOFINT – RXRSM RXSUSP 76543210 – – EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

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37.6.6 UDP Interrupt Mask Register

Name: UDP_IMR Address: 0xFFFA4018 Access Type: Read-only  EP0INT: Mask Endpoint 0 Interrupt  EP1INT: Mask Endpoint 1 Interrupt  EP2INT: Mask Endpoint 2 Interrupt  EP3INT: Mask Endpoint 3 Interrupt  EP4INT: Mask Endpoint 4 Interrupt  EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled.  RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled.  RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled.  SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled.  BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 311 1 1 09 8 – – WAKEUP BIT12 SOFINT – RXRSM RXSUSP 76543210 – – EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

6242E–ATARM–11-Sep09 AT91SAM9261S  WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may po wer down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.7 UDP Interrupt Status Register

Name: UDP_ISR Address: 0xFFFA401C Access Type: Read-only  EP0INT: Endpoint 0 Interrupt Status  EP1INT: Endpoint 1 Interrupt Status  EP2INT: Endpoint 2 Interrupt Status  EP3INT: Endpoint 3 Interrupt Status  EP4INT: Endpoint 4 Interrupt Status  EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit.  RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP ENDBUSRES SOFINT – RXRSM RXSUSP 76543210 – – EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

6242E–ATARM–11-Sep09 AT91SAM9261S  RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register.  SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.  ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the end- point 0. The host starts the enumeration, then performs the configuration.  WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR register.

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.8 UDP Interrupt Clear Register

Name: UDP_ICR Address: 0xFFFA4020 Access Type: Write-only  RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt.  RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.  SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt.  ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt.  WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP ENDBUSRES SOFINT – RXRSM RXSUSP 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.9 UDP Reset En dpoint Register

Name: UDP_RST_EP Address: 0xFFFA4028 Access Type: Read-write  EP0: Reset Endpoint 0  EP1: Reset Endpoint 1  EP2: Reset Endpoint 2  EP3: Reset Endpoint 3  EP4: Reset Endpoint 4  EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT c ondition on a BULK endpoint. Refer to Chapter Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. Resetting the endpoint is a two-step operation: 1. Set the corresponding EPx field. 2. Clear the corresponding EPx field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – EP5 EP4 EP3 EP2 EP1 EP0

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.10 UDP Endpoint Control and Status Register

Name: UDP_CSRx [x = 0..5] Address: 0xFFFA402C Access Type: Read-write WARNING: Due to synchronization between MCK and UDPCK, the soft ware application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared. //! Clear flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_clr_flag(pInterface, endpoint, flags) { \\ pInterface->UDP_CSR[endpoint] &= ~(flags); \\ while ( (pInterface->UDP_CSR[endpoint] & (flags)) == (flags) ); \\ //! Set flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_set_flag(pInterface, endpoint, flags) { \\ pInterface->UDP_CSR[endpoint] |= (flags); \\ while ( (pInterface->UDP_CSR[endpoint] & (flags)) != (flags) ); \\ Note: In preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. How- ever, RX_DATA_BLK0, TXPKTRDY , RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 3 peripheral clock cycles before accessing DPR.  TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXBYTECNT 15 14 13 12 11 10 9 8 EPEDS – – – DTGLE EPTYPE 76543210 DIR RX_DATA_ BK1 FORCE STALL TXPKTRDY STALLSENT ISOERROR RXSETUP RX_DATA_ BK0 TXCOMP

6242E–ATARM–11-Sep09 AT91SAM9261S  RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral cl ock cycles is required before accessing DPR.  RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success- fully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set.  STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect.

6242E–ATARM–11-Sep09 AT91SAM9261S This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect.  TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = There is no data to send. 1 = The data is waiting to be sent upon reception of token IN. Write: 0 = Can be used in the procedure to cancel transmission data. (See, Section 37.5.2.9 “Transmit Data Cancellation” on page 563) 1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data payload has been transferred to the FIFO, the firmwar e notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral cl ock cycles is required before accessing DPR.  FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.

6242E–ATARM–11-Sep09 AT91SAM9261S Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.  RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clear- ing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral cl ock cycles is required before accessing DPR.  DIR: Transfer Direction (only available for control endpoints) Read-write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage.  EPTYPE[2:0]: Endpoint Type Read-write

000 Control

001 Isochronous OUT

101 Isochronous IN

010 Bulk OUT

110 Bulk IN

011 Interrupt OUT

111 Interrupt IN

6242E–ATARM–11-Sep09 AT91SAM9261S  DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.  EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero).  RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontrol- ler. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register.

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.11 UDP FIFO Data Register

Name: UDP_FDRx [x = 0..5] Address: 0xFFFA404C Access Type: Read-write  FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 FIFO_DATA

6242E–ATARM–11-Sep09 AT91SAM9261S

37.6.12 UDP Transceiver Control Register

Name: UDP_TXVC Address: 0xFFFA4074 Access Type: Read-write WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.  TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. NOTE: If the USB pullup is not connected on DP, the user shou ld not write in any UDP register other than the UDP_TXVC register. This is because if DP and DM are floating at 0, or pulled down, then SE0 is received by the device with the conse- quence of a USB Reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

6242E–ATARM–11-Sep09 AT91SAM9261S 38. LCD Controller (LCDC)

38.1 Overview

The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN displays to generate up to 4096 colors. The LCD Controller has a display input buffer (FIFO) to allow a flexible connection of the exter- nal AHB master interface, and a lookup table to allow palletized display configurations. The LCD Controller is programmable in order to support many different requirements such as resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing. The LCD Controller is connected to the ARM Advanced High Performance Bus (AHB) as a mas- ter for reading pixel data. However, the LCD Cont roller interfaces with the AHB as a slave in order to configure its registers.

6242E–ATARM–11-Sep09 AT91SAM9261S

38.2 Block Diagram

Figure 38-1. LCD Macrocell Block Diagram Timegen PWMDisplay CFG CH-L AHB IF CH-U CTRL CFG AHB SLAVE DISPLAY IF AHB MASTER SPLIT LUT MEM FIFO MEM DMA Controller LCD Controller Core Configuration IF Control Interface Lower Push FIFO SERIALIZER PALETTE DITHERING OUTPUT SHIFTER AHB SLAVE AHB SLAVE Input Interface Upper Push DMA Data LCDD DISPLAY IF Control signals Dvalid Dvalid LUT Mem Interface FIFO Mem Interface LUT Mem Interface DATAPATH

6242E–ATARM–11-Sep09 AT91SAM9261S

38.3 I/O Lines Description

38.4 Product Dependencies

38.4.1 I/O Lines

The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The pro- grammer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCD Controller are not used by the application, they can be used for other pur- poses by the PIO Controller.

38.4.2 Power Management

The LCD Controller is not continuously clocked. As the LCD Controller is on the AHB bus, the clock is enabled by setting the HCKx bit in the PMC_SCER register.

38.4.3 Interrupt Sources

The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC.

38.5 Functional Description

The LCD Controller consists of two main blocks ( Figure 38-1 on page 588 ), the DMA controller and the LCD controller core (LCDC core). The DMA controller reads the display data from an external memory through a AHB master interface. The LCD controller core formats the display data. The LCD controller core continuously pumps the pixel data into the LCD module via the LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK, LCDDEN, LCDHSYNC, and LCDVSYNC signals.

38.5.1 DMA Controller

38.5.1.1 Configuration Block

The configuration block is a set of programmable registers that are used to configure the DMA controller operation. These registers are written via the AHB slave interface. Only word access is allowed. For details on the configuration registers, see “LCD Controller (LCDC) User Interface” on page 613.

38.5.1.2 AHB Interface

This block generates the AHB transactions. It generates undefined-length incrementing bursts as well as 4- ,8- or 16-beat incrementing bursts. The size of the transfer can be configured in the Table 38-1. I/O Lines Description Name Description Type LCDCC Contrast control signal Output LCDHSYNC Line synchronous signal (STN) or Horizontal synchronous signal (TFT) Output LCDDOTCK LCD clock signal (STN/TFT) Output LCDVSYNC Frame synchronous signal (STN) or Ve rtical synchronization signal (TFT) Output LCDDEN Data enable signal Output LCDD[23:0] LCD Data Bus output Output

6242E–ATARM–11-Sep09 AT91SAM9261S BRSTLN field of the DMAFRMCFG register. For details on this register, see “DMA Frame Con- figuration Register” on page 619.

38.5.1.3 Channel-U

This block stores the base address and the number of words transferred for this channel (frame in single scan mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame signal. It has two pointers, the base address and the number of words to transfer. When the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. When the module receives the new_frame signal, it also reloads the base address with the base address programmed by the host. The size of the frame/panel can be programmed in the FRMSIZE field of the DMAFRMCFG Register. This size is calculated as follows: where:  Display_size =Horizontal_display_size x Vertical_display_size  Bpp is the bits per pixel configuration

38.5.1.4 Channel-L

This block has the same functionality as Channel- U, but for the Lower Panel in dual scan mode only.

38.5.1.5 Control

This block receives the request signals from the LCDC core and generates the requests for the channels.

38.5.2 LCD Controller Core

38.5.2.1 Configuration Block

The configuration block is a set of programmable registers that are used to configure the LCDC core operation. These registers are written via the AHB slave interface. Only word access is allowed. The description of the configuration registers can be found in “LCD Controller (LCDC) User Interface” on page 613.

38.5.2.2 Datapath

The datapath block contains five submodules: FIF O, Serializer, Palette, Dithering and Shifter. The structure of the datapath is shown in Figure 38-2. Frame_size Display_size Bpp×

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-2. Datapath Structure This module transforms the data read from the memory into a format according to the LCD mod- ule used. It has four different interfaces: the input interface, the output interface, the configuration interface and the control interface.  The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus and two push lines that are used by the DMA controller to fill the FIFOs.  The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).  The configuration interface connects the datapath with the configuration block. It is used to select between the different datapath configurations.  The control interface connects the datapath with the timing generation block. The main control signal is the data-request signal, used by the timing generation module to request new data from the datapath. The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data is available at the output of the datapath. Th e parameter cycles_per_data is the minimum num- ber of LCDC Core clock cycles between two consecutive data at the output interface. FIFO Serializer Palette Dithering Output Shifter Input Interface Output Interface Configuration IF Control Interface

6242E–ATARM–11-Sep09 AT91SAM9261S These parameters are different for the different configurations of the LCD Controller and are shown in Table 38-2.

38.5.2.3 FIFO

The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to be used in Dual Scan configuration that are configured as a single FIFO when used in single scan configuration. The size of the FIFOs allows a wide range of architectures to be supported. The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO regis- ter. The LCDC core will request a DMA transfer when the number of words in each FIFO is less than FIFOTH words. To avoid overwriting in the FIFO and to maximize the FIFO utilization, the FIFOTH should be programmed with: FIFOTH = 512 - (2 x DMA_BURST_LENGTH + 3) where:  512 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode.  DMA_burst_length is the burst length of the transfers made by the DMA

38.5.2.4 Serializer

This block serializes the data read from memory. It reads words from the FIFO and outputs pix- els (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both big- endian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register. The organization of the pixel data in the memory depends on the configur ation and is shown in Table 38-3 and Table 38-4. Table 38-2. Datapath Parameters Configuration initial_latency cycles_per_dataDISTYPE SCAN IFWIDTH TFT 9 1 STN Mono Single 4 13 4 STN Mono Single 8 17 8 STN Mono Dual 8 17 8 STN Mono Dual 16 25 16 STN Color Single 4 11 2 STN Color Single 8 12 3 STN Color Dual 8 14 4 STN Color Dual 16 15 6

6242E–ATARM–11-Sep09 AT91SAM9261S Table 38-3. Little Endian Memory Organization Mem Addr 0x3 0x2 0x1 0x0 B i t 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 Pixel 2bpp 15 14 13 12 11 10 9 876543210 Pixel 4bpp 7 6 5 4 3 2 1 0 Pixel 8bpp 3210 Pixel 16bpp 10 Pixel 24bpp 10 Pixel 24bpp 21 Pixel 24bpp 32 Pixel 24bpp 54 Table 38-4. Big Endian Memory Organization Mem Addr 0x3 0x2 0x1 0x0 B i t 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Pixel 1bpp 0 1 2 34567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Pixel 2bpp 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 Pixel 4bpp 0 1 2 3 4 5 6 7 Pixel 8bpp 0123 Pixel 16bpp 01 Pixel 24bpp 01 Pixel 24bpp 12 Pixel 24bpp 23 Pixel 24bpp 45

6242E–ATARM–11-Sep09 AT91SAM9261S

38.5.2.5 Palette

This block is used to generate the pixel gray or color information in palletized configurations. The different modes with the palletized/non-palletized configuration can be found in Table 38-5. In these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. The corresponding entry in the lookup table contains the color or gray shade information for the pixel. The lookup table can be accessed by the host in R/W mode to allow the host to program and check the values stored in the palette. It is mapped in the LCD controller configuration memory map. The LUT is mapped as 16-bit half-words aligned at word boundaries, only word write access is allowed (the 16 MSB of the bus are not used). For the detailed memory map, see Table 38-12 on page 613. The lookup table contains 256 16 -bit wide entries. The 256 entries are chosen by the program- mer from the 2 16 possible combinations. For the structure of each LUT entry, see Table 38-6. In STN Monochrome, only the four most signifi cant bits of the red value are used (16 gray shades). In STN Color, only the four most signi ficant bits of the blue, green and red value are used (4096 colors). In TFT mode, all the bits in the blue, green and red values are used (32768 colors). In this mode, there is also a common intensity bit that can be used to double the possible colors. This bit is the least significant bit of each color component in the LCDD interface (LCDD[18], LCDD[10], LCDD[2]). The LCDD unused bits are tied to 0 when TFT palletized configurations are used (LCDD[17:16], LCDD[9:8], LCDD[1:0]). Table 38-5. Palette Configurations Configuration PaletteDISTYPE PIXELSIZE TFT 1, 2, 4, 8 Palletized TFT 16, 24 Non-palletized STN Mono 1, 2 Palletized STN Mono 4 Non-palletized STN Color 1, 2, 4, 8 Palletized STN Color 16 Non-palletized Table 38-6. Lookup Table Structure in the Memory Address Data Output [15:0]

00 Intensity_bit_0 Blue_value_0[4:0] Green_value_0[4:0] Red_value_0[4:0]

01 Intensity_bit_1 Blue_value_1[4:0] Green_value_1[4:0] Red_value_1[4:0]

... FE Intensity_bit_254 Blue_value_254[4: 0] Green_value_254[4:0] Red_value_254[4:0] FF Intensity_bit_255 Blue_value_255[4: 0] Green_value_255[4:0] Red_value_255[4:0]

6242E–ATARM–11-Sep09 AT91SAM9261S

38.5.2.6 Dithering

The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Con- trol method. The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the dis- play an appearance of multiple shades. In order to reduce the flicker noise caused by turning on and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. This algorithm is expressed in terms of Dithering Pattern registers (DP_i) and considers not only the pixel gray level number, but also its horizontal coordinate. Table 38-7 shows the correspondences between the gray levels and the duty cycle. The duty cycles for gray levels 0 and 15 are 0 and 1, respectively. The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The dithering pattern for the first pair member is the inversion of the one for the second. The DP_i registers contain a series of 4-bit patterns. The (3-m) th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame. The operation is shown by the examples below. Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is DP3_5 =”1010 0101 1010 0101 1111”. Table 38-7. Dithering Duty Cycle Gray Level Duty Cycle Pattern Register 15 1 - 14 6/7 DP6_7 13 4/5 DP4_5 12 3/4 DP3_4 11 5/7 DP5_7 10 2/3 DP2_3 93 / 5 D P 3 _ 5 84 / 7 D P 4 _ 7 7 1/2 ~DP1_2 6 3/7 ~DP4_7 5 2/5 ~DP3_5 4 1/3 ~DP2_3 3 1/4 ~DP3_4 2 1/5 ~DP4_5 1 1/7 ~DP6_7 00-

6242E–ATARM–11-Sep09 AT91SAM9261S The output sequence obtained in the data output for monochrome mode is shown in Table 38-8. Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be dis- played sending the color components {R0, G0, B0 } to the display. Pixe l p1 will be displayed sending the color components {R1, G1, B1}. Suppose that the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color components of both pixels, with the dithering pattern to apply to all of them being DP2_3 = “1101 1011 0110”. Table 38-9 shows the output sequence in the data output bus for single scan configurations. (In Dual Scan Configuration, each panel data bus acts like in the equivalent single scan configuration.) Table 38-8. Dithering Algorithm for Monochrome Mode Frame Number Pattern Pixel a Pixel b Pixel c Pixel d N1 0 1 0 O N O F F O N O F F N+1 0101 OFF ON OFF ON N+2 1010 ON OFF ON OFF N+3 0101 OFF ON OFF ON N + 4 1 1 1 1 O NO NO NO N N+5 1010 ON OFF ON OFF N+6 0101 OFF ON OFF ON N+7 1010 ON OFF ON OFF Table 38-9. Dithering Algorithm for Color Mode Frame Signal Shadow Level Bit used Dithering Pattern 4-bit LCDD 8-bit LCDD Output N red_data_0 1010 3 1101 LCDD[3] LCDD[7] R0 N green_data_0 1010 2 1101 LCDD[2] LCDD[6] G0 N blue_data_0 1010 1 1101 LCDD[1] LCDD[5] b0 N red_data_1 1010 0 1101 LCDD[0] LCDD[4] R1 N green_data_1 1010 3 1101 LCDD[3] LCDD[3] G1 N blue_data_1 1010 2 1101 LCDD[2] LCDD[2] B1 N+1 red_data_0 1010 3 1011 LCDD[3] LCDD[7] R0 N+1 green_data_0 1010 2 1011 LCDD[2] LCDD[6] g0 N+1 blue_data_0 1010 1 1011 LCDD[1] LCDD[5] B0 N+1 red_data_1 1010 0 1011 LCDD[0] LCDD[4] R1 N+1 green_data_1 1010 3 1011 LCDD[3] LCDD[3] G1 N+1 blue_data_1 1010 2 1011 LCDD[2] LCDD[2] b1 N+2 red_data_0 1010 3 0110 LCDD[3] LCDD[7] r0

6242E–ATARM–11-Sep09 AT91SAM9261S Note: Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF . gi = green pixel component OFF . bi = blue pixel component OFF .

38.5.2.7 Shifter

The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output interfac e. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LCDCON2 register. The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCAN- MODE field selects between single and dual sc an modes; in TFT mode, only single scan is supported. The IFWIDTH field configures the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only). For a more detailed description of the fields, see “LCD Controller (LCDC) User Interface” on page 613. For a more detailed description of the LCD Interface, see “LCD Interface” on page 602.

38.5.2.8 Timegen

The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, used by the LCD module. This block is programmable in order to support different types of LCD modules and obtain the output clock signals, which are derived from the LCDC Core clock. The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BY PASS bit in the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCD- DOTCK signal depends on the configuration. This information can be found in Table 38-10. The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2 register:  Always Active (used with TFT LCD Modules)  Active only when data is available (used with STN LCD Modules) N+2 green_data_0 1010 2 0110 LCDD[2] LCDD[6] G0 N+2 blue_data_0 1010 1 0110 LCDD[1] LCDD[5] B0 N+2 red_data_1 1010 0 0110 LCDD[0] LCDD[4] r1 N+2 green_data_1 1010 3 0110 LCDD[3] LCDD[3] g1 N+2 blue_data_1 1010 2 0110 LCDD[2] LCDD[2] B1 Table 38-9. Dithering Algorithm for Color Mode (Continued) Frame Signal Shadow Level Bit used Dithering Pattern 4-bit LCDD 8-bit LCDD Output fLCDDOTCK fLCDC_clock

6242E–ATARM–11-Sep09 AT91SAM9261S The LCDDEN signal indicates valid data in the LCD Interface. After each horizontal line of data has been shifte d into the LCD, the LCDHSYNC is asserted to cause the line to be displayed on the panel. The following timing parameters can be configured:  Vertical to Horizontal Delay (VHDL Y): The delay between begin_of_line and the generation of LCDHSYNC is configurable in the VHDL Y field of the LCDTIM1 register. The delay is equal to (VHDL Y+1) LCDDOTCK cycles.  Horizontal Pulse Width (HPW): The LCDHSYNC pu lse width is configurable in HPW field of LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles.  Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles.  Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2) LCDDOTCK cycles. There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by the initial latency of the datapath. The total de lay in LCDC clock cycles must be higher than or equal to the latency column in Table 38-2 on page 592 . This limitation is given by the following formula:

38.5.2.9 Equation 1

where:  VHDL Y , HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers  PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles  DPATH_LATENCY is the datapath latency of the configuration, given in Table 38-2 on page 592 Table 38-10. Minimum LCDDOTCK Period in LCDC Core Clock Cycles Configuration LCDDOTCK PeriodDISTYPE SCAN IFWIDTH TFT 1 STN Mono Single 4 4 STN Mono Single 8 8 STN Mono Dual 8 8 STN Mono Dual 16 16 STN Color Single 4 2 STN Color Single 8 2 STN Color Dual 8 4 STN Color Dual 16 6 VHDLY HPW HBP 3++ +() PCLK_PERIOD× DPATH_LATENCY≥

6242E–ATARM–11-Sep09 AT91SAM9261S The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at the top of the display. The timing of this signal depends on the type of LCD: STN or TFT LCD. In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode, this signal is synchronized with the first active LCDDOTCK rising edge in a line. In TFT mode, the high phase of this signal starts at the beginning of the first line. The following timing parameters can be selected:  Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register. The pulse width is equal to (VPW+1) lines.  Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of LCDTIM1 register. The number of inactive lines is equal to VBP . This field should be programmed with 0 in STN Mode.  Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of LCDTIM2 register. The number of inactive lines is equal to VFP . This field should be programmed with 0 in STN mode. There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the LCDFRMCFG:  HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.  LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The minimum value of this parameter is 1. Figure 38-3 , Figure 38-4 and Figure 38-5 show the timing of LCDDOTCK, LCDDEN, LCDH- SYNC and LCDVSYNC signals:

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-3. STN Panel Timing, CLKMOD 0 Figure 38-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1 LCDHSYNC LCDVSYNC LCDDEN LCDDOTCK LCDD Frame Period VHDLY+ HBP+1HPW+1 HFP+2HOZVAL+1 LCDDOTCK LCDD

1 PCLK 1/2 PCLK 1/2 PCLK

VHDLY+1 HBP+1 HPW+1 HFP+2 HOZVAL+1 LCDDOTCK LCDD (VPW+1) Lines LCDVSYNC LCDDOTCK LCDD LCDDEN VHDLY+1 LCDHSYNC Vertical Fron t Porch = VFP Lines Vertical Back Porch = VBP Lines Frame Period

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-5. TFT Panel Timing (Line Expanded View), CLKMOD=1 Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation: where:  HOZVAL determines de number of LCDDOTCK cycles per line  LINEVAL determines the number of LCDHSYNC cycles per frame, according to the expressions shown below: In STN Mode: In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. In color mode, Horizontal_display_size equals three times the number of horizontal pixels. In TFT Mode: The frame rate equation is used first without considering the clock periods added at the end beginning or at the end of each line to determine, approximately, the LCDDOTCK rate: With this value, the CLKVAL is fixed, as well as the corresponding LCDDOTCK rate. Then select VHDLY, HPW and HBP according to the type of LCD used and “Equation 1” on page 598. Finally, the frame rate is adjusted to 70 Hz - 75 Hz with the HFP value: VHDLY+1 HBP+1 HPW+1 HFP+2 HOZVAL+1 LCDDOTCK LCDD ⎛⎞ VBP LINEVAL VFP 1++ +()= HOZVAL Horizontal_display_size LINEVAL Vertical_display_size 1 –= HOZVAL Horizontal_display_size 1 –= LINEVAL Vertical_display_size 1 –= flcd_pclk HOZVAL 5+() flcd_vsync LINEVAL 1+()×()×=

6242E–ATARM–11-Sep09 AT91SAM9261S The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The LINECNT field decreases by one unit at each falling edge of LCDHSYNC.

38.5.2.10 Display

This block is used to configure the polarity of the data and control signals. The polarity of all clock signals can be configured by LCDCON2[12:8] register setting. This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and off by software the LCD module. This signal is controlled by the PWRCON register and respects the number of frames configured in the GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the write access to LCD_PWR field (PWRCON[0]) and the activation/deactivation of lcd_pwr signal. The minimum value for the GUARD_TIME field is one frame. This gives the DMA Controller enough time to fill the FIFOs before the start of data transfer to the LCD.

38.5.2.11 PWM

This block generates the LCD co ntrast control signal (LCDCC) to make possible the control of the display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog voltage with a simple passive filter. The PWM module has a free-running counter whose value is compared against a compare reg- ister (CONTRAST_VAL register). If the value in the counter is less than that in the register, the output brings the value of the polarity (POL) bit in the PWM control register: CONTRAST_CTR. Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width propor- tional to the value in the compare register is generated. Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles. Thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) × VDD can be obtained (for the positive polarity case, or between (1/256) × VDD and VDD for the negative polarity case). Other voltage values can be obtained by adding active external circuitry. For PWM mode, the frequency of the counter can be adjusted to four different values using field PS of CONTRAST_CTR register.

38.5.3 LCD Interface

The LCD Controller interfaces with the LCD Module through the LCD Interface ( Table 38-11 on page 608 ). The Controller supports the following interface configurations: 24-bit TFT single scan, 16-bit STN Dual Scan Mono (Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit sin- gle scan Mono (Color). A 4-bit single scan STN display us es 4 parallel data lines to shift data to successive single hori- zontal lines one at a time until the entire frame has been shifted and transferred. The 4 LSB pins of LCD Data Bus (LCDD [3:0]) can be directly connected to the LCD driver; the 20 MSB pins (LCDD [23:4]) are not used. HFP f LCDDOTCK

6242E–ATARM–11-Sep09 AT91SAM9261S An 8-bit single scan STN display uses 8 parallel data lines to shift data to successive single hor- izontal lines one at a time until the entire frame has been shifted and transferred. The 8 LSB pins of LCD Data Bus (LCDD [7:0]) can be directly connected to the LCD driver; the 16 MSB pins (LCDD [23:8]) are not used. An 8-bit Dual Scan STN display uses two sets of 4 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[3:0] is connected to the upper panel data lines and the bus LCDD[7:4] is connected to the lower panel data lines. The re st of the LCD Data Bus lines (LCDD[23:8]) are not used. A 16-bit Dual Scan STN display uses two sets of 8 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[7:0] is connected to the upper panel data lines and the bus LCDD[15:8] is connected to the lower panel data lines. The rest of the LCD Data Bus lines (LCDD[23:16]) are not used. STN Mono displays require one bit of image data per pixel. STN Color displays require three bits (Red, Green and Blue) of image data per pixel, resu lting in a horizontal shift register of length three times the number of pixels per horizontal line. This RGB or Monochrome data is shifted to the LCD driver as consecutive bits via the parallel data lines. A TFT single scan display uses up to 24 parallel data lines to shift data to successive horizontal lines one at a time until the entire frame has been shifted and transferred. The 24 data lines are divided in three bytes that define the color shade of each color component of each pixel. The LCDD bus is split as LCDD[23:16] for the blue component, LCDD[15:8] for the green component and LCDD[7:0] for the red component. If the LCD Module has lower color resolution (fewer bits per color component), only the most significant bits of each component are used. All these interfaces are shown in Figure 38-6 to Figure 38-10. Figure 38-6 on page 603 shows the 24-bit single scan TFT display timing; Figure 38-7 on page 604 shows the 4-bit single scan STN display timing for monochrome and color modes; Figure 38-8 on page 605 shows the 8-bit single scan STN display timing for monochrome and color modes; Figure 38-9 on page 606 shows the 8-bit Dual Scan STN display timing for monochrome and color modes; Figure 38-10 on page 607 shows the 16-bit Dual Scan STN display timing for monochrome and color modes. Figure 38-6. TFT Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [24:16] LCDD [15:8] LCDD [7:0]

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-7. Single Scan Monochrome and Color 4-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] LCDD [2] LCDD [1] LCDD [0] LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] LCDD [2] LCDD [1] LCDD [0]

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-8. Single Scan Monochrome and Color 8-bit Panel Timing (First Line Expanded View) LCDD [7] LCDD [6] LCDD [5] LCDD [4] P10 P11 LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] P13 P12 P14 P15 LCDD [3] LCDD [2] LCDD [1] LCDD [0] LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-9. Dual Scan Monochrome and Color 8-bit Panel Timing (First Line Expanded View) LCDD [7] LCDD [6] LCDD [5] LCDD [4] LP1 LP0 LP5 LP4 LP6 LP7 LCDD [7] LCDD [6] LCDD [5] LCDD [4] LG0 LR0 LB0 LR1 LB1 LG1 LR2 LG2 LCDD [3] LCDD [2] LCDD [1] LCDD [0] UP1 UP0 UP2 UP3 UP5 UP4 UP6 UP7 LCDD [3] LCDD [2] LCDD [1] LCDD [0] UG0 UR0 UB0 UR1 UB1 UG1 UR2 UG2 Lower Pane Upper Pane Lower Pane Upper Pane LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 38-10. Dual Scan Monochrome and Color 16-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [15] LCDD [14] LCDD [13] LCDD [12] LP1 LP0 LP2 LP3 LP9 LP8 LP10 LP11 LCDD [15] LCDD [14] LCDD [13] LCDD [12] LG0 LR0 LB0 LR1 LR3 LB2 LG3 LB3 LCDD [11] LCDD [10] LCDD [9] LCDD [8] LP5 LP4 LP6 LP7 LP13 LP12 LP14 LP15 LCDD [11] LCDD [10] LCDD [9] LCDD [8] LB1 LG1 LR2 LG2 LG4 LR4 LB4 LR5 LCDD [7] LCDD [6] LCDD [5] LCDD [4] UG0 UR0 UB0 UR1 UR3 UB2 UG3 UB3 LCDD [3] LCDD [2] LCDD [1] LCDD [0] UB1 UG1 UR2 UG2 UG4 UR4 UB4 UR5 Lower Panel Upper Panel LCDD [7] LCDD [6] LCDD [5] LCDD [4] UP1 UP0 UP2 UP3 UP9 UP8 UP10 UP11 LCDD [3] LCDD [2] LCDD [1] LCDD [0] UP5 UP4 UP6 UP7 UP13 UP12 UP14 UP15 Lower Panel Upper Panel LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK

6242E–ATARM–11-Sep09 AT91SAM9261S Table 38-11. LCD Signal Multiplexing LCD Data Bus 4-bit STN Single Scan (mono, color) 8-bit STN Single Scan (mono, color) 8-bit STN Dual Scan (mono, color) 16-bit STN Dual Scan (mono, color) 24-bit TFT 16-bit TFT LCDD[23] LCD_BLUE7 LCD_BLUE4 LCDD[22] LCD_BLUE6 LCD_BLUE3 LCDD[21] LCD_BLUE5 LCD_BLUE2 LCDD[20] LCD_BLUE4 LCD_BLUE1 LCDD[19] LCD_BLUE3 LCD_BLUE0 LCDD[18] LCD_BLUE2 Intensity Bit LCDD[17] LCD_BLUE1 LCDD[16] LCD_BLUE0 LCDD[15] LCDLP7 LCD_GREEN7 LCD_GREEN4 LCDD[14] LCDLP6 LCD_GREEN6 LCD_GREEN3 LCDD[13] LCDLP5 LCD_GREEN5 LCD_GREEN2 LCDD[12] LCDLP4 LCD_GREEN4 LCD_GREEN1 LCDD[11] LCDLP3 LCD_GREEN3 LCD_GREEN0 LCDD[10] LCDLP2 LCD_GREEN2 Intensity Bit LCDD[9] LCDLP1 LCD_GREEN1 LCDD[8] LCDLP0 LCD_GREEN0 LCDD[7] LCD7 LCDLP3 LCDUP7 LCD_RED7 LCD_RED4 LCDD[6] LCD6 LCDLP2 LCDUP6 LCD_RED6 LCD_RED3 LCDD[5] LCD5 LCDLP1 LCDUP5 LCD_RED5 LCD_RED2 LCDD[4] LCD4 LCDLP0 LCDUP4 LCD_RED4 LCD_RED1 LCDD[3] LCD3 LCD3 LCDUP3 LCDUP3 LCD_RED3 LCD_RED0 LCDD[2] LCD2 LCD2 LCDUP2 LCDUP2 LCD_RED2 Intensity Bit LCDD[1] LCD1 LCD1 LCDUP1 LCDUP1 LCD_RED1 LCDD[0] LCD0 LCD0 LCDUP0 LCDUP0 LCD_RED0

6242E–ATARM–11-Sep09 AT91SAM9261S

38.6 Interrupts

The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are:  DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer.  FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty.  FIFO overwrite IRQ. Generated when the DMA Co ntroller tries to write a word in the FIFO while the FIFO is full.  DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base Address pointers. This IRQ can be used to implement a double-buffer technique. For more information, see “Double-buffer Technique” on page 610.  End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached and the DMA Controller is in inactive state.  End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of the current frame is reached and the DMA Controller is in inactive state. Each IRQ can be individually enabled, disabled or cleared, in the LCD_IER (Interrupt Enable Register), LCD_IDR (Interrupt Disable Register ) and LCD_ICR (Interrupt Clear Register) regis- ters. The LCD_IMR register contains the mask value for each IRQ source and the LDC_ISR contains the status of each IRQ source. A more detailed description of these registers can be found in “LCD Controller (LCDC) User Interface” on page 613.

38.7 Configuration Sequence

The DMA Controller starts to transfer image dat a when the LCDC Core is activated (Write to LCD_PWR field of PWRCON register). Thus, t he user should config ure the LCDC Core and configure and enable the DMA Controller prior to activation of the LCD Controller. In addition, the image data to be shows should be available when the LCDC Core is activated, regardless of the value programmed in the GUARD_TIME field of the PWRCON register. To disable the LCD Controller, the user should disable the LCDC Core and then disable the DMA Controller. The user should not enable LIP again until the LCDC Core is in IDLE state. This is checked by reading the LCD_BUSY bit in the PWRCON register. The initialization sequence that the user should follow to make the LCDC work is:  Create or copy the first image to show in the display buffer memory.  If a palletized mode is used, create and store a palette in the internal LCD Palette memory(See “Palette” on page 594.  Configure the LCD Controller Core without enabling it: – LCDCON1 register: Program the C LKVAL and BYP ASS fields: these fields control the pixel clock divisor that is used to generate the pixel clock LCDDOTCK. The value to program depends on the LCD Core clock and on the type and size of the LCD Module used. There is a minimum value of the LCDDOTCK clock period that depends on the LCD Controller Configuration, this minimum value can be found in Table 38-10 on page 598. The equations that are used to calculate the value of the pixel clock divisor can be found at the end of the section “Timegen” on page 597

6242E–ATARM–11-Sep09 AT91SAM9261S – LCDCON2 register: Program its fields fo llowing their descriptions in the LCD Controller User Interface section below and considering the type of LCD module used and the desired working mode. Consider that not all combinations are possible. – LCDTIM1 and LCDTIM2 registers: Program their fields according to the datasheet of the LCD module used and with the help of the Timegen section in page 10. Note that some fields are not applicable to STN modules and must be programmed with 0 values. Note also that there is a limitation on the minimum value of VHDL Y , HPW, HBP that depends on the configuration of the LCDC. – LCDFRMCFG register: program the dimensions of the LCD module used. – LCDFIFO register: To program it, use the formula in section “FIFO” on page 592 – DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules. They are loaded with recommended patterns at reset, so it is not necessary to write anything on them. They can be used to improve the image quality in the display by tuning the patterns in each application. – PWRCON Register: this register controls the power-up sequence of the LCD, so take care to use it properly. Do not enable the LCD (writing a 1 in LCD_PWR field) until the previous steps and the configuration of the DMA have been finished. – CONTRAST_CTR and CONTRAST_VAL: use this registers to adjust the contrast of the display, when the LCDCC line is used.  Configure the DMA Controller. The user should configure the base address of the display buffer memory, the size of the AHB transaction and the size of the display image in memory. When the DMA is configured the user should enable the DMA. To do so the user should configure the following registers: – DMABADDR1 and DMABADDR2 registers: In single scan mode only DMABADDR1 register must be configured with the base address of the display buffer in memory. In dual scan mode DMABADDR1 should be configured with the base address of the Upper Panel display buffer and DMABADDR2 should be configured with the base address of the Lower Panel display buffer. – DMAFRMCFG register: Program the FRMSIZE field. Note that in dual scan mode the vertical size to use in the calculation is that of each panel. Respect to the BRSTLN field, a recommended value is a 4-word burst. – DMACON register: Once both the LCD Controller Core and the DMA Controller have been configured, enable the DMA Controller by writing a “1” to the DMAEN field of this register.  Finally, enable the LCD Controller Core by writing a “1” in the LCD_PWR field of the PWRCON register and do any other action that may be required to turn the LCD module on.

38.8 Double-buffer Technique

The double-buffer technique is used to avoid flickering while the frame being displayed is updated. Instead of using a single buffer, there are two different buffers, the backbuffer (back- ground buffer) and the primary buffer (the buffer being displayed). The host updates the backbuffer while the LCD Controller is displaying the primary buffer. When the backbuffer has been updated the host updates the DMA Base Address registers. When using a Dual Panel LCD Module, both base address pointers should be updated in the same frame. There are two possibilities:

6242E–ATARM–11-Sep09 AT91SAM9261S  Check the DMAFRMPTx register to ensure that there is enough time to update the DMA Base Address registers before the end of frame.  Update the Frame Base Address Registers when the End Of Frame IRQ is generated. Once the host has updated the Frame Base Address Registers and the next DMA end of frame IRQ arrives, the backbuffer and the primary buffer are swapped and the host can work with the new backbuffer.

38.9 Register Configuration Guide

Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. PMC_SCER = 1 << 17;//LCDC HCLK = HCK1

38.9.1 STN Mode Example

STN color (R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 Mhz Data rate: 320*240*70*3/8 = 2.016 MHz HOZVAL= ((3*320)/8 ) - 1 LINEVAL= 240 -1 CLKVAL = (60 MHz/ (2*2.016 MHz)) - 1= 14 LCDCON1= CLKVAL << 12 LCDCON2 = LITTLEENDIAN | SINGLESCAN | STNCOLOR | DISP8BIT| PS8BPP; LCDTIM1 = 0; LCDFRMCFG = (HOZVAL << 21) | LINEVAL;

38.9.2 TFT Mode Example

This example is based on the NEC TFT color LCD module NL6448BC20-08 TFT 640*480, 16-bit single scan, 60 frames/sec, pixel clock frequency = [21MHz..29MHz] with a typical value = 25.175 MHz. The Master clock must be (2*(n + 1))*pixel clock frequency HOZVAL = 640 - 1 LINEVAL = 480 - 1 If Master clock is 50 MHz CLKVAL = (50 MHz/ (2*25.175 MHz)) - 1= 0 VFP = (12 -1), VBP = (31-1), VPW = (2-1), VHDLY= (2-1)

6242E–ATARM–11-Sep09 AT91SAM9261S LCDCON1= CLKVAL << 12 LCDCON2 = LITTLEENDIAN | CLKMOD | INVERT_CLK | INVERT_LINE | INVERT_FRM | PS16BPP | SINGLESCAN | TFT LCDTIM1 = VFP | (VBP << 8) | (VPW << 16) | (VHDLY << 24) LCDTIM2 = HBP | (HPW << 8) | (HFP << 21) LCDFRMCFG = (HOZVAL << 21) | LINEVAL

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10 LCD Controller (LCDC) User Interface

Table 38-12. Register Mapping Offset Register Name Access Reset 0x0 DMA Base Address Register 1 DMABADDR1 Read-write 0x00000000 0x4 DMA Base Address Register 2 DMABADDR2 Read-write 0x00000000 0x8 DMA Frame Pointer Register 1 DMAFRMPT1 Read-only 0x00000000 0xC DMA Frame Pointer Register 2 DMAFRMPT2 Read-only 0x00000000 0x10 DMA Frame Address Register 1 DMAFRMADD1 Read-only 0x00000000 0x14 DMA Frame Address Register 2 DMAFRMADD2 Read-only 0x00000000 0x18 DMA Frame Configuration Regi ster DMAFRMCFG Read-write 0x00000000 0x1C DMA Control Register DMACON Read-write 0x00000000 0x800 LCD Control Register 1 LCDCON1 Read-write 0x00002000 0x804 LCD Control Register 2 LCDCON2 Read-write 0x00000000 0x808 LCD Timing Register 1 LCDTIM1 Read-write 0x00000000 0x80C LCD Timing Register 2 LCDTIM2 Read-write 0x00000000 0x810 LCD Frame Configuration Register LCDFRMCFG Read-write 0x00000000 0x814 LCD FIFO Register LCDFIFO Read-write 0x00000000 0x818 Reserved – – – 0x81C Dithering Pattern DP1_2 DP1_2 Read-write 0xA5 0x820 Dithering Pattern DP4_7 DP4_7 Read-write 0x5AF0FA5 0x824 Dithering Pattern DP3_5 DP3_5 Read-write 0xA5A5F 0x828 Dithering Pattern DP2_3 DP2_3 Read-write 0xA5F 0x82C Dithering Pattern DP5_7 DP5_7 Read-write 0xFAF5FA5 0x830 Dithering Pattern DP3_4 DP3_4 Read-write 0xFAF5 0x834 Dithering Pattern DP4_5 DP4_5 Read-write 0xFAF5F 0x838 Dithering Pattern DP6_7 DP6_7 Read-write 0xF5FFAFF 0x83C Power Control Register PWRCON Read-write 0x0000000e 0x840 Contrast Control Register CONTRAST_CTR Read-write 0x00000000 0x844 Contrast Value Register CONTRAST_VAL Read-write 0x00000000 0x848 LCD Interrupt Enable Register LCD_IER Write-only 0x0 0x84C LCD Interrupt Disable Register LCD_IDR Write-only 0x0 0x850 LCD Interrupt Mask Register LCD_IMR Read-only 0x0 0x854 LCD Interrupt Status Register LCD_ISR Read-only 0x0 0x858 LCD Interrupt Clear Register LCD_ICR Write-only 0x0 0xC00 Palette entry 0 LUT ENTRY 0 Read-write 0xC04 Palette entry 1 LUT ENTRY 1 Read-write 0xC08 Palette entry 2 LUT ENTRY 2 Read-write 0xC0C Palette entry 3 LUT ENTRY 3 Read-write 0xFFC Palette entry 255 LUT ENTRY 255 Read-write

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.1 DMA Base Address Register 1

Name: DMABADDR1 Address:0x00600000 Access: Read-write Reset value: 0x00000000  BADDR-U Base Address for the upper panel in dual scan mode. Base Address for the complete frame in single scan mode.

38.10.2 DMA Base Address Register 2

Name: DMABADDR2 Address:0x00600004 Access: Read-write Reset value: 0x00000000  BADDR-L Base Address for the lower panel in dual scan mode only. 31 30 29 28 27 26 25 24 BADDR-U 23 22 21 20 19 18 17 16 BADDR-U 15 14 13 12 11 10 9 8 BADDR-U 76543210 BADDR-U 0 0 31 30 29 28 27 26 25 24 BADDR-L 23 22 21 20 19 18 17 16 BADDR-L 15 14 13 12 11 10 9 8 BADDR-L 76543210 BADDR-L

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.3 DMA Frame Pointer Register 1

Name: DMAFRMPT1 Address:0x00600008 Access: Read-only Reset value: 0x00000000 F R M P T - U Current value of frame pointer for the upper panel in dual scan mode. Current value of frame pointer for the complete frame in single scan mode. Down count from FRMSIZE to 0. Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame). It can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –F R M P T - U 15 14 13 12 11 10 9 8 FRMPT -U 76543210 FRMPT -U

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.4 DMA Frame Pointer Register 2

Name: DMAFRMPT2 Address:0x0060000C Access: Read-only Reset value: 0x00000000 F R M P T - L Current value of frame pointer for the Lower panel in dual scan mode only. Down count from FRMSIZE to 0. Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame). It can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 -F R M P T - L 15 14 13 12 11 10 9 8 FRMPT -L 76543210 FRMPT -L

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.5 DMA Frame Address Register 1

Name: DMAFRMADD1 Address:0x00600010 Access: Read-only Reset value: 0x00000000  FRMADD-U Current value of frame address for the upper panel in dual scan mode. Current value of frame address for the complete frame in single scan. Note: This register is read-only and contains the current val ue of the last DMA transaction in the bus for the panel/frame. 31 30 29 28 27 26 25 24 FRMADD-U 23 22 21 20 19 18 17 16 FRMADD-U 15 14 13 12 11 10 9 8 FRMADD-U 76543210 FRMADD-U

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.6 DMA Frame Address Register 2

Name: DMAFRMADD2 Address:0x00600014 Access: Read-only Reset value: 0x00000000  FRMADD-L Current value of frame address for the lower panel in single scan mode only. Note: This register is read-only and contains the current va lue of the last DMA transaction in the bus for the panel. 31 30 29 28 27 26 25 24 FRMADD-L 23 22 21 20 19 18 17 16 FRMADD-L 15 14 13 12 11 10 9 8 FRMADD-L 76543210 FRMADD-L

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.7 DMA Frame C onfiguration Register

Name: DMAFRMCFG Address:0x00600018 Access: Read-write Reset value: 0x00000000  FRMSIZE: Frame Size In single scan mode, this is the frame size in words. In dual scan mode, this is the size of each panel.  BRSTLN: Burst Length Program with the desired burst length - 1 31 30 29 28 27 26 25 24 –B R S T L N 23 22 21 20 19 18 17 16 –F R M S I Z E 15 14 13 12 11 10 9 8 FRMSIZE 76543210 FRMSIZE

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.8 DMA Control Register

Name: DMACON Address:0x0060001C Access: Read-write Reset value: 0x00000000  DMAEN: DMA Enable 0: DMA is disabled. 1: DMA is enabled.  DMARST: DMA Reset (Write-only) 0: No effect. 1: Reset DMA module. DMA Module should be reset only when disabled and in idle state.  DMABUSY: DMA Busy 0: DMA module is idle. 1: DMA module is busy (doing a transaction on the AHB bus). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – - - DMABUSY DMARST DMAEN

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.9 LCD Control Register 1

Name: LCDCON1 Address:0x00600800 Access: Read-write, except LINECNT: Read-only Reset value: 0x00002000  BYPASS: Bypass LCDDOTCK divider 0: The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1: The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.  CLKVAL: Clock divider 9-bit divider for pixel clock (LCDDOTCK) frequency.  LINECNT: Line Counter (Read-only) Current Value of 11-bit line counter. Down count from LINEVAL to 0. 31 30 29 28 27 26 25 24 LINECNT 23 22 21 20 19 18 17 16 LINECNT CLKVAL 15 14 13 12 11 10 9 8 C L K V A L –––– 76543210 Pixel_clock system_clock CLKVAL( 1 )+ 2×⁄=

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.10 LCD Control Register 2

Name: LCDCON2 Address:0x00600804 Access: Read-write Reset value: 0x0000000  DISTYPE: Display Type  SCANMOD: Scan Mode 0: Single Scan 1: Dual Scan  IFWIDTH: Interface width (STN) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CLKMOD – – INVDVAL INVCLK INVLINE INVFRAME INVVD 76543210 PIXELSIZE IFWIDTH SCANMOD DISTYPE DISTYPE 0 0 STN Monochrome 0 1 STN Color

10 T F T

0 0 4-bit (Only valid in single scan STN mono or color) 0 1 8-bit (Only valid in STN mono or Color) 1 0 16-bit (Only valid in dual scan STN mono or color)

6242E–ATARM–11-Sep09 AT91SAM9261S  PIXELSIZE: Bits per pixel  INVVD: LCDD polarity 0: Normal 1: Inverted  INVFRAME: LCDVSYNC polarity 0: Normal (active high) 1: Inverted (active low)  INVLINE: LCDHSYNC polarity 0: Normal (active high) 1: Inverted (active low)  INVCLK: LCDDOTCK polarity 0: Normal (LCDD fetched at LCDDOTCK falling edge) 1: Inverted (LCDD fetched at LCDDOTCK rising edge)  INVDVAL: LCDDEN polarity 0: Normal (active high) 1: Inverted (active low)  CLKMOD: LCDDOTCK mode 0: LCDDOTCK only active during active display period 1: LCDDOTCK always active  MEMOR: Memory Ordering Format 00: Big Endian 10: Little Endian PIXELSIZE 0 0 0 1 bit per pixel 0 0 1 2 bits per pixel 0 1 0 4 bits per pixel 0 1 1 8 bits per pixel 1 0 0 16 bits per pixel 1 0 1 24 bits per pixel, packed (Only valid in TFT mode) 1 1 0 Reserved 1 1 1 Reserved

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.11 LCD Timing Configuration Register 1

Name: LCDTIM1 Address:0x00600808 Access: Read-write Reset value: 0x0000000  VFP: Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0. V B P : V e r t i c a l B a c k P o r c h In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to 0.  VPW: Vertical Synchronization pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal to (VPW+1) lines. In STN mode, these bits should be set to 0.  VHDLY: Vertical to horizontal delay In TFT mode, this is the delay between LCDVSYNC rising or fallin g edge and LCDHSYNC ri sing edge. Delay is (VHDLY+1) LCDDOTCK cycles. In STN mode, these bits should be set to 0. 31 30 29 28 27 26 25 24 –––– V H D L Y 23 22 21 20 19 18 17 16 –– V P W 15 14 13 12 11 10 9 8 VBP 76543210 VFP

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.12 LCD Timing Configuration Register 2

Name: LCDTIM2 Address:0x0060080C Access: Read-write Reset value: 0x0000000  HBP: Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is (HBP+1) LCDDOTCK cycles.  HPW: Horizontal synch ronization pulse width Width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is (HPW+1) LCDDOTCK cycles.  HFP: Horizontal Front Porch Number of idle LCDDOTCK cycles at the end of the line. Idle period is (HFP+2) LCDDOTCK cycles. 31 30 29 28 27 26 25 24 HFP 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– H P W 76543210 HBP

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.13 LCD Frame Configuration Register

Name: LCDFRMCFG Address:0x00600810 Access: Read-write Reset value: 0x0000000  LINEVAL: Vertical size of LCD module LINEVAL = (Vertical display size) - 1 In dual scan mode, vertical display size refers to the size of each panel.  HOZVAL: Horizontal size of LCD module In STN Mode: – HOZVAL = (Horizontal display size / Number of valid LCDD data line) - 1 – In STN monochrome mode, Horizontal display size = Number of horizontal pixels – In STN color mode, Horizontal display size = 3*Number of horizontal pixels – In 4-bit single scan or 8-bit dual scan STN display mode, number of valid LCDD data lines = 4 – In 8-bit single scan or 16-bit dual scan STN display mode, number of valid LCDD data lines = 8 – If the value calculated for HOZVAL with the above formula is not an integer, it must be rounded up to the next integer value. In TFT mode: – HOZVAL = Horizontal display size 31 30 29 28 27 26 25 24 HOZVAL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 LINEVAL

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.14 LCD FIFO Register

Name: LCDFIFO Address:0x00600814 Access: Read-write Reset value: 0x0000000  FIFOTH: FIFO Threshold Must be programmed with: FIFOTH = 512 - (2 x DMA_BURST_LENGTH + 3) where:  512 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode.  DMA_burst_length is the burst length of the transfers made by the DMA. Refer to “BRSTLN: Burst Length” on page 619. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FIFOTH 76543210 FIFOTH

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.15 Dithering Pattern DP1_2 Register

Name: DP1_2 Address:0x0060081C Access: Read-write Reset value: 0xA5  DP1_2: Pattern value for ½ duty cycle

38.10.16 Dithering Pattern DP4_7 Register

Name: DP4_7 Address:0x00600820 Access: Read-write Reset value: 0x5AF0FA5  DP4_7: Pattern value for 4/7 duty cycle 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 DP1_2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DP4_7 15 14 13 12 11 10 9 8 DP4_7 76543210 DP4_7

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.17 Dithering Pattern DP3_5 Register

Name: DP3_5 Address:0x00600824 Access: Read-write Reset value: 0xA5A5F  DP3_5: Pattern value for 3/5 duty cycle

38.10.18 Dithering Pattern DP2_3 Register

Name: DP2_3: Dithering Pattern DP2_3 Register Address:0x00600828 Access: Read-write Reset value: 0xA5F  DP2_3: Pattern value for 2/3 duty cycle 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DP3_5 76543210 DP3_5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 DP2_3

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.19 Dithering Pattern DP5_7 Register

Name: DP5_7: Address:0x0060082C Access: Read-write Reset value: 0xFAF5FA5  DP5_7: Pattern value for 5/7 duty cycle

38.10.20 Dithering Pattern DP3_4 Register

Name: DP3_4 Address:0x00600830 Access: Read-write Reset value: 0xFAF5  DP3_4: Pattern value for 3/4 duty cycle 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DP5_7 15 14 13 12 11 10 9 8 DP5_7 76543210 DP5_7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DP3_4 76543210 DP3_4

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.21 Dithering Pattern DP4_5 Register

Name: DP4_5 Address:0x00600834 Access: Read-write Reset value: 0xFAF5F  DP4_5: Pattern value for 4/5 duty cycle

38.10.22 Dithering Pattern DP6_7 Register

Name: DP6_7 Address:0x00600838 Access: Read-write Reset value: 0xF5FFAFF  DP6_7: Pattern value for 6/7 duty cycle 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DP4_5 76543210 DP4_5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DP6_7 15 14 13 12 11 10 9 8 DP6_7 76543210 DP6_7

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.23 Power Control Register

Name: PWRCON Address:0x0060083C Access: Read-write Reset value: 0x0000000e  LCD_PWR: LCD module power control 0 = lcd_pwr signal is low, other lcd_* signals are low. 0->1 = lcd_* signals activated, lcd_pwr is set high with the delay of GUARD_TIME frame periods. 1 = lcd_pwr signal is high, other lcd_* signals are active. 1->0 = lcd_pwr signal is low, other lcd_* signals are active, but are set low after GUARD_TIME frame periods.  GUARD_TIME Delay in frame periods between applying control signals to the LCD module and setting LCD_PWR high, and between set- ting LCD_PWR low and removing control signals from LCD module  LCD_BUSY Read-only field. If 1, it indicates that the LCD is busy (act ive and displaying data, in power on sequence or in power off sequence). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 GUARD_TIME LCD_PWR

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.24 Contrast Control Register

Name: CONTRAST_CTR Address:0x00600840 Access: Read-write Reset value: 0x00000000 P S This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows: P O L This bit defines the polarity of the output. If 1, the output pulses are high level (the output will be high whenever the value in the counter is less than the value in the compare register CONTRAST_VAL). If 0, the output pulses are low level. E N A When 1, this bit enables the operation of the PWM generator. When 0, the PWM counter is stopped. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– E N A P O L P S PS 0 0 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK. 0 1 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/2. 1 0 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/4. 1 1 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/8.

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.25 Contrast Value Register

Name: CONTRAST_VAL Address:0x00600844 Access: Read-write Reset value: 0x00000000 C V A L PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 CVAL

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.26 LCD Interrupt Enable Register

Name: LCD_IER Address:0x00600848 Access: Write-only Reset value: 0x0  LNIE: Line interrupt enable 0: No effect 1: Enable each line interrupt  LSTLNIE: Last line interrupt enable 0: No effect 1: Enable last line interrupt  EOFIE: DMA End of frame interrupt enable 0: No effect 1: Enable End Of Frame interrupt  UFLWIE: FIFO underflow interrupt enable 0: No effect 1: Enable FIFO underflow interrupt  OWRIE: FIFO overwrite interrupt enable 0: No effect 1: Enable FIFO overwrite interrupt  MERIE: DMA memory error interrupt enable 0: No effect 1: Enable DMA memory error interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – MERIE OWRIE UFLWIE - EOFIE LSTLNIE LNIE

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.27 LCD Interrupt Disable Register

Name: LCD_IDR Address:0x0060084C Access: Write-only Reset value: 0x0  LNID: Line interrupt disable 0: No effect 1: Disable each line interrupt  LSTLNID: Last line interrupt disable 0: No effect 1: Disable last line interrupt  EOFID: DMA End of frame interrupt disable 0: No effect 1: Disable End Of Frame interrupt  UFLWID: FIFO underflow interrupt disable 0: No effect 1: Disable FIFO underflow interrupt  OWRID: FIFO overwrite interrupt disable 0: No effect 1: Disable FIFO overwrite interrupt  MERID: DMA Memory error interrupt disable 0: No effect 1: Disable DMA Memory error interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – MERID OWRID UFLWID – EOFID LSTLNID LNID

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.28 LCD Interrupt Mask Register

Name: LCD_IMR Address:0x00600850 Access: Read-only Reset value: 0x0  LNIM: Line interrupt mask 0: Line Interrupt disabled 1: Line interrupt enabled  LSTLNIM: Last line interrupt mask 0: Last Line Interrupt disabled 1: Last Line Interrupt enabled  EOFIM: DMA End of frame interrupt mask 0: End Of Frame interrupt disabled 1: End Of Frame interrupt enabled  UFLWIM: FIFO underflow interrupt mask 0: FIFO underflow interrupt disabled 1: FIFO underflow interrupt enabled  OWRIM: FIFO overwrite interrupt mask 0: FIFO overwrite interrupt disabled 1: FIFO overwrite interrupt enabled  MERIM: DMA Memory error interrupt mask 0: DMA Memory error interrupt disabled 1: DMA Memory error interrupt enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –M E R I M O W R I M U F L W I M – EOFIM LSTLNIM LNIM

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.29 LCD Interrupt Status Register

Name: LCD_ISR Address:0x00600854 Access: Read-only Reset value: 0x0  LNIS: Line interrupt status 0: Line Interrupt not active 1: Line Interrupt active  LSTLNIS: Last line interrupt status 0: Last Line Interrupt not active 1: Last Line Interrupt active  EOFIS: DMA End of frame interrupt status 0: End Of Frame interrupt not active 1: End Of Frame interrupt active  UFLWIS: FIFO underflow interrupt status 0: FIFO underflow interrupt not active 1: FIFO underflow interrupt active  OWRIS: FIFO overwrite interrupt status 0: FIFO overwrite interrupt not active 1: FIFO overwrite interrupt active  MERIS: DMA Memory error interrupt status 0: DMA Memory error interrupt not active 1: DMA Memory error interrupt active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – MERIS OWRIS UFLWIS – EOFIS LSTLNIS LNIS

6242E–ATARM–11-Sep09 AT91SAM9261S

38.10.30 LCD Interrupt Clear Register

Name: LCD_ICR Address:0x00600858 Access: Write-only Reset value: 0x0  LNIC: Line interrupt clear 0: No effect 1: Clear each line interrupt  LSTLNIC: Last line interrupt clear 0: No effect 1: Clear Last line Interrupt  EOFIC: DMA End of frame interrupt clear 0: No effect 1: Clear End Of Frame interrupt  UFLWIC: FIFO underflow interrupt clear 0: No effect 1: Clear FIFO underflow interrupt  OWRIC: FIFO overwrite interrupt clear 0: No effect 1: Clear FIFO overwrite interrupt  MERIC: DMA Memory error interrupt clear 0: No effect 1: Clear DMA Memory error interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – MERIC OWRIC UFLWIC – EOFIC LSTLNIC LNIC

6242E–ATARM–11-Sep09 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S 39. AT91SAM9261S Electrical Characteristics

39.1 Absolute Maximum Ratings

39.2 DC Characteristics

The following characteristics are applicable to the operating temperature range: T A = -40°C to 85°C, unless otherwise specified. Table 39-1. Absolute Maximum Ratings* Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. Voltage on Input Pins Maximum Operating Voltage Maximum Operating Voltage (VDDOSC, VDDPLL, VDDIOM Table 39-2. DC Characteristics Symbol Parameter Conditions Min Typ Max Units VVDDCORE DC Supply Core 1.08 1.2 1.32 V VVDDBU DC Supply Backup 1.08 1.2 1.32 VVDDOSC DC Supply Oscillator 3.0 3.3 3.6 V VVDDPLL DC Supply PLL 3.0 3.3 3.6 V VVDDIOM DC Supply Memory I/Os 1.65 1.8 1.95 V 3.0 3.3 3.6 V VVDDIOP DC Supply Peripheral I/Os 2.7 3.3 3.6 V VIL Input Low-level Voltage VVDDIO from 3.0V to 3.6V -0.3 0.8 V VVDDIO from 1.65V to 1.95V -0.3 0.3 x V VDDIO V VIH Input High-level Voltage VVDDIO from 3.0V to 3.6V 2.0 V VDDIO+0.3V V VVDDIO from 1.65V to 1.95V 0.7 x V VDDIO VVDDIO +0.3V V VOL Output Low-level Voltage IO Max, VVDDIO from 3.0V to 3.6V 0.4 V CMOS (IO <0.3 mA) VVDDIO from 1.65V to 1.95V 0.1 V TTL (IO Max) VVDDIO from 1.65V to 1.95V 0.4 V

6242E–ATARM–11-Sep09 AT91SAM9261S

39.3 Power Consumption

 Power consumption of power supply in four different modes: Full Speed, Idle Mode, Quasi Static and Backup.  Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock.

39.3.1 Power Consumption versus Modes

The values in Table 39-3 and Table 39-4 on page 644 are measured values of power consump- tion with operating conditions as follows: V DDIOM = VDDIOP = 3.3V V DDPLL = VDDOSC = 3.3V  There is no consumption on the I/Os of the device. Figure 39-1. Measures Schematics VOH Output High-level Voltage IO Max, VVDDIO from 3.0V to 3.6V V VDDIO - 0.4 V CMOS (IO <0.3 mA) VVDDIO from 1.65V to 1.95V VVDDIO - 0.1 V TTL (IO Max) VVDDIO from 1.65V to 1.95V VVDDIO - 0.4 ILEAK Input Leakage Current Pullup resistors disabled ±1 µA CIN Input Capacitance 217-ba ll LFBGA Package 5.0 pF RPULLUP Pull-up Resistance PA0-PA31, PB0-PB31, PC0-PC31 70 100 175 kOhm IO Output Current PA0 -PA31, PB0-PB31, PC0-PC31, SHDN 8 mA ISC Static Current On VVDDCORE = 1.2V, MCK = 0 Hz, excluding POR TA = 25°C 245 µA All inputs driven TMS, TDI, TCK, NRST = 1 TA = 85°C 3000 On VVDDBU = 1.2V, Logic cells consumption, excluding POR T A = 25°C 1.13 µA All inputs driven WKUP = 0 T A = 85°C 9.8 Table 39-2. DC Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Units VDDCORE VDDBU AMP2 AMP1

6242E–ATARM–11-Sep09 AT91SAM9261S These figures represent the power consumption measured on the power supplies. Table 39-3. Power Consumption for Different Modes Mode Conditions Consumption Unit Full speed ARM Core clock is 188 MHz. MCK is 94 MHz. Dhrystone running in Icache. VDDCORE = 1.08V TA = 85° C onto AMP2 52.7 mA ARM Core clock is 240 MHz. MCK is 120 MHz. Dhrystone running in Icache. VDDCORE = 1.2V TA = 85° C onto AMP2 78.3 ARM Core clock is 240 MHz. MCK is 120 MHz. Dhrystone running in Icache. VDDCORE = 1.2V TA = 25° C onto AMP2 75.3 Idle(1) MCK is 96 MHz. ARM core in idle state, waiting an interrupt. Processor clock disabled VDDCORE = 1.08V TA = 85° C onto AMP2 12.0 mA MCK is 96 MHz. ARM core in idle state, waiting an interrupt. Processor clock disabled VDDCORE = 1.2V TA = 85° C onto AMP2 14.6 MCK is 96 MHz. ARM core in idle state, waiting an interrupt. Processor clock disabled VDDCORE = 1.2V TA = 25° C onto AMP2 10.9

6242E–ATARM–11-Sep09 AT91SAM9261S Note: 1. No SRAM access in Idle Mode. Quasi Static ARM Core clock is 500 Hz. MCK is 500 Hz VDDCORE = 1.08V TA = 85° C onto AMP2 2300 µA ARM Core clock is 500 Hz. MCK is 500 Hz VDDCORE = 1.2V TA = 85° C onto AMP2 2450 ARM Core clock is 500 Hz. MCK is 500 Hz VDDCORE = 1.2V TA = 25° C onto AMP2 260 Backup In Shutdown Mode VDDBU = 1.08V TA = 85° C onto AMP1 µA In Shutdown Mode VDDBU = 1.2V TA = 85° C onto AMP1 6.7 In Shutdown Mode VDDBU = 1.2V TA = 25° C onto AMP1 2.5 Table 39-4. Power Consumption by Peripheral (TA = 25⋅ C, VDDCORE = 1.2V) Peripheral Consumption Unit PIO Controller 4.5 µA/MHz USART 1.7 UHP 12.1 UDP 8.9 LCDC 40.2 TWI 2.1 SPI 9.5 MCI 12.9 SSC 15.3 Timer Counter Channels 3.0 Table 39-3. Power Consumption for Different Modes (Continued) Mode Conditions Consumption Unit

6242E–ATARM–11-Sep09 AT91SAM9261S

39.4 Clock Characteristics

39.4.1 Processor Clock Characteristics

39.4.2 Master Clock Characteristics

39.4.3 XIN Clock Characteristics

Note: 1. These characteristics apply only wh en the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register.) Table 39-5. Processor Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCPPCK) Processor Clock Frequency VDDCORE = 1.08V T = 85°C 188 MHz 1/(tCPPCK) Processor Clock Frequency VDDCORE = 1.2V T = 85°C 240 MHz Table 39-6. Master Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCPPCK) Master Clock Frequency VDDCORE = 1.08V T = 85°C 94 MHz 1/(tCPPCK) Master Clock Frequency VDDCORE = 1.2V T = 85°C 120 MHz Table 39-7. XIN Clock Electrical Characteristics Symbol Parameter Conditions Min Max Units 1/(tCPXIN) XIN Clock Frequency 50.0 MHz tCPXIN XIN Clock Period 20.0 ns tCHXIN XIN Clock High Half-period 0.4 x t CPXIN 0.6 x tCPXIN tCLXIN XIN Clock Low Half-period 0.4 x t CPXIN 0.6 x tCPXIN CIN XIN Input Capacitance (1) 25 pF RIN XIN Pulldown Resistor (1) 500 k Ω

6242E–ATARM–11-Sep09 AT91SAM9261S

39.5 Crystal Oscillat or Characteristics

The following characteristics are applicabl e to the operating temperature range: T A = -40°C to 85°C and worst case of power supply, unless otherwise specified. 39.5.1 32 kHz Oscillator Characteristics Notes: 1. R S is the equivalent series resistance, CL is the equivalent load capacitance. 2. C LEXT32 is determined by taking into account internal parasitic and package load capacitance. 3. Additional user load capacitan ce should be subtracted from CLEXT32. 39.5.2 32 kHz Crystal Characteristics Table 39-8. 32 kHz Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit 1/(tCP32KHz) Crystal Oscillator Frequency 32.768 kHz CCRYSTAL32 Crystal Load Capacitance Crystal @ 32.768 kHz 6 12.5 pF CLEXT32 (2) External Load Capacitance CCRYSTAL32 = 6 pF(3) 4p F CCRYSTAL32 = 12.5 pF(3) 17 pF Duty Cycle 40 60 % tST Startup Time VDDBU = 1.2V RS = 50 kΩ, CL = 6 pF(1) 400 ms VDDBU = 1.2V RS = 50 kΩ, CL = 12.5 pF(1) 900 ms VDDBU = 1.2V RS = 100 kΩ, CL = 6pF(1) 600 ms VDDBU = 1.2V RS = 100 kΩ, CL = 12.5 pF(1) 1200 ms Table 39-9. 32 kHz Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resistor Rs Crystal @ 32.768 kHz 50 100 k Ω CM Motional Capacitance Crystal @ 32.768 kHz 3 fF CS Shunt Capacitance Crystal @ 32.768 kHz 2 pF XIN32 XOUT32 CLEXT32CLEXT32 CCRYSTAL32 AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S

39.5.3 Main Oscillator Characteristics

Notes: 1. C S is the shunt capacitance. 3. R S = 50 to 100 Ω ; CS = 2.0 to 2.5 pF; CM = 4 to 3 fF (typ, worst case). 4. R S = 25 to 50 Ω ; CS = 2.5 to 3.0 pF; CM = 7 to 5 fF (typ, worst case). 5. R S = 20 to 50 Ω ; CS = 3.2 to 4.0 pF; CM = 10 to 8 fF (typ, worst case). 6. Additional user load capacitan ce should be subtracted from CLEXT. 7. C LEXT is determined by taking into account internal parasitic and package load capacitance. Table 39-10. Main Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit 1/(tCPMAIN) Crystal Oscillator Frequency 3 16 20 MHz CCRYSTAL Crystal Load Capacitance 12.5 15 17.5 pF CLEXT (7) External Load Capacitance CCRYSTAL = 12.5 pF(6) 15 pF CCRYSTAL = 15 pF(6) 18 CCRYSTAL = 17.5 pF(6) 22 Duty Cycle 40 50 60 % tST Startup Time VDDPLL = 3 to 3.6V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 8 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz ms I DDST Standby Current Consumption Standby mode 1 µA PON Drive Level @ 3 MHz 15 µW @ 8 MHz 30 @ 16 MHz 50 @ 20 MHz 50 I DD ON Current Dissipation @ 3 MHz(2) 150 250 µA @ 8 MHz(3) 300 530 @ 16 MHz(4) 300 530 @ 20 MHz(5) 450 650 XIN XOUT CLEXTCLEXT CCRYSTAL AT91SAM9261S

6242E–ATARM–11-Sep09 AT91SAM9261S

39.5.4 Crystal Characteristics

39.5.5 PLL Characteristics

Note: 1. Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. Table 39-11. Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resistor Rs Fundamental @ 3 MHz 200 Ω Fundamental @ 8 MHz 100 Fundamental @ 16 MHz 80 Fundamental @ 20 MHz 50 CM Motional Capacitance 8f F CS Shunt Capacitance 7p F Table 39-12. Phase Lock Loop Characteristics Symbol Parameter Conditions Min Typ Max Unit FOUT Output Frequency Field OUT of CKGR_PLL is 00 80 200 MHz Field OUT of CKGR_PLL is 10 190 240 MHz FIN Input Frequency 1 32 MHz IPLL Current Consumption Active mode 3 mA Standby mode 1 µA

6242E–ATARM–11-Sep09 AT91SAM9261S

39.6 USB Transceiver Characteristics

39.6.1 Electrical Characteristics

Table 39-13. USB Transceiver Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit Input Levels VIL Low Level 0.8 V VIH High Level 2.0 V VDI Differential Input Sensitivity |(D+) - (D-)| 0.2 V VCM Differential Input Common Mode Range 0.8 2.5 V CIN Transceiver capacitance Capacitance to ground on each line 9.18 pF I Hi-Z State Data Line Leakage 0V < V IN < 3.3V - 10 + 10 µA REXT Recommended External USB Series Resistor In series with each USB pin with ±5% 27 Ω Output Levels V OL Low Level Output Measured with RL of 1.425 kΩ tied to 3.6V 0.0 0.3 V VOH High Level Output Measured with RL of 14.25 kΩ tied to GND 2.8 3.6 V VCRS Output Signal Crossover Voltage Measure conditions described in Figure 39-2 1.3 2.0 V Pull-up Resistor R PUI Bus Pull-up Resistor on Upstream Port (idle bus) 0.900 1.575 kOhm RPUA Bus Pull-up Resistor on Upstream Port (upstream port receiving) 1.425 3.090 kOhm

6242E–ATARM–11-Sep09 AT91SAM9261S

39.6.2 Switching Characteristics

Figure 39-2. USB Data Signal Rise and Fall Times

39.7 Core Power Supply POR Characteristics

39.7.1 Power Sequence Requirements

The AT91SAM9261S board design must comply with the power-up guidelines below to guaran- tee reliable operation of the device. Any deviation from these sequences may prevent the device from booting. Table 39-14. In Full Speed Symbol Parameter Conditions Min Typ Max Unit tFR Transition Rise Time C LOAD = 400 pF 75 300 ns tFE Transition Fall Time C LOAD = 400 pF 75 300 ns tFRFM Rise/Fall time Matching C LOAD = 400 pF 80 125 % Table 39-15. In Full Speed Symbol Parameter Conditions Min Typ Max Unit tFR Transition Rise Time C LOAD = 50 pF 4 20 ns tFE Transition Fall Time C LOAD = 50 pF 4 20 ns tFRFM Rise/Fall time Matching 90 111.11 % 10% 10% 90%VCRS tR tF Differential Data Lines Rise Time Fall Time Fosc = 6 MHz/750kHz REXT = 27 Ohms CloadBuffer (b) (a) Table 39-16. Power-On-Reset Characteristics Symbol Parameter Conditions Min Typ Max Units Vth+ Threshold Voltage Rising Minimum Slope of +2.0V/30ms 0.7 0.9 1.08 V Vth- Threshold Voltage Falling 0.6 0.8 1.0 V TRES Reset Time 50 170 300 µs

6242E–ATARM–11-Sep09 AT91SAM9261S

39.7.2 Power-Up Sequence

Figure 39-3. VDDCORE and VDDIO Constraints at Startup VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR.  VDDIOP must be ≥ to VIH (refer to DC characteristics Table 39-2 for more details) within (Tres + T1) after VDDCORE has reached Vth+.  VDDIOM must reach VOH (refer to DC characteristics table for more details) within (Tres +T1 +T2) after VDDCORE has reached Vth+ –T RES is a POR characteristic –T 1 = 3 x TSLCK – T2 = 16 x T SLCK As TSLCK is the period of the external 32.768 kHz oscillator. –T RES = 50 µs – T1 = 91.5 µs – T2 = 488 µs

39.8 EBI Timings

These timings are given for worst case Process, T° = 85°C and VDDCORE = Min. First column for VDDIOM in 1.8V Supply range (1.65V-1.95V) and 30 pF load capacitance. Second column for VDDIOM in 3.3V Supply range (3.0V-3.6V) and 50 pF load capacitance. VDD (V) Core Supply POR Output VDDIOtyp Vih Vt h+ t SLCK <--- Tres ---> VDDIO > Vih VDDCORE VDDIO < T1 > VDDCOREtyp Voh VDDIO > Voh

6242E–ATARM–11-Sep09 AT91SAM9261S Table 39-17. SMC Read Signals with Hold Settings Symbol Parameter Min Units VDDIOM Supply 1.8V 3.3V VDDCORE Supply 1.08V 1.2V 1.08V 1.2V NRD Controlled (READ_MODE = 1) SMC1 Data Setup before NRD High 13.5 10.6 10.7 8.5 ns SMC2 Data Hold after NRD High 0 0 0 0 ns SMC3 NRD High to NBS0/A0 Change (1) nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 ns SMC4 NRD High to NBS1 Change (1) nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.1 nrd hold length * tCPMCK + 0.1 ns SMC5 NRD High to NBS2/A1 Change (1) nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 nrd hold length * tCPMCK + 0.2 ns SMC6 NRD High to NBS3 Change (1) nrd hold length * tCPMCK + 0.1 nrd hold length * tCPMCK + 0.1 nrd hold length * tCPMCK + 0.1 nrd hold length * tCPMCK + 0.1 ns SMC7 NRD High to A2 - A25 Change (1) nrd hold length * tCPMCK - 0.5 nrd hold length * tCPMCK - 0.5 nrd hold length * tCPMCK - 0.7 nrd hold length * tCPMCK - 0.5 ns SMC8 NRD High to NCS Inactive (1) (nrd hold length - ncs rd hold length) * tCPMCK - 0.4 (nrd hold length - ncs rd hold length) * tCPMCK - 0.3 (nrd hold length - ncs rd hold length) * tCPMCK - 0.4 (nrd hold length - ncs rd hold length) * tCPMCK - 0.3 ns SMC9 NRD Pulse Width nrd pulse length * tCPMCK - 0.2 nrd pulse length * tCPMCK - 0.2 nrd pulse length * tCPMCK + 0.1 nrd pulse length * tCPMCK - 0.0 ns NCS Controlled (READ_MODE = 0) SMC10 Data Setup before NCS High 16.5 12.7 13.6 10.6 ns SMC11 Data Hold after NCS High 0 0 0 0 ns SMC12 NCS High to NBS0/A0 Change (1) ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 1.8 ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 1.8 ns SMC13 NCS High to NBS1 Change (1) ncs rd hold length * tCPMCK - 2.4 ncs rd hold length * tCPMCK - 1.7 ncs rd hold length * tCPMCK - 2.5 ncs rd hold length * tCPMCK - 1.8 ns SMC14 NCS High to NBS2/A1 Change (1) ncs rd hold length * tCPMCK - 2.5 ncs rd hold length * tCPMCK - 1.7 ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 1.8 ns SMC15 NCS High to NBS3 Change (1) ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 1.9 ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 1.9 ns

6242E–ATARM–11-Sep09 AT91SAM9261S Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”. Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold length”. SMC16 NCS High to A2 - A25 Change (1) ncs rd hold length * tCPMCK - 3.5 ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 3.6 ncs rd hold length * tCPMCK - 2.6 ns SMC17 NCS High to NRD Inactive (1) (ncs rd hold length - nrd hold length)* tCPMCK - 2.9 (ncs rd hold length - nrd hold length)* tCPMCK - 2.1 (ncs rd hold length - nrd hold length)* tCPMCK - 2.9 (ncs rd hold length - nrd hold length)* tCPMCK - 2.1 ns SMC18 NCS Pulse Width ncs rd pulse length * tCPMCK - 2.7 ncs rd pulse length * tCPMCK - 2.0 ncs rd pulse length * tCPMCK - 2.5 ncs rd pulse length * tCPMCK - 1.8 ns Table 39-17. SMC Read Signals with Hold Settings (Continued) Symbol Parameter Min Units VDDIOM Supply 1.8V 3.3V VDDCORE Supply 1.08V 1.2V 1.08V 1.2V Table 39-18. SMC Read Signals with No Hold Settings Symbol Parameter Min Units VDDIOM supply 1.8V 3.3V VDDCORE supply 1.08V 1.2V 1.08V 1.2V NRD Controlled (READ_MODE = 1) SMC19 Data Setup before NRD High 16.1 12.4 13.1 10.2 ns SMC20 Data Hold after NRD High 0 0 0 0 ns NCS Controlled (READ_MODE = 0) SMC21 Data Setup before NCS High 19.0 14.5 16.0 12.3 ns SMC22 Data Hold after NCS High 0 0 0 0 ns

6242E–ATARM–11-Sep09 AT91SAM9261S Table 39-19. SMC Write Signals with Hold Settings Symbol Parameter Min Units VDDIOM supply 1.8V 3.3V VDDCORE supply 1.08V 1.2V 1.08V 1.2V NWE Controlled (WRITE_MODE = 1) SMC23 Data Out Valid before NWE High (NWE pulse length) * tCPMCK - 3.8 (NWE pulse length) * tCPMCK - 2.9 (NWE pulse length) * tCPMCK - 2.7 (NWE pulse length) * tCPMCK - 2.1 ns SMC24 Data Out Valid after NWE High (1) NWE hold length * tCPMCK - 5.0 NWE hold length * tCPMCK - 4.1 NWE hold length * tCPMCK - 3.7 NWE hold length * tCPMCK - 3.1 ns SMC25 NWE High to NBS0/A0 Change (1) NWE hold length * tCPMCK - 0.2 NWE hold length * tCPMCK - 0.1 NWE hold length * tCPMCK - 0.2 NWE hold length * tCPMCK - 0.1 ns SMC26 NWE High to NBS1 Change (1) NWE hold length * tCPMCK - 0.1 NWE hold length * tCPMCK - 0.1 NWE hold length * tCPMCK - 0.1 NWE hold length * tCPMCK - 0.1 ns SMC29 NWE High to NBS2/A1 Change (1) NWE hold length * tCPMCK - 0.1 NWE hold length * tCPMCK - 0.0 NWE hold length * tCPMCK - 0.2 NWE hold length * tCPMCK - 0.1 ns SMC30 NWE High to NBS3 Change (1) NWE hold length * tCPMCK - 0.2 NWE hold length * tCPMCK - 0.2 NWE hold length * tCPMCK - 0.2 NWE hold length * tCPMCK - 0.2 ns SMC31 NWE High to A2 - A25 Change (1) NWE hold length * tCPMCK - 1.0 NWE hold length * tCPMCK - 0.9 NWE hold length * tCPMCK - 1.2 NWE hold length * tCPMCK - 0.8 ns SMC32 NWE High to NCS Inactive (1) (NWE hold length - ncs wr hold length)* tCPMCK - 0.9 (NWE hold length - ncs wr hold length)* tCPMCK - 0.7 (NWE hold length - ncs wr hold length)* tCPMCK - 0.9 (NWE hold length - ncs wr hold length)* tCPMCK - 0.7 ns SMC33 NWE Pulse Width NWE pulse length * tCPMCK - 0.4 NWE pulse length * tCPMCK - 0.3 NWE pulse length * tCPMCK - 0.1 NWE pulse length * tCPMCK - 0.1 ns NCS Controlled (WRITE_MODE = 0) SMC34 Data Out Valid before NCS High (ncs wr pulse length)* tCPMCK - 4.7 (ncs wr pulse length )* tCPMCK - 3.6 (ncs wr pulse length)* tCPMCK - 3.6 (ncs wr pulse length)* tCPMCK - 2.7 ns SMC35 Data Out Valid after NCS High (1) ncs wr hold length * tCPMCK - 7.5 ncs wr hold length * tCPMCK - 5.8 ncs wr hold length * tCPMCK - 6.2 ncs wr hold length * tCPMCK - 4.9 ns SMC36 NCS High to NWE Inactive (1) (ncs wr hold length - NWE hold length)* tCPMCK - 2.6 (ncs wr hold length - NWE hold length)* tCPMCK - 1.9 (ncs wr hold length - NWE hold length)* tCPMCK - 2.6 (ncs wr hold length - NWE hold length)* tCPMCK - 1.9 ns

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 39-4. SMC NCS Controlled Access Table 39-20. SMC Write Signals with No Hold Settings (NWE Controlled Only) Symbol Parameter Min Units VDDIOM supply 1.8V 3.3V VDDCORE supply 1.08V 1.2V 1.08V 1.2V SMC37 NWE Rising to A2-A25 Valid 3.2 3.2 2.6 2.6 ns SMC38 NWE Rising to NBS0/A0 Valid 3.2 3.2 2.6 2.6 ns SMC39 NWE Rising to NBS1 Change 3.1 3.1 2.5 2.5 ns SMC40 NWE Rising to A1/NBS2 Change 3.3 3.3 2.7 2.7 ns SMC41 NWE Rising to NBS3 Change 3.1 3.1 2.5 2.5 ns SMC42 NWE Rising to NCS Rising 3.1 3.1 2.5 2.5 ns SMC43 Data Out Valid before NWE Rising (NWE pulse length ) * tCPMCK - 3.8 (NWE pulse length) * tCPMCK - 2.9 (NWE pulse length) * tCPMCK - 2.7 (NWE pulse length) * tCPMCK - 2.1 ns SMC44 Data Out Valid after NWE Rising 2.8 2.8 2.5 2.5 ns SMC45 NWE Pulse Width NWE pulse length * tCPMCK - 0.4 NWE pulse length * tCPMCK - 0.3 NWE pulse length * tCPMCK - 0.1 NWE pulse length * tCPMCK - 0.1 ns NRD NCS D0 - D15 NWE A2-A25 A0/A1/NBS[3:0] SMC34 SMC35SMC10 SMC11 SMC16 SMC15 SMC22SMC21 SMC17 SMC18 SMC14 SMC13 SMC12 SMC18 SMC17 SMC16 SMC15 SMC14 SMC13 SMC12 SMC18 SMC36 SMC16 SMC15 SMC14 SMC13 SMC12

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 39-5. SMC Signals for NRD and NWR Controlled Access NRD NCS D0 - D31 NWR A2-A25 A0/A1/NBS[3:0] SMC7 SMC19 SMC20 SMC43 SMC37 SMC42 SMC8 SMC1 SMC2 SMC23 SMC24 SMC32 SMC7 SMC8 SMC6 SMC5 SMC4 SMC3 SMC9 SMC41 SMC40 SMC39 SMC38 SMC45 SMC9 SMC6 SMC5 SMC4 SMC3 SMC33 SMC30 SMC29 SMC26 SMC25 SMC31 SMC44

6242E–ATARM–11-Sep09 AT91SAM9261S

39.9 SDRAMC TImings

The timings that follow are given for a 10 pF load on SDCK and 50 pF on the databus. Table 39-21. SDRAMC Clock Signal Symbol Parameter Max Units1.8V Supply 3.3V Supply 1/(tCPSDCK) SDRAM Controller Clock Frequency MCK Maximum Clock Frequency See Table 39-6, “Master Clock Waveform Parameters” MHz Table 39-22. SDRAM Signals Symbol Parameter Min Units 1.8V Supply 3.3V Supply SDRAMC1 SDCKE High before SDCK Rising Edge tCPSDCK/2 - 0.8 tCPSDCK/2 - 0.8 ns SDRAMC2 SDCKE Low after SDCK Rising Edge tCPSDCK/2 - 0.3 tCPSDCK/2 - 0.4 ns SDRAMC3 SDCKE Low before SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.2 ns SDRAMC4 SDCKE High after SDCK Rising Edge tCPSDCK/2 - 0.2 tCPSDCK/2 - 0.2 ns SDRAMC5 SDCS Low before SDCK Rising Edge tCPSDCK/2 - 1.5 tCPSDCK/2 - 1.2 ns SDRAMC6 SDCS High after SDCK Rising Edge tCPSDCK/2 - 0.3 tCPSDCK/2 - 0.3 ns SDRAMC7 RAS Low before SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.2 ns SDRAMC8 RAS High after SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.4 ns SDRAMC9 SDA10 Change before SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.5 ns SDRAMC10 SDA10 Change after SDCK Rising Edge tCPSDCK/2 - 0.3 tCPSDCK/2 - 0.4 ns SDRAMC11 Address Change before SDCK Rising Edge tCPSDCK/2 - 3.6 tCPSDCK/2 - 3.7 ns SDRAMC12 Address Change after SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.5 ns SDRAMC13 Bank Change before SDCK Rising Edge tCPSDCK/2 - 3.3 tCPSDCK/2 - 3.3 ns SDRAMC14 Bank Change after SDCK Rising Edge tCPSDCK/2 - 0.5 tCPSDCK/2 - 0.5 ns

6242E–ATARM–11-Sep09 AT91SAM9261S SDRAMC15 CAS Low before SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.2 ns SDRAMC16 CAS High after SDCK Rising Edge tCPSDCK/2 - 0.3 tCPSDCK/2 - 0.3 ns SDRAMC17 DQM Change before SDCK Rising Edge tCPSDCK/2 - 3.4 tCPSDCK/2 - 3.3 ns SDRAMC18 DQM Change after SDCK Rising Edge tCPSDCK/2 - 0.5 tCPSDCK/2 - 0.5 ns SDRAMC19 D0-D15 in Setup before SDCK Rising Edge 1.4 1.4 ns SDRAMC20 D0-D15 in Hold after SDCK Rising Edge 0.1 0.0 ns SDRAMC21 D16-D31 in Setup before SDCK Rising Edge 1.8 1.8 ns SDRAMC22 D16-D31 in Hold after SDCK Rising Edge 0.0 0.0 ns SDRAMC23 SDWE Low before SDCK Rising Edge tCPSDCK/2 - 0.2 tCPSDCK/2 - 0.1 ns SDRAMC24 SDWE High after SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.4 ns SDRAMC25 D0-D15 Out Valid before SDCK Rising Edge tCPSDCK/2 - 1.3 tCPSDCK/2 - 1.1 ns SDRAMC26 D0-D15 Out Valid after SDCK Rising Edge tCPSDCK/2 - 0.6 tCPSDCK/2 - 0.6 ns SDRAMC27 D16-D31 Out Valid before SDCK Rising Edge tCPSDCK/2 - 3.9 tCPSDCK/2 - 3.9 ns SDRAMC28 D16-D31 Out Valid after SDCK Rising Edge tCPSDCK/2 - 0.5 tCPSDCK/2 - 0.5 ns Table 39-22. SDRAM Signals (Continued) Symbol Parameter Min Units 1.8V Supply 3.3V Supply

6242E–ATARM–11-Sep09 AT91SAM9261S Figure 39-6. SDRAM Signals Relative to SDCK RAS A0 - A9, A11 - A13 D0 - D15 Read SDCK SDA10 D0 - D15 to Write SDRAMC1 SDCKE SDRAMC2 SDRAMC3 SDRAMC4 SDCS SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 CAS SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16 SDWE SDRAMC23 SDRAMC24 SDRAMC9 SDRAMC10SDRAMC9 SDRAMC10SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12SDRAMC11 SDRAMC12 BA0/BA1 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC17 SDRAMC18SDRAMC17 SDRAMC18 DQM0 - DQM3 SDRAMC19 SDRAMC20 D16 - D31 Read SDRAMC21 SDRAMC22 SDRAMC25 SDRAMC26 D16 - D31 to Write SDRAMC27 SDRAMC28

6242E–ATARM–11-Sep09 AT91SAM9261S

39.10 Peripheral Timings

39.10.1 SPI

Timings are given assuming a capacitance load on MISO, SPCK and MOSI. Figure 39-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) Figure 39-8. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) Table 39-23. Capacitance Load for MISO, SPCK and MOSI IO Supply Corner MAX STH 3.3V 40 pF 40 pF 1.8V 20 pF 20 pf SPCK MISO MOSI SPI2 SPI0 SPI1 SPCK MISO MOSI SPI5 SPI3 SPI4

6242E–ATARM–11-Sep09 AT91SAM9261S Table 39-24. SPI Timings Symbol Parameter Conditions Min Max Units Master Mode SPI0 MISO Setup time before SPCK rises STH corner 10.9 + 0.5*t CPMCK ns MAX corner 14.2 + 0.5*t CPMCK ns SPI1 MISO Hold time after SPCK rises STH corner -3.5 - 0.5* t CPMCK ns MAX corner -3.5 - 0.5* t CPMCK ns SPI2 SPCK rising to MOSI STH corner 0.3 ns MAX corner 0.4 ns SPI3 MISO Setup time before SPCK falls STH corner 11.1 + 0.5*t CPMCK ns MAX corner 14.4 + 0.5*t CPMCK ns SPI4 MISO Hold time after SPCK falls STH corner -3.5 - 0.5* t CPMCK ns MAX corner -3.5 - 0.5* t CPMCK ns SPI5 SPCK falling to MOSI STH corner 0.3 ns MAX corner 0.5 ns Slave Mode SPI6 SPCK falling to MISO STH corner 8.7 ns MAX corner 11.4 ns SPI7 MOSI Setup time before SPCK rises STH corner 1.0 ns MAX corner 1.1 ns SPI8 MOSI Hold time after SPCK rises STH corner 0.0 ns MAX corner -0.1 ns SPI9 SPCK rising to MISO STH corner 8.8 ns MAX corner 11.4 ns SPI10 MOSI Setup time before SPCK falls STH corner 0.9 ns MAX corner 1.0 ns SPI11 MOSI Hold time after SPCK falls STH corner -0.1 ns MAX corner 0.0 ns

6242E–ATARM–11-Sep09 AT91SAM9261S

39.10.2 MCI

The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (emp ty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming). These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card. Figure 39-11. MCI Timing Diagram Valid Data Valid Data Valid Data Valid Data Bus Clock CMD_DAT Input CMD_DAT Output 2 3 4 5 Table 39-25. MCI Timings Symbol Parameter Min Max Units 1/tCLOCK CLK frequency at Data transfer Mode (PP) 0 50 MHz 2 Input hold time 0.9 ns 3 Input setup time 0.2 ns 4 Output hold time 8.5 ns

5 Output setup time t

CLOCK-2.1 ns

6242E–ATARM–11-Sep09 AT91SAM9261S 40. AT91SAM9261S Mechanical Characteristics

40.1 Package Drawings

Figure 40-1. 217-ball LFBGA Package Drawing Table 40-1. Soldering Information (Substrate Level) Ball Land 0.43 mm ± 0.05 Solder Mask Opening 0.30 mm ± 0.05 Table 40-2. Device and 217-ball LFBGA Package Maximum Weight 450 mg Table 40-3. 217-ball LFBGA Package Characteristics Moisture Sensitivity Level 3 Table 40-4. Package Reference JEDEC Drawing Reference MO-205 JESD97 Classification e1

6242E–ATARM–11-Sep09 AT91SAM9261S

40.2 Soldering Profile

Table 40-5 gives the recommended soldering profile from J-STD-20. Note: It is recommended to apply a soldering temperature higher than 250°C. A maximum of three reflow passes is allowed per component. Table 40-5. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3 ⋅ C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5⋅ C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260 +0 ⋅ C Ramp-down Rate 6 ⋅ C/sec. max. Time 25⋅ C to Peak Temperature 8 min. max.

6242E–ATARM–11-Sep09 AT91SAM9261S 41. AT91SAM9261S Ordering Information Table 41-1. AT91SAM9261S Ordering Information Ordering Code Package Package Type Temperature Operating Range AT91SAM9261S-CJ BGA217 RoHS-compliant Industrial -40°C to 85°C AT91SAM9261SB-CU BGA217 RoHS-compliant Industrial -40°C to 85°C

6242E–ATARM–11-Sep09 AT91SAM9261S 42. AT91SAM9261S Errata

42.1 Marking

All devices are marked with the Atmel logo and the ordering code. Additional marking is as follows: where “ Y Y ” : m a n u f a c t o r y y e a r  “WW”: manufactory week  “V”: revision  “XXXXXXXXX”: lot number YYWW V XXXXXXXXX ARM

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2 AT91SAM9261S Errata - Revision A Parts

Refer to Section 42.1 “Marking” on page 667.

42.2.1 Main Oscillator

42.2.1.1 Main Oscillator: Spurious Malfunction of Main Oscillator

The main oscillator can exhibit sp urious malfunction as exhibited by the duty-cycle not perform- ing according to specification, missing main clock periods, or in the worst case, no main clock at all. The behavior does not alter over time. A device fully tested over the operating range (includ- ing power supply and temperat ure) in an application without exhibiting any malfunction will continue to function according to specifications. Problem Fix/Workaround Placing a series resistor of 470 Ω between XOUT and the crystal will fix the issue. The additional series resistor will not alter the device specif ication as documented in the datasheet, including the startup time and power consumption.

42.2.2 Battery Backup

42.2.2.1 Backup Overconsumption During AHB Masters Activity

Conditions: During AHB Masters activity (LCD DMA, USB Host DMA, etc.) the backup current can rise up to 12 µA @ 25⋅ C. Problem Fix/Workaround Figure 42-1 on page 668 shows how to feed the backup part of the chip from the battery only when the main power supply is off. In active mode, the clocks of unused peripherals should be disabled through the Power Management Controller to save power. Figure 42-1. Schematic 3V3 CR1225 CR1 MMBD1704A MN1 R1100D121C OUT1 VDD2 GND 3 R1 1K 100NF 100NF VDDBU

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2.3 Boot ROM

42.2.3.1 Boot ROM: NAND Flash Boot is Not Functional

NAND Flash Boot is not functional in this revision Problem Fix/Workaround None.

42.2.3.2 Boot ROM: Watchdog Disable

When AT91SAM9261S boots on internal ROM (BMS =1) the watchdog timer is disabled by soft- ware. Because the watchdog mode register is a “write once”, the system, designed to boot on an SPI DataFlash, cannot reuse the watchdog functionality. Problem Fix/Workaround If the watchdog feature is mandatory for the application, the system must boot on external mem- ory connected on CS0 (BMS = 0).

42.2.3.3 Boot ROM: Temperature Range

The temperature range for the Boot ROM use is 0°C / 70°C. Starting up the device outside this temperature range can lead to unpredictable behavior. If the AT91SAM9261S-based system may have to start up at temperatures below 0 ⋅ C and above 70⋅ C, it is recommended to boot out of an external memory connected on NCS0. Problem Fix/Workaround None.

42.2.3.4 Boot ROM: UDP Pad Pull-up Enable

When AT91SAM9261S boots on internal ROM (BMS =1), the UDP Pad Pull-up is enabled by software. This can lead to enumeration error. Problem Fix/Workaround Disable UDP Pad Pull-up at the beginning of the boot program (ex: at91bootstrap).

42.2.4 Bus Matrix

42.2.4.1 Bus Matrix: Problem with Locked Transfers

Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freeze up. This does not concern ARM locked transfers. Problem Fix/Workaround Avoid other Bus Matrix masters locked transfers.

42.2.5 LCD

42.2.5.1 LCD: Screen Shifting After a Reset

When a FIFO underflow occurs, a reset of the LCD DMA and FIFO pointers is necessary. If only LCD DMA pointers are reset (FIFO pointers not reset), the displayed image is shifted. Problem Fix/Workaround Apply the following sequence to correctly reset LCD DMA and FIFO pointers:  LCD power off

6242E–ATARM–11-Sep09 AT91SAM9261S  DMA disable  Wait for DMABUSY  DMA reset  LCD power on  DMA enable. Powering LCD off, then powering LCD on, resets the FIFO pointers. Disabling DMA, then enabling DMA, resets the DMA pointers.

42.2.5.2 LCD: Periodic Bad Pixels

LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per- forms bursts to read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA boundary. Problem Fix/Workaround The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG register. The LCD DMA Base Address is programmed in DMABADDR1 register. The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst size, e.g.: BRSTLN = 15 For a 16-word burst, the LCD DMA Base Address must start on a 16-word offset: 0x0, 0x40, 0x80 or 0xc0. BRSTLN = 3 For a 4-word burst, the LCD DMA Base Address offset must start on a 4-word offset: 0x0, 0x10, ..., 0xf0.

42.2.5.3 LCD: 24-bit Packed Mode

LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed mode. A 32-bit word contains some bits of a pixe l and some bits of the following. If LCD DMA Base Address is not aligned with a pixel start, the colors will be modified. Respect "LCD periodic bad pixels" erratum c onstrains lead to select the LCD DMA Base Address regarding the LCD DMA burst size. Problem Fix/Workaround LCD DMA Base Address is to be set on a pixel start, every three 32-bit word. The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or 0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8, 0xb4, 0xc0 ...) e.g. regarding the bursts size: 1) BRSTLN = 3 implies the following LCD DMA Base Address offsets: 0x0, 0x30, 0x60, ... 2) BRSTLN = 15 implies the following LCD DMA Base Address offsets: 0x0 and 0xc0 only.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2.6 MCI

42.2.6.1 MCI: Busy Signal of R1b Responses is not Taken In Account

The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a conflict can occur on data line 0 if the MCI sends data to the card while the card is still busy. The behavior is correct for CMD12 command (STOP_TRANSFER). Problem Fix/Workaround None

42.2.6.2 MCI: Data Timeout Error Flag

As the data timeout error flag cannot rise, the MCI is stalled indefinitely waiting for the data start bit. Problem Fix/Workaround A STOP command must be sent with a software timeout.

42.2.6.3 MCI: STREAM Command Not Supported

The STREAM READ/WRITE commands are not supported by the MCI. Problem Fix/Workaround None.

42.2.6.4 MCI: STOP During a WRITE_MULTIPLE_BLOCK Command

The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is not stopped by the STOP command. Problem Fix/Workaround Choose an appropriate size for the block length.

42.2.6.5 MCI: Data Write Operation and Number of Bytes

The Data Write operation with a number of bytes less than 12 is impossible. Problem Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number.

42.2.7 NTRST

42.2.7.1 NTRST: Device Does Not Boot Correctly due to Power-up Sequencing Issue

The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is pow- ered by VDDCORE power supply (1.2V). During the power-up sequence, if VDDIOP power supply is not established whereas the VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. The ARM processor then enters debug state and the device does not boot correctly. Problem Fix/Workaround 1. Connect NTRST pin to NRST pin to ensur e that a correct powering sequence takes place in all cases. 2. Connect NTRST to GND if no debug capabilities are required.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2.8 SDRAM Controller

42.2.8.1 SDRAM: SDCLK Clock Active After Reset

After a reset the SDRAM clock is always active leading in over consumption in the pad. Problem Fix/Workaround The following sequence allows to stop the SDRAM clock. 1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register. 2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to complete.

42.2.8.2 SDRAM: JEDEC Standard Compatibility

In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh mode. To be fully compliant with the JEDEC standard, SDCK must be stable before the rising edge of SDCKE. This is not the case in this product. Problem Fix/Workaround Use a fully JEDEC compliant SDRAM module.

42.2.8.3 SDRAM: Mobile SDRAM De vice Initialization Constraint

Using Mobile SDRAM devices that need to hav e their DQMx level HIGH during the Mobile SDRAM device initialization, may lead to data bus contention. Therefore, external memories on the same EBI must not be accessed. This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this phase. Problem Fix/Workaround Mobile SDRAM initialization must be performed in internal SRAM.

42.2.9 Serial Peripheral Interface (SPI)

42.2.9.1 SPI: Pulse Generation on SPCK

In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows: – The Baudrate is odd and different from 1. – The Polarity is set to 1. – The Phase is set to 0. Problem Fix/Workaround Do not use this configuration.

42.2.9.2 SPI: Bad PDC Behavior when CSAAT=1 and SCBR = 1

If the SPI2 is programmed with CSAAT = 1, SC BR(baudrate) = 1 and two transfers are per- formed consecutively on the same slave with an IDLE state between them, the second data is sent twice. Problem Fix/Workaround None. Do not use the combination CSAAT=1 and SCBR =1.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2.9.3 SPI: LASTXFER (Last Transfer) Behavior

In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a "1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY flag is set. Problem Fix/Workaround Use the CS in PIO mode when “PDC mode” is required and CS has to be maintained between transfers.

42.2.9.4 SPI: Chip Select and Fixed Mode

In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the output sp i_size sampled by the PDC will depend on the field BITS of SPI_CSR0 register, whatever the selected Chip select is. For example if CSR0 is configured for a 10-bit transfer whereas the CSR1 is configured for a 8-bit transfer, when a transfer is per- formed in Fixed mode through the PDC on Chip Select1, the transfer is considered as a halfword transfer. Problem Fix/Workaround If a PDC transfer has to be performed in 8 bits, on a Chip select y (y different from 0), the field BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy Register.

42.2.9.5 SPI: Baudrate Set to 1

When Baudrate is set at 1 (i.e. when serial cl ock frequency equals the system clock frequency), and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No problem occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None.

42.2.9.6 SPI: Software Reset

If the Software reset command is performed at the same clock cycle as an event for TXRDY occurs, there is no reset. Problem Fix/Workaround Perform another software reset.

42.2.9.7 SPI: Bad Serial Clock Generation on 2nd Chip Select

Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0. This occurs using SPI with the following conditions:  Master Mode  CPOL = 1 and NCPHA = 0  Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1  Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on output SPCK during the second transfer. Problem Fix/Workaround

6242E–ATARM–11-Sep09 AT91SAM9261S Do not use a multiple Chip Select configurati on where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear.

42.2.9.8 SPI: Software Reset Must be Written Twice

If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop- erly (the clock is enabled before the chip select). Problem Fix/Workaround The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly set.

42.2.10 Serial Synchronous Controller (SSC)

42.2.10.1 SSC: Transmitter Limitations in Slave Mode

If TK is programmed as input and TF is programmed as output and requested to be set to low/high during data emission, the Frame Synchro is generated one bit clock period after the data start, one data bit is lost. This problem does not exist when generating periodic synchro. Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK and NRST are AT91SAM9261S signals, TXD is the delayed data to connect to the device.

42.2.10.2 SSC: Periodic Transmission Limitations in Master Mode

If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None.

42.2.10.3 SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer

When the SSC receiver is used with the following conditions:

6242E–ATARM–11-Sep09 AT91SAM9261S  the internal clock divider is used (CKS = 0 and DIV different from 0)  RK pin set as output and provides the clock during data transfer (CKO = 2)  data sampled on RK falling edge (CKI = 0), At the end of the data, the RK pin is set in high impedance which might be seen as an unex- pected clock cycle. Problem Fix/Workaround Enable the pull-up on RK pin.

42.2.10.4 SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer

When the SSC receiver is used with the following conditions:  RX clock is divided clock (CKS = 0 and DIV different from 0)  RK pin set as output and provides the clock during data transfer (CKO = 2)  data sampled on RK falling edge (CKI = 0), The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)). Problem Fix/Workaround None.

42.2.11 Shutdown Controller (SHDWC)

42.2.11.1 SHDWC: Boundary Scan Mode Outputs the 32 kHz clock

In boundary scan mode, the SHDN pin outputs the 32 kHz clock. Problem/Fix Workaround There is only one way to disable the 32 kHz clock on the SHDN pin. In boundary scan mode, connect TST and JTAGSEL pins to VDDBU and set the SHDN pin to low level.

42.2.12 Static Memory Controller (SMC)

42.2.12.1 SMC: Chip Select Parameters Modification

The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory connected on this CS0, may lead to unpredictable behavior. Problem Fix/Workaround The code used to modify the parameters of an SMC Chip Select can be executed from the inter- nal RAM or from a memory connected to another Chip Select

42.2.13 System Controller

42.2.13.1 SYSC: Possible Event Loss when Reading RTT_SR

If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround The software must handle an RTT event as interrupt and as the only source of the interrupt source level 1.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2.14 Two-wire Interface (TWI)

42.2.14.1 TWI: Clock Divider

The value of CLDIV x 2 CKDIV must be less than or equal to 8191, the value of CHDIV x 2 CKDIV must be less than or equal to 8191· Problem Fix/Workaround None.

42.2.14.2 TWI: Disabling Does not Operate Correctly

Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI.

42.2.14.3 TWI: NACK Status Bit Lost

During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set. Problem Fix/Workaround The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not completed. Note: TXCOMP and NACK fields are set simultaneously a nd the NACK field is reset after the read of the TWI_SR.

42.2.14.4 TWI: Possible Receiv e Holding Register Corruption

When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data.

42.2.14.5 TWI: Software Reset

When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None.

42.2.14.6 TWI: STOP Not Generated

If the sequence described as follows occurs: 1. WRITE 1 or more bytes at a given address. 2. Send a STOP . 3. Wait for TXCOMP flag. 4. READ (or WRITE) 1 or more bytes at the same address. then STOP is not generated.

6242E–ATARM–11-Sep09 AT91SAM9261S Problem Fix/Workaround Insert a delay of one TWI clock period before step 4 in the sequence above.

42.2.15 USART

42.2.15.1 USART: RTS Unexpected Behavior

1. Setting the receiver to hardware handshaking mode drops RTS line to low level even if the receiver is still turned off. USART needs to be completely configured and started before setting the receiver to hardware handshaking mode. 2. Disabling the receiver during a PDC transfer while RXBUFF flag is '0' has no effect on RTS. The only way to get the RTS line rising to high level is to reset both PDMA buffers by writing the value '0' in both counter registers. Problem Fix/Workaround None.

42.2.15.2 USART: TXD Signal is Floating in Modem and Hardware Handshaking Mode

TXD signal should be pulled up in Modem and Hardware Handshaking mode. Problem Fix/Workaround TXD is multiplexed with a PIO which integrates a pull-up resistor. This internal pullup needs to be enabled.

42.2.15.3 USART: DCD is Active High Instead of Low

DCD signal is active at “High” level in USART block (Modem Mode). DCD should be active at “Low” level. Problem Fix/Workaround Add an inverter.

42.2.15.4 USART: CTS signal in Hardware Handshake

When Hardware Handshaking is used and if CTS goes low near the end of the starting bit of the transmitter, a character is lost. Problem Fix/Workaround CTS must not go low during a time slot comprised between 2 Master Clock periods before the rising edge of the starting bit, and 16 Master Clock periods after the rising edge of the starting bit.

42.2.16 UHP

42.2.16.1 UHP: Non-ISO IN transfers

Conditions: Consider the following sequence: 1. The Host controller issues an IN token. 2. The Device provides the IN data in a short packet. 3. The Host controller writes the received data to the system memory.

6242E–ATARM–11-Sep09 AT91SAM9261S 4. The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement write) to the system memory in order to complete the status update. 5. The Host controller raises the request for the first write transaction. By the time the transaction is completed, a frame boundary is crossed. 6. After completing the first write transaction, the Host controller skips the second write transaction. Consequence: When this defect manifests itself, the Host controller re-attempts the same IN token. Problem Fix/Workaround This problem can be avoided if the system guarantees that the status update can be completed within the same frame.

42.2.16.2 UHP: ISO OUT Transfers

Conditions: Consider the following sequence: 1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory. 2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the packet are not available. This results in a buffer underrun condition. 3. While there is an underrun condition, if the Host controller is in the process of bit-stuff- ing, it causes the Host controller to hang. Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected device to go into suspend state. Problem Fix/Workaround This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer.

42.2.16.3 UHP: Remote Wakeup Event

Conditions: When a Remote Wakeup event occurs on a downs tream port, the OHCI Host controller begins sending resume signaling to the device. The Host controller is supposed to send this resume signaling for 20 ms. However, if the driver sets the HcControl.HCF S into USBOPERATIONAL state during the resume event, then the Host controller terminates sending the resume signal with an EOP to the device. Consequence: If the Device does not recognize the resume (<20 ms) event, then the Device will remain in suspend state. Problem Fix/Workaround Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.2.17 UDP

42.2.17.1 UDP: Bad Data in the First IN Data Stage

All or part of the data of the first IN data Stage are not transmitted.It may then be a Zero Length Packet. The CRC is correct. So the HOST may only see that the size of the received data does not match the reques ted length. But even if performed again, the control tran sfer will probably fail. Problem Fix/Workaround These Control transfers are mainly used at device configuration. After clearing RXSETUP, the software needs to compute the setup transaction request before writing data into the FIFO if needed. This time is generally greater than the minimum safe delay required above. If not, a software wait loop after RXSETUP clear may be added at minimum cost.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3 AT91SAM9261S Errata - Revision B Parts

Refer to Section 42.1 “Marking” on page 667.

42.3.1 Main Oscillator

42.3.1.1 Main Oscillator: Spurious Malfunction of Main Oscillator

The main oscillator can exhibit sp urious malfunction as exhibited by the duty-cycle not perform- ing according to specification, missing main clock periods, or in the worst case, no main clock at all. The behavior does not alter over time. A device fully tested over the operating range (includ- ing power supply and temperat ure) in an application without exhibiting any malfunction will continue to function according to specifications. Problem Fix/Workaround Placing a series resistor of 470 Ω between XOUT and the crystal will fix the issue. The additional series resistor will not alter the device specif ication as documented in the datasheet, including the startup time and power consumption.

42.3.2 Battery Backup

42.3.2.1 Backup Overconsumption During AHB Masters Activity

Conditions: During AHB Masters activity (LCD DMA, USB Host DMA, etc.) the backup current can rise up to 12 µA @ 25⋅ C. Problem Fix/Workaround Figure 42-1 on page 668 shows how to feed the backup part of the chip from the battery only when the main power supply is off. In active mode, the clocks of unused peripherals should be disabled through the Power Management Controller to save power. Figure 42-2. Schematic 3V3 CR1225 CR1 MMBD1704A MN1 R1100D121C OUT1 VDD2 GND 3 R1 1K 100NF 100NF VDDBU

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3.3 Boot ROM

42.3.3.1 Boot ROM: Temperature Range

The temperature range for the Boot ROM use is 0°C / 70°C. Starting up the device outside this temperature range can lead to unpredictable behavior. If the AT91SAM9261S-based system may have to start up at temperatures below 0 ⋅ C and above 70⋅ C, it is recommended to boot out of an external memory connected on NCS0. Problem Fix/Workaround None.

42.3.4 Bus Matrix

42.3.4.1 Bus Matrix: Problem with Locked Transfers

Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freeze up. This does not concern ARM locked transfers. Problem Fix/Workaround Avoid other Bus Matrix masters locked transfers.

42.3.5 LCD

42.3.5.1 LCD: Screen shifting after a reset

When a FIFO underflow occurs, a reset of the LCD DMA and FIFO pointers is necessary. If only LCD DMA pointers are reset (FIFO pointers not reset), the displayed image is shifted. Problem Fix/Workaround Apply the following sequence to correctly reset LCD DMA and FIFO pointers:  LCD power off  DMA disable  Wait for DMABUSY  DMA reset  LCD power on  DMA enable. Powering LCD off, then powering LCD on, resets the FIFO pointers. Disabling DMA, then enabling DMA, resets the DMA pointers.

42.3.5.2 LCD: Periodic bad pixels

LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per- forms bursts to read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA boundary. Problem Fix/Workaround The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG register. The LCD DMA Base Address is programmed in DMABADDR1 register. The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst size, e.g.:

6242E–ATARM–11-Sep09 AT91SAM9261S BRSTLN = 15 For a 16-word burst, the LCD DMA Base Address must start on a 16-word offset: 0x0, 0x40, 0x80 or 0xc0. BRSTLN = 3 For a 4-word burst, the LCD DMA Base Address offset must start on a 4-word offset: 0x0, 0x10, ..., 0xf0.

42.3.5.3 LCD: 24-bit Packed Mode

LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed mode. A 32-bit word contains some bits of a pixe l and some bits of the following. If LCD DMA Base Address is not aligned with a pixel start, the colors will be modified. Respect "LCD periodic bad pixels" erratum c onstrains lead to select the LCD DMA Base Address regarding the LCD DMA burst size. Problem Fix/Workaround LCD DMA Base Address is to be set on a pixel start, every three 32-bit word. The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or 0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8, 0xb4, 0xc0 ...) e.g. regarding the bursts size: 1) BRSTLN = 3 implies the following LCD DMA Base Address offsets: 0x0, 0x30, 0x60, ... 2) BRSTLN = 15 implies the following LCD DMA Base Address offsets: 0x0 and 0xc0 only.

42.3.6 MCI

42.3.6.1 MCI: Busy Signal of R1b Responses Is Not Taken In Account

The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a conflict can occur on data line 0 if the MCI sends data to the card while the card is still busy. The behavior is correct for CMD12 command (STOP_TRANSFER). Problem Fix/Workaround None

42.3.6.2 MCI: Data Timeout Error Flag

As the data timeout error flag cannot rise, the MCI is stalled indefinitely waiting for the data start bit. Problem Fix/Workaround A STOP command must be sent with a software timeout.

42.3.6.3 MCI: STREAM Command Not Supported

The STREAM READ/WRITE commands are not supported by the MCI. Problem Fix/Workaround None.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3.6.4 MCI: STOP During a WRITE_MULTIPLE_BLOCK Command

The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is not stopped by the STOP command. Problem Fix/Workaround Choose an appropriate size for the block length.

42.3.6.5 MCI: Data Write Operation and Number of Bytes

The Data Write operation with a number of bytes less than 12 is impossible. Problem Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number.

42.3.7 NTRST

42.3.7.1 NTRST: Device Does Not Boot Correctly Due To Power-up Sequencing Issue

The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is pow- ered by VDDCORE power supply (1.2V). During the power-up sequence, if VDDIOP power supply is not established whereas the VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. The ARM processor then enters debug state and the device does not boot correctly. Problem Fix/Workaround 1. Connect NTRST pin to NRST pin to ensur e that a correct powering sequence takes place in all cases. 2. Connect NTRST to GND if no debug capabilities are required.

42.3.8 SDRAM Controller

42.3.8.1 SDRAM: SDCLK Clock Active After Reset

After a reset the SDRAM clock is always active leading in over consumption in the pad. Problem Fix/Workaround The following sequence allows to stop the SDRAM clock. 1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register. 2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to complete.

42.3.8.2 SDRAM: JEDEC Standard Compatibility

In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh mode. To be fully compliant with the JEDEC standard, SDCK must be stable before the rising edge of SDCKE. This is not the case in this product. Problem Fix/Workaround Use a fully JEDEC compliant SDRAM module.

42.3.8.3 SDRAM: Mobile SDRAM De vice Initialization Constraint

Using Mobile SDRAM devices that need to hav e their DQMx level HIGH during the Mobile SDRAM device initialization, may lead to data bus contention. Therefore, external memories on the same EBI must not be accessed.

6242E–ATARM–11-Sep09 AT91SAM9261S This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this phase. Problem Fix/Workaround Mobile SDRAM initialization must be performed in internal SRAM.

42.3.9 Serial Peripheral Interface (SPI)

42.3.9.1 SPI: Pulse Generation on SPCK

In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows: – The Baudrate is odd and different from 1. – The Polarity is set to 1. – The Phase is set to 0. Problem Fix/Workaround Do not use this configuration.

42.3.9.2 SPI: Bad PDC behavior when CSAAT=1 and SCBR = 1

If the SPI2 is programmed with CSAAT = 1, SC BR(baudrate) = 1 and two transfers are per- formed consecutively on the same slave with an IDLE state between them, the second data is sent twice. Problem Fix/Workaround None. Do not use the combination CSAAT=1 and SCBR =1.

42.3.9.3 SPI: LASTXFER (Last Transfer) Behavior

In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a "1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY flag is set. Problem Fix/Workaround Use the CS in PIO mode when “PDC mode” is required and CS has to be maintained between transfers.

42.3.9.4 SPI: Chip Select and Fixed Mode

In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the output sp i_size sampled by the PDC will depend on the field BITS of SPI_CSR0 register, whatever the selected Chip select is. For example if CSR0 is configured for a 10-bit transfer whereas the CSR1 is configured for a 8-bit transfer, when a transfer is per- formed in Fixed mode through the PDC on Chip Select1, the transfer is considered as a halfword transfer. Problem Fix/Workaround If a PDC transfer has to be performed in 8 bits, on a Chip select y (y different from 0), the field BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy Register.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3.9.5 SPI: Baudrate Set to 1

When Baudrate is set at 1 (i.e. when serial cl ock frequency equals the system clock frequency), and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No problem occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None.

42.3.9.6 SPI: Software Reset

If the Software reset command is performed at the same clock cycle as an event for TXRDY occurs, there is no reset. Problem Fix/Workaround Perform another software reset.

42.3.9.7 SPI: Bad Serial Clock Generation on 2nd Chip Select

Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0. This occurs using SPI with the following conditions:  Master Mode  CPOL = 1 and NCPHA = 0  Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1  Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on output SPCK during the second transfer. Problem Fix/Workaround Do not use a multiple Chip Select configurati on where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear.

42.3.9.8 SPI: Software Reset Must be Written Twice

If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop- erly (the clock is enabled before the chip select). Problem Fix/Workaround The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly set.

42.3.10 Serial Synchronous Controller (SSC)

42.3.10.1 SSC: Transmitter Limitations in Slave Mode

If TK are programmed as input and TF is programmed as output and requested to be set to low/high during data emission, the Frame Synchro is generated one bit clock period after the data start, one data bit is lost. This problem does not exist when generating periodic synchro. Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly.

6242E–ATARM–11-Sep09 AT91SAM9261S In the following schematic, TD, TK and NRST are AT91SAM9261S signals, TXD is the delayed data to connect to the device.

42.3.10.2 SSC: Periodic Transmission Limitations in Master Mode

If Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None.

42.3.10.3 SSC: Last RK Clock Cycle When RK Outputs a Clock During Data Transfer

When the SSC receiver is used with the following conditions:  the internal clock divider is used (CKS = 0 and DIV different from 0)  RK pin set as output and provides the clock during data transfer (CKO = 2)  data sampled on RK falling edge (CKI = 0), At the end of the data, the RK pin is set in high impedance which might be seen as an unex- pected clock cycle. Problem Fix/Workaround Enable the pull-up on RK pin.

42.3.10.4 SSC: First RK Clock Cycle When Rk Outputs a Clock During Data Transfer

When the SSC receiver is used with the following conditions:  RX clock is divided clock (CKS = 0 and DIV different from 0)  RK pin set as output and provides the clock during data transfer (CKO = 2)  data sampled on RK falling edge (CKI = 0), The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)). Problem Fix/Workaround None.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3.11 Shutdown Controller (SHDWC)

42.3.11.1 SHDWC: Boundary Scan Mode Outputs the 32 kHz Clock

In boundary scan mode, the SHDN pin outputs the 32 kHz clock. Problem/Fix Workaround There is only one way to disable the 32 kHz clock on the SHDN pin. In boundary scan mode, connect TST and JTAGSEL pins to VDDBU and set the SHDN pin to low level.

42.3.12 Static Memory Controller (SMC)

42.3.12.1 SMC: Chip Select Parameters Modification

The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory connected on this CS0, may lead to unpredictable behavior. Problem Fix/Workaround The code used to modify the parameters of an SMC Chip Select can be executed from the inter- nal RAM or from a memory connected to another Chip Select

42.3.13 System Controller

42.3.13.1 SYSC: Possible Event Loss When Reading RTT_SR

If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround The software must handle an RTT event as interrupt and as the only source of the interrupt source level 1.

42.3.14 Two-wire Interface (TWI)

42.3.14.1 TWI: Clock Divider

The value of CLDIV x 2 CKDIV must be less than or equal to 8191, the value of CHDIV x 2 CKDIV must be less than or equal to 8191· Problem Fix/Workaround None.

42.3.14.2 TWI: Disabling Does Not Operate Correctly

Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3.14.3 TWI: NACK Status Bit Lost

During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set. Problem Fix/Workaround The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not completed. Note: TXCOMP and NACK fields are set simultaneously a nd the NACK field is reset after the read of the TWI_SR.

42.3.14.4 TWI: Possible Receiv e Holding Register Corruption

When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data.

42.3.14.5 TWI: Software Reset

When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None.

42.3.14.6 TWI: STOP Not Generated

If the sequence described as follows occurs: 1. WRITE 1 or more bytes at a given address. 2. Send a STOP . 3. Wait for TXCOMP flag. 4. READ (or WRITE) 1 or more bytes at the same address. then STOP is not generated. Problem Fix/Workaround Insert a delay of one TWI clock period before step 4 in the sequence above.

42.3.15 USART

42.3.15.1 USART: RTS Unexpected Behavior

1. Setting the receiver to hardware handshaking mode drops RTS line to low level even if the receiver is still turned off. USART needs to be completely configured and started before setting the receiver to hardware handshaking mode. 2. Disabling the receiver during a PDC transfer while RXBUFF flag is '0' has no effect on RTS. The only way to get the RTS line rising to high level is to reset both PDMA buffers by writing the value '0' in both counter registers. Problem Fix/Workaround None.

6242E–ATARM–11-Sep09 AT91SAM9261S

42.3.15.2 USART: TXD Signal is Floating in Modem and Hardware Handshaking Mode

TXD signal should be pulled up in Modem and Hardware Handshaking mode. Problem Fix/Workaround TXD is multiplexed with a PIO which integrates a pull-up resistor. This internal pullup needs to be enabled.

42.3.15.3 USART: DCD is Active High Instead of Low

DCD signal is active at “High” level in USART block (Modem Mode). DCD should be active at “Low” level. Problem Fix/Workaround Add an inverter.

42.3.15.4 USART: CTS signal in Hardware Handshake

When Hardware Handshaking is used and if CTS goes low near the end of the starting bit of the transmitter, a character is lost. Problem Fix/Workaround CTS must not go low during a time slot comprised between 2 Master Clock periods before the rising edge of the starting bit, and 16 Master Clock periods after the rising edge of the starting bit.

42.3.16 UHP

42.3.16.1 UHP: Non-ISO IN Transfers

Conditions: Consider the following sequence: 1. The Host controller issues an IN token. 2. The Device provides the IN data in a short packet. 3. The Host controller writes the received data to the system memory. 4. The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement write) to the system memory in order to complete the status update. 5. The Host controller raises the request for the first write transaction. By the time the transaction is completed, a frame boundary is crossed. 6. After completing the first write transaction, the Host controller skips the second write transaction. Consequence: When this defect manifests itself, the Host controller re-attempts the same IN token. Problem Fix/Workaround This problem can be avoided if the system guarantees that the status update can be completed within the same frame.

42.3.16.2 UHP: ISO OUT Transfers

Conditions: Consider the following sequence:

6242E–ATARM–11-Sep09 AT91SAM9261S 1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory. 2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the packet are not available. This results in a buffer underrun condition. 3. While there is an underrun condition, if the Host controller is in the process of bit-stuff- ing, it causes the Host controller to hang. Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected device to go into suspend state. Problem Fix/Workaround This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer.

42.3.16.3 UHP: Remote Wakeup Event

Conditions: When a Remote Wakeup event occurs on a downs tream port, the OHCI Host controller begins sending resume signaling to the device. The Host controller is supposed to send this resume signaling for 20 ms. However, if the driver sets the HcControl.HCF S into USBOPERATIONAL state during the resume event, then the Host controller terminates sending the resume signal with an EOP to the device. Consequence: If the Device does not recognize the resume (<20 ms) event, then the Device will remain in suspend state. Problem Fix/Workaround Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL.

42.3.17 UDP

42.3.17.1 UDP: Bad Data in the First IN Data Stage

All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length Packet. The CRC is correct. So the HOST may only see that the size of the received data does not match the reques ted length. But even if performed again, the control tran sfer will probably fail. Problem Fix/Workaround These Control transfers are mainly used at device configuration. After clearing RXSETUP, the software needs to compute the setup transaction request before writing data into the FIFO if needed. This time is generally greater than the minimum safe delay required above. If not, a software wait loop after RXSETUP clear may be added at minimum cost.

6242E–ATARM–11-Sep09 AT91SAM9261S 43. Revision History In the tables that follow, the most recent version of the document appears first. Doc. Rev. 6242E Date 08-Sep-09 Comments Change Request Ref. Memories: Section 8.1.2.1 ”BMS = 1, Boot on Embedded ROM” updated. 6387 Errata Section 42.2.3.4 ”Boot ROM: UDP Pad Pull-up Enable” added. 6002 Write Operation and Number of Bytes” added. 6426 CTS signal in Hardware Handshake” added. 6209 Electrical Characteristics: Section 39.7 ”Core Power Supply POR Characteristics” added. 6636 TWI Section 31. ”Two-wire Interface (TWI)” changed. 6231 Doc. Rev. 6242D Date 22-Dec-08 Comments Change Request Ref. Errata: Section 42.2.1 ”Main Oscillator”, added to errata. Section 42.2.1.1 ”Main Oscillator: Spurious Malfunction of Main Oscillator” Section 42.3.1 ”Main Oscillator”, added to errata Section 42.3.1.1 ”Main Oscillator: Spurious Malfunction of Main Oscillator” 5960 Section 42.2.12 ”Static Memory Controller (SMC)” Section 42.2.12.1 ”SMC: Chip Select Parameters Modification”, added to errata. Section 42.3.12 ”Static Memory Controller (SMC)” Section 42.3.12.1 ”SMC: Chip Select Parameters Modification”, added to errata. 5642 Section 42.2.9 ”Serial Peripheral Interface (SPI)” Section 42.2.9.8 ”SPI: Software Reset Must be Written Twice”, added to errata. Section 42.3.9 ”Serial Peripheral Interface (SPI)” Section 42.3.9.8 ”SPI: Software Reset Must be Written Twice”, added to errata. 5956 Overview: ”Features” Additional Embedded Memories, 16 Kbytes SRAM updated. Debug Unit (DBGU) updated. 5848 5846

6242E–ATARM–11-Sep09 AT91SAM9261S BootProgram: Section 13.8 ”SD Card Boot” Boot ROM does not support high capacity SDCards, added to datasheet. Section 13.11 ”Hardware and Software Constraints”added footnote (1)Boot ROM does not support high capacity SDCards. 5935 DBGU ”Overview”, added text: “The Debug Unit two-pin UART can be used stand alone for general purpose serial communication.” 5846 Electrical Characteristics: Table 39-2, “DC Characteristics”, “SHDN” added to Characteristics of IO/Output Current Parameters. 5824 Doc. Rev. 6242D Date 22-Dec-08 Comments (Continued) Change Request Ref.

6242E–ATARM–11-Sep09 AT91SAM9261S Doc. Rev. 6242C Date 12-Sep-08 Comments Change Request Ref. Ordering Information: Section 41. ”AT91SAM9261S Ordering Information” Updated with Revision B Parts: AT91SAM9261SB-CU Errata: Section 42.3 ”AT91SAM9261S Errata - Revision B Parts” has been added removed errata USART “CTS signal in Hardware Handshake...” from Revision A Errata Section 42.2.7.1 on page 671, effect on ETM9 removed from NTRST errata. 5487 5433 5186 5794 New!!! Address Offsets added to register tables in User Interface sections of the datasheet. rfo Section 7.2 ”Debug and Test Features”, removed ETM9 list. 5794 AIC: Section 27.8.15 ”AIC Spurious Interrupt Vector Register”, fixed typo in bitfields. 4749 Section 27.6.3 ”Interrupt Sources”, Interrupt Source 1 OR-wiring description updated. 5191 Section 27.7.5 ”Protect Mode”, enabling Debug Control Protect Mode in AIC_DCR register updated. 5193 ARM926EJ-S Processor Section 11.1 ”Overview”, removed last bullet on TCM interface. Removed the block diagram. 5794 Debug and Test: Table 12-2, “AT91SAM9261S JTAG Boundary Scan Register” Bit number 481 is assigned to Pin Name A19. 5530 GPBR: Section 19. ”General Purpose Backup Register (GPBR)”, added to the datasheet 5764 LCDC: Table 38-1, “I/O Lines Description”, updated description of LCDDEN. 3587 Section 38.5.1.3 ”Channel-U”, Removed equations for STN Monochrome mode and STN Color mode. Updated definitions. Table 38-4, “Big Endian Memory Organization”, Inverted Pixel 1bpp row values to go from 0 to 31. Section 38.10.23 ”Power Control Register”, LCD_PWR bit description, changed all occurrences of “pin” to “signal”. 4268 Section 38.10.1 ”DMA Base Address Register 1”, updated with new values for bits 0 and 1. 4488 Section 38.5.2.7 ”Shifter”, fixed typo: “LDCCON3 register” corrected to read “LCDCON2 register” 4739 Section 38.9.2 ”TFT Mode Example”, HFP = (16-2), HBP = (48 -1), HPW = (64-1), typo corrected. 5619

6242E–ATARM–11-Sep09 AT91SAM9261S TC: Section 34.6 ”Timer Counter (TC) User Interface”, previous Register Mapping tables consolidated in Table 34-4, “Register Mapping” as a result of indexed register scheme. 4583 From Section 34.6.3 ”TC Channel Control Register” to Section 34.6.13 ”TC Interrupt Mask Register”, register names updated with indexed offset reference. Functional value of WAVE is given, when relevant, in Register Name or Access. Section 34.6.2 ”TC Block Mode Register”, typo corrected in bit fields 2 and 3. Section 34.6.4 ”TC Channel Mode Register: Capture Mode”, bit field 15 updated. Section 34.6.5 ”TC Channel Mode Register: Waveform Mode”, bit field 15 updated. TWI: Section 31. ”Two Wire Interface (TWI)”, extensive update to this section. 5327 UDP: Table 37-2, “USB Communication Flow” changed the value in the cell on the “interrupt line of the “Supported Endpoint Size” column. 3476 Control endpoints are not effected by the ”EPEDS: Endpoint Enable Disable” bit field in the UDP_CSR register. 4063 4099 Section 37.6.10 ”UDP Endpoint Control and Status Register”, update to code and added instructions regarding USB clock and system clock cycle. Section 37.2 ”Block Diagram”, text under the block diagram updated: MCK specified as clock used by Master Clock domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral clock requirements. 4508 Table 37-4, “Register Mapping”, UDP_CSR, UDP_FDR updated with indexed register scheme, footnote added to UDP_ISR reset. Section 37.6.6 ”UDP Interrupt Mask Register”, bitfield 12 defined as BIT12, cannot be masked. 4802 Table 37-4, “Register Mapping”, Reset value for UDP_RST_EP is 0x000_0000 5049 Table 37-1, “USB Endpoint Description”, footnote added to Dual-Bank heading. Section 37.5.2.9 ”Transmit Data Cancellation”, added. Section 37.6.9 ”UDP Reset Endpoint Register”, added steps to clear endpoints. 5150 UHP: Section 36.1 ”Overview”, Added hyperlink to Open HCI Rev 1.0 Specification. 4364 USART: Section 32.5.1 ”I/O Lines”, added sentence on required use of internal pull up on TXD pertaining to hardware handshaking feature. 4285 Section 32.6.2 ”Receiver and Transmitter Control”, In the fourth paragraph, Software reset effects (RSTRX and RSTTX in US_CR register) updated by replacing 2nd sentence. 4367 Section 32.6.3.1 ”Transmitter Operations”, last paragraph updated. rfo Section 32.6.5 ”IrDA Mode”, updated with instructions to receive IrDA signals. 4912 Doc. Rev. 6242C Date 12-Sep-08 Comments (Continued) Change Request Ref.

6242E–ATARM–11-Sep09 AT91SAM9261S Electrical Characteristics: Section 39.8 ”EBI Timings”, Section 39.9 ”SDRAMC TImings”, Section 39.10 ”Peripheral Timings” extensive updates to these sections. 5609 Table 39-19, “SMC Write Signals with Hold Settings” SMC23 and SMC34: in “Min” columns, -1 removed from (NWE pulse length). Table 39-20, “SMC Write Signals with No Hold Settings (NWE Controlled Only)” SMC40: in “Min” columns, -1 removed from (NWE pulse length). 5527 Figure 39-2 ”USB Data Signal Rise and Fall Times”, REWXT = 27 Ohms. 5612 Mechanical Characteristics: Table 40-1, “Soldering Information (Substrate Level),” on page 664, updated. 5288 Doc. Rev. 6242C Date 12-Sep-08 Comments (Continued) Change Request Ref.

6242E–ATARM–11-Sep09 AT91SAM9261S Doc. Rev. 6242B Comments Change Request Ref. Updated references to USBCK (HCK0) and LCDCK (HCK1) in Section 9.6 “Power Management Controller” on page 23. Updated Figure 9-3, “Power Management Controller Block Diagram,” on page 23. 3491 Added Note (3) to Table 20-4, “EBI Pins and External Devices Connections,” on page 141 for CE “Don’t care” NAND Flash interface. 3894 Updated Table 38-1, “Absolute Maximum Ratings*,” on page 655. 3697 In Table 38-3, “Power Consumption for Different Modes(1),” on page 657, added Note (1) on SRAM access in Idle Mode. 3903 Updated Table 38-5, “Processor Clock Waveform Parameters,” on page 658. 3687 Updated Section 38.5 “Crystal Oscillator Characteristics” on page 659. 4213 Errata: Added Section 41.2.2.1 “Boot ROM: NAND Flash Boot is not functional” on page 668, Section Range” on page 669. Added Section 41.2.5.1 “NTRST: Device does not boot correctly due to power-up sequencing issue” on page 670. Added Section 41.2.6.1 “SDRAM: JEDEC standard compatibility” on page 670. behavior when CSAAT=1 and SCBR = 1” on page 671, Section 41.2.7.3 “SPI: LASTXFER (Last Transfer) Behavior” on page 671, Section 41.2.7.4 “SPI: Chip Select and fixed mode” on page 671 and Section 41.2.7.6 “SPI: Software reset” on page 671. Operate Correctly” on page 673, Section 41.2.10.3 “TWI: NACK Status Bit Lost” on page 673, Section Software reset” on page 673 and Section 41.2.10.6 “TWI: STOP not generated” on page 673. Added Section 41.2.11.1 “USART: CTS signal in Hardware Handshake” on page 674 and Section 41.2.11.2 “USART: RTS unexpected behavior” on page 674. 4213 4216 6242A First issue.

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31.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User In-

32 Universal Synchro nous Asynchronous Receiver Transmitter (USART)

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32.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User In-

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x 6242E–ATARM–11-Sep09 AT91SAM9261S

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