Download PDFAT91FR40161 ATMEL
Document overview
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Technical content
Features
Incorporates the ARM7TDMI® ARM ® Thumb ® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 136 Kbytes of On-chip SRAM – 32-bit Data Bus, Single Clock Cycle Access 1024K-word 16-bit Flash Memory (2M bytes) – Single Voltage Read/Write – Sector Erase Architecture, Erase Suspend Capability – Dual-plane Organization Allows Concurrent Read and Program/Erase – Low-power Operation – Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection – Reset Input for Device Initialization – Sector Program Unlock Command – 128-bit Protection Register – Factory-programmed AT91 Flash Uploader Software Fully Programmable External Bus Interface (EBI) – Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes – Software Programmable 8/16-bit External Data Bus 8-level Priority, Individually Maskable, Vectored Interrupt Controller – Four External Interrupts, Including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines 3-channel 16-bit Timer/Counter – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel Two USARTs – Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features – CPU and Peripherals Can be De-activated Individually Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at 3.0V, 85°C 2.7V to 3.6V Operating Range -40°C to 85°C Temperature Range Available in a 120-ball BGA Package
Description
The AT91FR40161 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. A large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The eight-level priority-vectored interrupt controller, together with the Peripheral Data Con- troller, significantly enhance real-time device performance. By combining a microcontroller featuring more than 1 Mbit of on-chip SRAM and a wide range of peripheral functions with 16 Mbits of Flash memory in a single compact 120-ball BGA package, the AT91FR40161 provides a powerful, flexible and cost-effec- tive solution to many compute-intensive embedded control applications and offers significant board size and system cost reductions. The Flash memory may be programmed via the JTAG/ICE interface or the factory-pro- grammed Flash Uploader using a single device supply, making the AT91FR40161 ideal for in-system programmable applications. AT91 ARM ® Thumb ® Microcontrollers AT91FR40161 Summary Note: This is a summary document. A complete document is not available at this time. For more complete product information, refer to the documents listed in Table 2 on page 8 of this document and contact an Atmel sales office..
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Figure 1. AT91FR40161 Pinout (Top View)
Table 1. AT91FR40161 Pin Description
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2 Mbyte (1M x 16/2M x 8) 3-volt Only Flash
Table 1. AT91FR40161 Pin Description (Continued)
Figure 2. AT91FR40161
2 PDC
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6040B–ATARM–03/04 Architectural Overview The AT91FR40161 integrates Atmel’s AT91R40807 ARM Thumb processor and an AT49BV1604A/1614A 2 Mbyte (16 Mbit) Flash memory die in a single compact 120-ball BGA device. The address, data and control signals, except the Flash memory enable and Flash reset, are internally interconnected. The AT91R40807 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA Bridge. The AMBA Bridge drives the APB, designed for access to on-chip peripherals and optimized for low power consumption. The AT91FR40161 implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target debugging. Memories The AT91FR40161 embeds 136 Kbytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the processor, minimizing system power consumption and improving on the performance of separate memory solutions. The AT91FR40161 features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI imple- ments the early read protocol, enabling faster memory access than standard memory interfaces. The AT91FR40161 embeds a Flash memory organized as 1024K 16-bit words, accessed via the EBI. Its main function is program memory. A 16-bit Thumb instruction can be loaded from Flash memory in a single access. Separate MCU and Flash memory reset inputs (NRST and NRSTF) are provided for maximum flexibility. The user is thus free to tailor the reset operation to the application. The AT91FR40161 integrates resident boot software called AT91 Flash Uploader soft- ware in the embedded Flash. The AT91 Flash Uploader software is able to upload program application software into its Flash memory. Peripherals The AT91FR40161 integrates several peripherals that are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be pro- grammed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and on- and off-chip memory address spaces without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead, making it possible to transfer up to 64K contiguous bytes without reprogramming the start address, thus increasing the performance of the microcontroller and reducing the power consumption. System Peripherals The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8- or 16-bit data bus and is programmed through the APB. Each chip select line has its own programming register.
6040B–ATARM–03/04 The Power-saving (PS) module implements the Idle Mode (ARM7TDMI core clock stopped until the next interrupt) and enables the user to adapt the power consumption of the microcontroller to application requirements (independent peripheral clock control). The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the auto-vectoring feature, reduces the interrupt latency time. The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. The PIO controller can be programmed to detect an interrupt on a signal change from each line. The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock. The Special Function (SF) module integrates the Chip ID, the Reset Status and the Pro- tect registers. User Peripherals Two USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to eight data bits. Each USART also features a Timeout and a Time Guard register, facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels. The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or waveform modes. Each TC channel can be programmed to measure or generate dif- ferent kinds of waves, and can detect and control two input/output signals. In addition, the TC has three external clock signals.
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6040B–ATARM–03/04 Associated Documentation Table 2. Associated Documentation
Ordering information
AT91FR40161 Summary Datasheet (this document) Detailed description of Flash memoryAT49BV/LV1604A/1614A(T) 2-Mbyte (1M x 16/2M x 8) 3-volt Only Flash Memory Datasheet
6040B–ATARM–03/04 Product Overview Power Supply The AT91FR40161 has a single power supply pin, VDD . The VDD pin supplies the I/O pads and the core. The supported voltage range on VDD is 2.7V to 3.6V. Input/Output Considerations The AT91FR40161 I/O pads accept voltage levels up to the power supply limit. After reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption. Master Clock The AT91FR40161 has a fully static design and works on the Master Clock (MCK), pro- vided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general purpose I/O line. While NRST is active, and after the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. Reset Reset restores the default states of the user interface registers (defined in the user inter- face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM7TDMI registers do not have defined reset states. NRST Pin NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn- chronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST. Watchdog Reset The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority. Emulation Functions Tri-state Mode The AT91FR40161 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the out- put pin drivers of the AT91R40807 microcontroller are disabled. In Tri-state Mode, direct access to the Flash via external pins is provided. This enables production Flash programming using standard Flash programmers prior to board mounting. To enter tri-state mode, the NTRI pin must be held low during the last ten clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400 kΩ . NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1. JTAG/ICE Debug ARM standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con- nected to a host computer via the external ICE interface. In ICE Debug Mode, the
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ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant. In any of these address spaces, the ARM7TDMI operates in little-endian mode only. mizes the microcontroller performance and minimizes the system power consumption. ARM7TDMI advanced performance. signal, are connected within the device. type of boot memory (see Table 3). pulled down externally and NCS0 must be connected to NCSF externally. Table 3. Boot Mode Select
1 Internal 32-bit extended SRAM
0 External 16-bit memory on NCS0
6040B–ATARM–03/04 Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91FR40161 uses a remap command that enables switching between the boot memory and the inter- nal primary SRAM bank addresses. The remap command is accessible through the EBI User Interface by writing one in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to the other external devices (connected to chip selects 1 to 7) is required. The remap operation can only be changed back by an internal reset or an NRST assertion. Abort Control The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is asserted when accessing an undefined address in the EBI address space. No abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not. External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can be configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte, half-word and word aligned accesses. For each of these banks, the user can program: Number of wait states Number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus) Data bus width (8-bit or 16-bit) With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16- bit memory (Byte Write Access Mode). The External Bus Interface features also the Early Read Protocol, configurable for all the devices, that significantly reduces access time requirements on an external device in the case of single-clock cycle access. In the AT91FR40161, the External Bus Interface connects internally to the Flash memory. Flash Memory The 2 Mbyte Flash memory is organized as 1,048,576 words of 16 bits each. The Flash memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A20. The address, data and control signals, except the Flash memory enable, are internally interconnected. The user should connect the Flash memory enable (NCSF) to one of the active-low chip selects on the EBI; NCS0 must be used if the Flash memory is to be the boot memory. In addition, if the Flash memory is to be used as boot memory, the BMS input must be pulled down externally in order for the processor to perform correct 16-bit fetches after reset. During boot, the EBI must be configured with the correct number of standard wait states. For example, four standard wait states are required when the microcontroller is running at 40 MHz. The user must ensure that all V DD and all GND pins are connected to their respective supplies by the shortest route. The Flash memory powers on in the read mode. Com- mand sequences are used to place the device in other operating modes, such as program and erase.
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6040B–ATARM–03/04 A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility, enabling the reset operation to adapt to the application. When this input is at a logic high level, the memory is in its standard operating mode; a low level on this input halts the current memory operation and puts its outputs in a high impedance state. The Flash memory features data polling to detect the end of a program cycle. While a program cycle is in progress, an attempted read of the last word written will return the complement of the written data on I/O7. An open-drain NBUSY output pin provides another method of detecting the end of a program or erase cycle. This pin is pulled low while program and erase cycles are in progress and is released at the completion of the cycle. A toggle bit feature provides a third means of detecting the end of a program or erase cycle. The Flash memory is segmented into two memory planes. Reads from one memory plane may be performed even while program or erase functions are being executed in the other memory plane. This feature enhances performance by not requiring the sys- tem to wait for a program or erase cycle to complete before a read may be performed. The Flash memory is divided into 39 sectors for erase operations. To further enhance device flexibility, an Erase Suspend feature is offered. This feature puts the erase cycle on hold for an indefinite period and allows the user to read data from, or to write data to, any other sector within the same memory plane. There is no need to suspend an erase cycle if the data to be read is in the other memory plane. The device has the capability to protect data stored in any sector. Once the data protec- tion for a sector is enabled, the data in that sector cannot be changed while input levels lie between ground and V DD . An optional VPP pin is available to enhance program/erase times. A 6-byte command sequence (Enter Single Pulse Program Mode) allows the device to be written to directly, using single pulses on the write control lines. This mode (Single- pulse Programming) is exited by powering down the device or by pulsing the NRSTF pin low for a certain duration (1) and then bringing it back to VDD . The following hardware features protect against inadvertent programming of the Flash memory: V DD Sense – if VDD is below a certain level(1), the program function is inhibited. V DD Power-on Delay – once VDD has reached the VDD sense level, the device will automatically time out a certain duration(1) before programming. Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles. Noise Filter – pulses of less than a certain duration(1) on the WE or CE inputs will not initiate a program cycle. See the AT49BV1604A/1614A(T) 2-Mbyte (1M x 16/2M x 8) 3-volt Only Flash Memory Datasheet for further details on Flash operation and electrical characteristics. Note: 1. Defined in the AT49BV1614A Flash Memory Datasheet, Atmel lit° 1411.
on-chip USARTs can be used by the Flash Uploader. Figure 3. Flash Uploader to minimize the risk that the Flash Uploader is erased and the power supply shuts down. grammed using the Flash Uploader. site and requires only a serial cable to connect the Host to the Target.
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6040B–ATARM–03/04 Communications can be selected on either COM1 or COM2 and the serial link speed is limited to 115200 bauds. Because the serial link is the bottleneck in this configuration, the Flash programming lasts 110 seconds per Mbyte. Reduced programming time can be achieved by using a faster programming system. An AT91 Evaluation Board is capable of running a serial link at up to 500 Kbits/sec and can match the fastest programming allowed by the Flash, for example, about 40 seconds per Mbyte when the word programming becomes the bottleneck. Peripherals The AT91FR40161 peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not sup- ported. If a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access. Each peripheral has a 16 Kbyte address space allocated (the AIC only has a 4 Kbyte address space). Peripheral Registers The following registers are common to all peripherals: Control Register – write-only register that triggers a command when a one is written to the corresponding position at the appropriate address. Writing a zero has no effect. Mode Register – read/write register that defines the configuration of the peripheral. Usually has a value of 0x0 after a reset. Data Registers – read and/or write register that enables the exchange of data between the processor and the peripheral. Status Register – read-only register that returns the status of the peripheral. Enable/Disable/Status Registers are shadow command registers. Writing a one in the Enable Register sets the corresponding bit in the Status Register. Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register. Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non-interruptible instruction, replacing the costly read-modify-write operation. Unused bits in the peripheral registers must be written at 0 for upward compatibility. These bits read 0. Peripheral Interrupt ControlThe Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller. The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter- rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a non- interruptible single instruction. This eliminates the need for interrupt masking at the AIC or core level in real-time and multi-tasking systems.
6040B–ATARM–03/04 Peripheral Data Controller The AT91FR40161 has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Register (RCR or TCR). When the programmed number of transfers are per- formed, a status bit indicating the end of transfer is set in the USART Status Register and an interrupt can be generated.
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6040B–ATARM–03/04 System Peripherals PS: Power-saving The Power-saving feature optimizes power consumption, enabling the software to stop the ARM7TDMI clock (idle mode), restarting it when the module receives an interrupt (or reset). It also enables on-chip peripheral clocks to be enabled and disabled individually, matching power consumption and application needs. AIC: Advanced Interrupt Controller The Advanced Interrupt Controller has an 8-level priority, individually maskable, vec- tored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from: The external fast interrupt line (FIQ) The three external interrupt request lines (IRQ0 - IRQ2) The interrupt signals from the on-chip peripherals The AIC is extensively programmable offering maximum flexibility, and its vectoring fea- tures reduce the real-time overhead in handling interrupts. The AIC also features a spurious vector detection feature, which reduces spurious inter- rupt handling to a minimum, and a protect mode that facilitates the debug capabilities. PIO: Parallel I/O ControllerThe AT91FR40161 has 32 programmable I/O lines. Six pins are dedicated as general- purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins. WD: Watchdog The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or inter- rupt, or assert an active level on the dedicated pin NWDOVF. All programming registers are password-protected to prevent unintentional programming. SF: Special Function The AT91FR40161 provides registers that implement the following special functions. Chip Identification RESET Status P r o t e c t M o d e
6040B–ATARM–03/04 User Peripherals USART: Universal Synchronous/ Asynchronous Receiver Transmitter The AT91FR40161 provides two identical, full-duplex, universal synchronous/asynchro- nous receiver/transmitters. Each USART has its own baud rate generator, and two dedicated Peripheral Data Con- troller channels. The data format includes a start bit, up to 8 data bits, an optional programmable parity bit and up to 2 stop bits. The USART also features a Receiver Timeout register, facilitating variable length frame support when it is working with the PDC, and a Time-guard register, used when interfac- ing with slow remote equipment. TC: Timer Counter The AT91FR40161 features a Timer Counter block that includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval mea- surement, pulse generation, delay timing and pulse width modulation. The Timer Counter can be used in Capture or Waveform mode, and all three counter channels can be started simultaneously and chained together.
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6040B–ATARM–03/04 Table 4. Ordering Information
Figure 4. 120-ball Ball Grid Array Package Drawing Table 5. Thermal Resistance Data Table 6. Device and 120-ball BGA Package Maximum Weight
1.70 Max
0.41 Max
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Table 7. 120-ball BGA Package Characterisicst
Soldering Profile Table 8 gives the recommended soldering profile from J-STD-20. tures of up to 235°C, not 220°C (IR reflow). Recommended package reflow conditions depend on package thickness and volume.
- By default, the package level 1 is qualified at 220°C (unless 235°C is stipulated).
- The body temperature is the most important parameter, but other profile parameters
A maximum of three reflow passes is allowed per component. Table 8. Soldering Profile Average Ramp-up Rate (183°C to Peak) 3 °C/sec. max. 10 °C/sec. Temperature Maintained Above 183°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 10 sec. to 20 sec. 60 sec. Ramp-down Rate 6 °C/sec. 10 °C/sec. Table 9. Recommended Package Reflow Conditions (1, 2, 3)
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