AT89S4D12

AT89S4D12 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 13

Technical content

Features

• Compatible with MCS-51™ Products
• 128K Bytes of In-System Reprogrammable Flash data memory and 4K Bytes of Downloadable Flash Program Memory – Endurance: 1,000 Write/Erase Cycles per Sector – Data Retention: 10 Years
• Sector Programming: 128 Bytes/Sector
• Single 3.3V ±±±± 10% Supply
• On-Chip 12 MHz oscillator
• Two-Level Program Memory Lock
• 256-Bytes Internal RAM
• 5 Programmable I/O Lines
• Serial Peripheral Interface (SPI) Channel
• Serial Program Downloading
• Dual Data Pointer Registers

Description

The AT89S4D12 is a low-voltage, highly integrated CMOS 8-bit microcomputer with 4K bytes of downloadable Flash program memory and 128K bytes of in-system repro- grammable Flash data memory. The device is manufactured using Atmel’s high den- sity Flash memory technology and is compatible with the industry-standard MCS-51™ instruction set. The 128K bytes of on-chip Flash data memory are accessed as two 64K byte blocks. Bit 0 at SFR location 96H is used to select the active block. The MOVX instruction is used to read and write the data memory. Both the program and data memory arrays can be programmed by an external programmer. The downloadable Flash can be changed one page (128 bytes) at a time and is accessible through the SPI serial peripheral interface port. Holding RESET active forces the SPI bus into a slave input mode and allows the program memory to be writ- ten-from or read-to unless Lock Bit 2 has been activated. The functional operations of the 128K bytes Flash data memory are equivalent to those on the AT29LV010A 1M Bit Flash memory device. 0921A-A–12/97 8-Bit Microcontroller with 132K Bytes Flash Data Memory AT89S4D12 SOIC T op View GND TEST1 RESET SDI/P1.1 SDO/P1.0 TEST2 NC NC NC NC NC NC NC NC VCC P1.2/DTR P1.3/SCK P1.4/DSR NC NC NC NC NC NC NC NC NC NC PLCC T op View P1.0/SDO TEST2 NC NC NC NC NC NC NC P1.4/DSR NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC P1.1/SDI RESET TEST1 GND VCC P1.2/DTR P1.3/SCK Pin Configurations

B REGISTER STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 1 DRIVERS P1.0 - P1.4 12MHz OSC GND VCC RST RAM ADDR. REGISTER PORT 1 LATCH SPI PORT PROGRAM LOGIC

Supply voltage. GND Ground. Port 1 Port 1 is a 5-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups. In addition, P1.0, P1.1, and P1.3 can be configured as the SPI data output, data input and shift clock input pins, as shown in the following table. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. TEST1 TEST1 is set to V CC during downloading of the Flash pro- gram or data memory. This pin can be left unconnected or tied to ground during normal operation. TEST2 Test input. This pin has no user available function and can be left unconnected or tied to ground. Special Function Registers A map of the on-chip memory area called the Special Func- tion Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect. User software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Memory Control Register The MCON register contains the RDY/BSY flag and the most significant Flash address bit A16, for the 128K bytes of on-chip Flash data memory. SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 3) and SPSR (shown in Table 4). The SPI data bits are contained in the SPDR register. Writing the SPI data register during serial data transfer sets the Write Collision bit, WCOL, in the SPSR register. The SPDR is double buff- ered for writing and the values in SPDR are not changed by Reset. Dual Data Pointer Registers To facilitate data transfer, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H - 83H and DP1 at 84H - 85H. Bit DPS = 0 in SFR MCON selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer register. Port Pin Alternate Functions P1.0 SDO (data output pin for SPI channel) P1.1 SDI (data input pin for SPI channel) P1.3 SCK (clock input pin for SPI channel)

Table 1. AT89S4D12 SFR Map and Reset Values

Table 2. MCON—Memory Control Register Table 3. SPCR—SPI Control Register DP0, and DPS = 1 selects the second bank, DP1. equals \0' and is automatically reset to \1' when programming is completed. A16 Memory Block Select. A16 = 0 selects the lower 64K bytes DataFlash memory block. A16 = 1 selects the upper 64K bytes DataFlash block. P1.3. SPI = 0 disables the SPI channel. low when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control. master and slave. Please refer to figure on SPI Clock Phase and Polarity Control.

Table 4. SPSR—SPI Status Register Table 5. SPDR—SPI Data Register addressing access SFR space. accesses the SFR at location 086H (which is SPDR). completed and another write cycle can be initiated. register with SPIF and WCOL bits set, and then accessing the SPI data register.

• Full-Duplex, 3-Wire Synchronous Data T ransfer
• 2 MHz Bit Frequency (max.)
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End of T ransmission Interrupt Flag
• Write Collision Flag Protection The interconnection between master and slave CPU with SPI is shown in the following figure. The SCK pin is the clock input. Writing to the SPI data register of the master CPU starts the SPI clock generator, and the data written shifts out of the MOSI pin and into the SDI pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI inter- rupt enable bit (SPIE) is set, an interrupt is requested. There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 3 and Figure 4.

Figure 1. SPI Block Diagram

Oscillator Characteristics An on-chip oscillator is provided with a minimum frequency of 12 MHz and maximum frequency of 15 MHz over the recommended operating conditions. Each CPU instruction cycle takes 12 oscillator cycles. Program Memory Lock Bits The AT89S4D12 has two lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. The self-timed lock bit programming operation typically takes 40 ms. Once programmed, the lock bits can only be unpro- grammed with the Chip Erase operation. Lock Bit Protection Modes(1)(2) Notes: 1. U = Unprogrammed 2. P = Programmed Flash Programming Specification Both the 128K bytes Data and 4K bytes Code flash mem- ory arrays can be programmed using the serial SPI bus while the RESET and TEST1 pins are pulled to V CC = 3.3V (±10%). Both memory arrays are organized in 128-byte sectors for programming and are written sector-by-sector, similar to the Atmel AT29LV010A. The serial interface consists of pins SCK (serial shift clock), SDI (serial input) and SDO (serial output). After RESET and TEST1 are set high, the Programming Enable instruc- tion needs to be executed once before programming oper- ations can occur. During device programming, pin TEST2 should be connected to Ground. An auto-erase cycle is built into the self-timed Page Write operation and there is no need to first execute the Chip Erase instruction. The Chip Erase operation is self-timed and typically takes 5 ms. Chip Erase turns the content of every flash memory location in both the Code and Data arrays into FFH. The Code and Data memory arrays have separate address spaces: 0000H to 0FFFH for Code memory and 00000H to 2FFFFH for Data memory. The maximum serial clock (SCK) frequency used during flash programming should be less than 500 KHz. The High time of SCK should be 1.5 µ s minimum and Low time should be 0.5 µs minimum. DATA Polling The AT89S4D12 features DA T A Polling to indicate the end of a page write cycle. During a write cycle, an attempted serial read of the last byte written will result in the comple- ment of the written datum at bit D7. Once the write cycle has been completed, true data are valid on all output data bits, and the next write cycle may begin. DAT A Polling may begin any time after a write instruction has been executed. Toggle Bit The Toggle Bit provides another method to detect comple- tion of a programming cycle. During a page write or chip erase operation, successive attempts to read data from the memory will result in output bit D6 toggling between ‘1’ and ‘0’. Once the program cycle has completed, output data bit D6 will stop toggling and valid data will be presented. Examining the toggle bit may begin any time during a pro- gram cycle. Ready/Busy A third method to monitor the progress of programming is provided by the RDY/BSY output signal. Pin P1.4/DSR is pulled Low during programming to indicate BUSY and is pulled High again when programming is done to indicate READY. Page Write The Code and Data memory arrays are programmed on a sector basis. If a byte of data is to be changed, data for the entire 128-byte sector must be serially loaded into the device using the appropriate serial interface instruction. The data in any byte that is not loaded during the program- ming of its sector will be indeterminate. The AT89S4D12 automatically does a sector erase to turn the whole sector into FFH prior to loading the data into the sector. An erase command is not required. The self-timed Page Write cycle typically takes 5 ms (t WC ). Program Lock Bits LB1 LB2 Protection Type 1 U U No internal memory lock feature. 2 P U Programming of the Flash memory is disabled. 3 P P Same as mode 2, but verify is also disabled. (continued)

Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the self-timed pro- gramming cycle (t WC ). After the first data byte has been loaded into the device, successive bytes need to be entered within 300-µ s time intervals. If a Page Write instruction is not detected in 300-µs after the last write instruction, the load period will end and the internal pro- gramming cycle will start. Address bits A7 - A11 and A7 - A16 specify the sector address of the Code and Data memory arrays, respec- tively. The valid sector address must be entered during each write instruction. Address bits A0 - A6 specify the byte address within the sector. The bytes may be loaded in any order, sequential loading is not required. Once a program- ming operation has been initiated, and for a duration of typ- ically 5 ms, a read operation will effectively be a polling operation. Program Verify If lock bits LB1 and LB2 have not been programmed, the programmed Code and Data byte can be read back via serial output pin SDO. The state of the lock bits can only be verified indirectly by observing that the lock bit features are enabled. Serial Programming Instruction Set Notes: 1. A16:A0 = Memory byte address 2. ‘DDDDDDDD’ = Data input at pin SDI or data output at pin SDO. 3. ‘x’ = Don’t care. Instruction Format OperationByte 1 Byte 2 Byte 3 Byte 4 Programming Enable 10101100 01010011 11111111 11111111 Enable Serial Programming after RST goes high. Chip Erase 10101100 10000000 xxxxxxxx xxxxxxxx Chip erase both 128K & memory arrays. Read Code Memory 0010000x A11 A10 DDDDDDDD Read data at pin SDO for Code memory at address A11:A0. Page Write Code Memory 0100000x A11 A10 DDDDDDDD Write data at pin SDI for Code memory at address A11:A0. Read Data Memory 1010000 A15 A14 A13 A12 A11 A10 DDDDDDDD Read data at pin SDO for Data memory at address A16:A0. Page Write Data Memory 1100000 A15 A14 A13 A12 A11 A10 DDDDDDDD Write data at pin SDI for Data memory at address A16:A0. Program Lock Bits 10101100 111000 xxxxxxxx xxxxxxxx Set LB1, LB2 = ‘0’ to program lock bits. Read Signature 0011000x xxxxxxxx DDDDDDDD Read device I.D. at address A6:A0. A16A16 LB2 LB1 xxxx xxxx x

Flash Memory Serial Programming Circuit Reading the Signature Bytes The signature bytes are read by executing the Read Signa- ture command at locations 30H and 31H. The values returned are as follows: (30H) = 1EH indicates manufactured by Atmel (31H) = 84H indicates A T89S4D12 INSTRUCTION INPUT DATA OUTPUT CLOCK IN RDY/BUSY VCC RESET TEST1 3.3V SDI/P1.1 SDO/P1.0 SCK/P1.3 DSR/P1.4 TEST2 GND Serial Downloading Waveforms SERIAL CLOCK INPUT SCK/P1.3 SERIAL DATA INPUT SDI/P1.1 SERIAL DATA OUTPUT SDO/P1.0 76543210 MSB LSB MSB LSB BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 1 BYTE 2 BYTE 3 BYTE 4 1ST INSTRUCTION 2ND INSTRUCTION tBLC = 300 µS MAX.

Absolute Maximum Ratings* DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 3.0V to 3.6V, unless otherwise noted. Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 5 bit port: 15 mA If IOL exceeds the test condition, VOL may exceeed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V . Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin Symbol Parameter Condition Min Max Units V IL Input Low Voltage -0.5 0.2 V CC - 0.1 V VIH Input High Voltage (Except RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High Voltage (RST) 0.7 V CC VCC + 0.5 V VOL Output Low Voltage(1) IOL = 1.6 mA 0.5 V VOH Output High Voltage IOH = -60 µA2 . 4 V IOH = -25 µA0 . 7 5 V CC V IOH = -10 µA0 . 9 V CC V IIL Logical 0 Input Current VIN = 0.45V -50 µA ITL Logical 1 to 0 T ransition Current VIN = 2V -650 µA RRST Reset Pulldown Resistor 50 300 K Ω C IO Pin Capacitance T est Freq. = 1 MHz, T A = 25°C 10 pF ICC Power Supply Current Active Mode 20 mA

Ordering Information

(MHz) Power Supply Ordering Code Package Operation Range 12 3.3V ± 10% A T89S4D12-12JC AT89S4D12-12RC 32J 28R Commercial (0°C to 70°C) AT89S4D12-12JI AT89S4D12-12RI 32J 28R Industrial (-40°C to 85°C) Package Type 32J 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 28R 28-Lead, Plastic Gull Wing Small Outline (SOIC)