AT89C51CC01CA-RLTUM

T89C51CC01_08 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 167

Technical content

Features

• 80C51 Core Architecture
• 256 Bytes of On-chip RAM
• 1K Bytes of On-chip XRAM
• 32K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85° C Erase/Write Cycle: 100K
• Boot Code Section with Independent Lock Bits
• 2K Bytes of On-chip Flash for Bootloader
• In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
• 2K Bytes of On-chip EEPROM Erase/Write Cycle: 100K
• 14-sources 4-level Interrupts
• Three 16-bit Timers/Counters
• Full Duplex UART Compatible 80C51
• Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
• Five Ports: 32 + 2 Digital I/O Lines
• Five-channel 16-bit PCA with: – PWM (8-bit) – High-speed Output – Timer and Edge Capture
• Double Data Pointer
• 21-bit Watchdog Timer (7 Programmable Bits)
• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
• Full CAN Controller: – Fully Compliant with CAN Rev2.0A and 2.0B – Optimized Structure for Communication Management ( Via SFR) – 15 Independent Message Objects: Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt – Supports: Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode – 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode – Readable Error Counters – Programmable Link to On-chip Timer for Time Stampi ng and Network Synchronization – Independent Baud Rate Prescaler – Data, Remote, Error and Overload Frame Handling
• On-chip Emulation Logic (Enhanced Hook System)
• Power Saving Modes: – Idle Mode – Power-down Mode 1. At BRP = 1 sampling point will be fixed. Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory T89C51CC01 AT89C51CC01

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4129N–CAN–03/08

• Power Supply: 3V to 5.5V
• Temperature Range: Industrial (-40 ° to +85 °C)
• Packages: VQFP44, PLCC44 Description The T89C51CC01 is the first member of the CANary TM family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memory including In-System-Programming (ISP), 2K Bytes Boo t Flash Memory, 2K Bytes EEPROM and 1.2-Kbyte RAM. Special attention is paid to the reduction of the e lectro-magnetic emission of T89C51CC01. Block Diagram Notes: 1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port Timer 0 INT RAM 256x8 RxD TxD WR RD EA PSEN ALE XTAL2 XTAL1 UART CPU Timer 1 INT1 Ctrl INT0 C51 CORE Port 0 Port 1 Port 2 Port 3 Parallel I/O Ports and Ext. Bus P1(1) XRAM 1kx8 IB-bus PCA RESET Watch Dog PCA ECI Vss Vcc Timer 2 T2EX Port 4 P4(2) 10 bit ADC Flash 32kx Boot loader 2kx8 EE PROM 2kx8 CAN CONTROLLER TxDC RxDC VAREF VAVCC VAGND

4129N–CAN–03/08 Pin Configuration PLCC44 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7/RD P4.0/ TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P3.6/WR ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.1/AD1 P0.0/AD0 P2.0/A8 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 43 42 41 40 39 44 38 37 36 35 34 12 13 17 16 15 14 20 19 18 21 22 VQFP44 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.2 /AD2 P0.3 /AD3 P0.4 /AD4 P0.1 /AD1 P0.0 /AD0 P2.0/A8 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P3.6/WR

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independently programmed as input or output. I/O or for its alternate input output function. ister (x = 1,3 or 4). To use a pin for general-purp ose input, set the bit in the Px register. This turns off the output FET drive. Figure 1. Port 1, Port 3 and Port 4 Structure Note: The internal pull-up can be disabled on P1 whe n analog function is selected. shows the structure of Port 2. An external source can pull a Port 2 pin low. turn off the output driver FET.

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It is not obvious the last three instructions in th is list are Read-Modify-Write instructions. than the pins returns the correct logic-one value. to input conditions by a logical one written to the latch. vention. Current strengths are 1/10 that of pFET #3. Table 1. Read-Modify-Write Instructions

Figure 4. Internal Pull-Up Configurations Note: Port 2 p1 assists the logic-one output for mem ory bus cycles.

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Table 2. C51 Core SFRs Table 3. I/O Port SFRs Table 4. Timers SFRs

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Table 4. Timers SFRs (Continued) Table 5. Serial I/O Port SFRs Table 6. PCA SFRs

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Table 6. PCA SFRs (Continued) Table 7. Interrupt SFRs Table 8. ADC SFRs Table 9. CAN SFRs

Table 9. CAN SFRs (Continued)

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Table 10. Other SFRs

Note: 1. These registers are bit – addressable. whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF. Table 11. SFR Mapping

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4129N–CAN–03/08 Clock The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.
• Saves power consumption while keeping the same CPU power (oscillator power saving).
• Saves power consumption by dividing dynamic operat ing frequency by 2 in operating and idle modes.
• Increases CPU power by 2 while keeping the same cr ystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core ( phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System-Programming". Description The X2 bit in the CKCON register (see Table 12) allo ws switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure 5.). The Timers 0, 1 and 2, Uart, PCA, Watchdog or CAN s witch in X2 mode only if the cor- responding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.

Figure 5. Clock CPU Generation Diagram

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Figure 6. Mode Switching Waveforms

4129N–CAN–03/08 Register Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register Note: 1. This control bit is validated when the CPU c lock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = 0000 0000b 7 6 5 4 3 2 1 0 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description

7 CANX2

CAN clock (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle.

6 WDX2

Watchdog clock (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle.

5 PCAX2

Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle.

4 SIX2

Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle.

3 T2X2

Timer 2 clock (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle.

2 T1X2

Timer 1 clock (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle.

1 T0X2

Timer 0 clock (1) Clear to select 6 clock periods per peripheral cloc k cycle. Set to select 12 clock periods per peripheral clock cycle. 0 X2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.

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cally divided by 2 using the X2 Mode detailed in Section “Clock”. internal reset source such as a watchdog, PCA, timer, etc.

• VDD must reach the specified VDD range,
• The level on xtal1 input must be outside the speci fication (VIH, VIL). If one of these two conditions are not met, the mic rocontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the RST pin must be maintained unt il both of the above conditions are met. A reset is active when the level VIH1 is reach ed and when the pulse width covers the period of time where VDD and the oscillator are not stabilized. Two parameters have to be taken into account to determine the reset pulse width:
• VDD rise time (vddrst),
• Oscillator startup time (oscrst). To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 7.

Figure 7. Reset Circuitry two values of oscillator start-up time and two pull-down resistor values. Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor discharged, leading to a bad reset sequence.

periods is mode independent (X2 or X1). tor must be added as shown Figure 8. Figure 8. Reset Circuitry for WDT reset out usage this bit allows mapping of the bootloader in the code area, a reset failure can be critical. (write or erase) may corrupt the Flash on-chip memory. supply failure, power supply switched off). status of the Port pins during Idle mode is detailed in Table 14. instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the T89C51CC01 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode.

1. Generate an enabled interrupt.

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4129N–CAN–03/08 of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC01 and vectors the CPU to address C:0000h. Note: 1. During the time that execution resumes, the internal RAM cannot be accessed; how- ever, it is possible for the Port pins to be access ed. To avoid unexpected outputs at the Port pins, the instruction immediately followin g the instruction that activated Idle mode should not write to a Port pin or to the external RAM. 2. If Idle mode is invoked by ADC Idle, the ADC conv ersion completion will exit Idle. Power-down Mode The Power-down mode places the T89C51CC01 in a very low power state. Power-down mode stops the oscillator and freezes all clocks at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the pr ogram counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 14. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON regist er. The T89C51CC01 enters the Power-down mode upon execution of the instruction t hat sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-down Mode If VDD was reduced during the Power-down mode, do n ot exit Power-down mode until VDD is restored to the normal operating level. There are two ways to exit the Power-down mode: 1. Generate an enabled external interrupt. – The T89C51CC01 provides capability to exit from Po wer-down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 9) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 8). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode. Note: 1. The external interrupt used to exit Power-do wn mode must be configured as level sensitive (INT0# and INT1#) and must be assigned th e highest priority. In addition, the duration of the interrupt must be long enough t o allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. 2. Exit from power-down by external interrupt does n ot affect the SFRs nor the internal RAM content.

Figure 9. Power-down Exit Waveform Using INT1:0# Power-down mode should not write to a Port pin or to the external RAM.

1. Exit from power-down by reset redefines all the S FRs, but does not affect the internal

Table 14. Pin Conditions in Special Operating Modes

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4129N–CAN–03/08 Registers Table 15. PCON Register PCON (S:87h) – Power configuration Register Reset Value = 00X1 0000b 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description

7 SMOD1 Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3

6 SMOD0

Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

4 POF

Clear to recognize next reset type. Set by hardware when V cc rises from 0 to its nominal voltage. Can also be set by software.

3 GF1

One use is to indicate whether an interrupt occurre d during normal operation or during Idle mode.

2 GF0

One use is to indicate whether an interrupt occurre d during normal operation or during Idle mode. 1 PD Power-down Mode bit Cleared by hardware when an interrupt or reset occu rs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence.

0 IDL

Cleared by hardware when an interrupt or reset occu rs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.

1. The internal space mapped in three separate segme nts:

• the lower 128 Bytes RAM segment.
• the upper 128 Bytes RAM segment.
• the expanded 1024 Bytes RAM segment (XRAM). 2. The external space. A fourth internal segment is available but dedicate d to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 11 shows the internal and external data memory spaces organization.

Figure 10. Internal Memory - RAM Figure 11. Internal and External Data Memory Organization XRAM-XRAM

128 Bytes

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ing, and can be used for context switching in interrupt service routines. Table 16. Register Bank Selection addresses in this area are 00h to 7Fh. Figure 12. Lower 128 Bytes Internal RAM Organization EXTRAM = 1, the XRAM is selected. must then be initialized properly.

4 Banks of

8 Registers

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Figure 14. External Data Read Waveforms Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruction, P2 outputs S FR content.

Figure 15. External Data Write Waveforms Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruction, P2 outputs S FR content.

and reducing code size in case of intensive usage of external memory accesses. Figure 16. Dual Data Pointer Implementation using one data pointer as a “source” pointer and the other one as a “destination” pointer. enhanced algorithm libraries.

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Table 19. AUXR Register

7 CY Carry Flag

Carry out from bit 1 of ALU operands.

6 AC Auxiliary Carry Flag

Carry out from bit 1 of addition operands. Refer to Table 16 for bits description.

2 OV Overflow Flag

Overflow set by arithmetic operations.

1 F1 User Definable Flag 1

Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s. The value read from these bits are indeterminate. D o not set this bit. the RD/ and the WR/ pulse length is increased accor ding to the value of M0. The value read from this bit is indeterminate. Do n ot set this bit.

Table 20. AUXR1 Register

1 EXTRAM

0 - Internal XRAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access. 1 - ALE is active only during a MOVX or MOVC instru ction. The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT (1)

Clear this bit for disable boot Flash. The value read from this bit is indeterminate. Do n ot set this bit.

3 GF3 General-purpose Flag 3

1 - Reserved for Data Pointer Extension.

0 DPS

Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

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4129N–CAN–03/08 EEPROM Data Memory The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setti ng control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in tw o steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary fro m 1 up to 128 Bytes (the page size). When programming, only the data written in t he column latch is programmed and a ninth bit is used to obtain this feature. This pr ovides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. Write Data in the Column Latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM pro gramming sessions, all the addresses in the column latches must stay on the sa me page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches:

• Save and disable interrupt.
• Set bit EEE of EECON register
• Load DPTR with the address to write
• Store A register with the data to be written
• Execute a MOVX @DPTR, A
• If needed loop the three last instructions until t he end of a 128 Bytes page
• Restore interrupt. Note: The last page address used when loading the co lumn latch is the one used to select the page programming address. Programming The EEPROM programming consists of the following actions:
• writing one or more Bytes of one page in the colum n latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded.
• launching programming by writing the control seque nce (50h followed by A0h) to the EECON register.
• EEBUSY flag in EECON is then set by hardware to in dicate that programming is in progress and that the EEPROM segment is not availab le for reading.
• The end of programming is indicated by a hardware clear of the EEBUSY flag. Note: The sequence 5xh and Axh must be executed with out instructions between then other- wise the programming is aborted. Read Data The following procedure is used to read the data stored in the EEPROM memory:
• Save and disable interrupt
• Set bit EEE of EECON register
• Load DPTR with the address to read
• Execute a MOVX A, @DPTR
• Restore interrupt

4129N–CAN–03/08 ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_rd_eeprom_byte: ; Save and clear EA MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but i t is possible upto ;* 128 Bytes. ;* before execute this function, be sure the EEPROM is not BUSY api_ld_eeprom_cl: ; Save and clear EA MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_wr_eeprom: ; Save and clear EA MOV EECON, #050h MOV EECON, #0A0h ; Restore EA ret

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4129N–CAN–03/08 Registers Table 21. EECON Register EECON (S:0D2h) EEPROM Control Register Reset Value = XXXX XX00b Not bit addressable 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic Description 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the pro gramming. 3 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 2 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

1 EEE

Set to map the EEPROM space during MOVX instruction s (Write in the column latches) Clear to map the XRAM space during MOVX.

0 EEBUSY

Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.

available using specific programming tool. Figure 17. Program/Code Memory Organization stant from this location does not affect Ports 0 and 2.

1. Default factory programmed parts come with maximu m hardware protection. Execu-

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17.22 External Code Memory Access

the bus control signals (PSEN#, and ALE). describes the external memory interface signals. Figure 18. External Code Memory Interface Structure Figure 19) in the external program/code memory. mation on X2 mode see section “Clock “. form and do not provide precise timing information. For bus cycling parameters refer to the ‘AC-DC parameters’ section. Table 23. External Code Memory Interface Signals

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4129N–CAN–03/08 FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 20):

• The memory array (user space) 32K Bytes
• The Extra Row
• The Hardware security bits
• The column latch registers User Space This space is composed of a 32K Bytes Flash memory organized in 256 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Byt es. The extra row may contain infor- mation for boot loader usage. Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Cross Flash Memory Access

Description

The FM0 memory can be program only from FM1. Progra mming FM0 from FM0 or from external memory is impossible. The FM1 memory can be program only by parallel programming. The Table 24 show all software Flash access allowed. Table 24. Cross Flash Memory Access

• Map the memory spaces in the adressable space
• Launch the programming of the memory spaces
• Get the status of the Flash memory (busy/not busy) Mapping of the Memory Space By default, the user space is accessed by MOVC inst ruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD 1 in FCON register in accor- dance with Table 25. A MOVC instruction is then used for reading these spaces.

Table 25. FM0 Blocks Select Bits spaces to program according to FMOD1:0 bits.

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Table 26. Programming Spaces otherwise the programming is aborted.

1. Interrupts that may occur during programming time must be disabled to avoid any

spurious exit of the programming mode. Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.

• Save then disable interrupt and map the column lat ch space by setting FPS bit.
• Load the DPTR with the address to load.
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
• If needed loop the three last instructions until t he page is completely loaded.
• Unmap the column latch and Restore Interrupt Write to FCON Operation FPL3:0 FPS FMOD1 FMOD0 User

5 X 0 0 No action

5 X 0 1 No action

5 X 1 0 No action

5 X 1 1 No action

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Figure 22. Flash and Extra Row Programming Procedure

• Set FPS and map Hardware byte (FCON = 0x0C)
• Save and disable the interrupts.
• Load DPTR at address 0000h.
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
• Launch the programming by writing the data sequenc e 54h followed by A4h in FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared. The end of the programming indicated by the FBusy flag cleared.
• Restore the interrupts. Flash Spaces Programming Save and Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh End Programming Restore IT Column Latches Loading see Figure 21 FBusy Cleared? Clear Mode FCON = 00h

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Figure 24. Reading Procedure Note: 1. aa = 10 for the Hardware Security Byte. chip code and data located in FM0 and FM1. Table 27. Program Lock bit Preventing Flash Corruption See the “Power Management” section. external program memory returns non coded data.

2 P U U

on reset, and further parallel programming of the F lash is disabled.

3 U P U Same as 2, also verify through parallel programming interface is

4 U U P Same as 3, also external execution is disabled if c ode roll over beyond

4129N–CAN–03/08 Registers FCON RegisterFCON (S:D1h) Flash Control Register Reset Value = 0000 0000b 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7-4 FPL3:0 Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 26)

3 FPS

Set to map the column latch space in the data memor y space. Clear to re-map the data memory space. 2-1 FMOD1:0 Flash Mode See Table 25 or Table 26.

0 FBUSY

Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.

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• RAM
• ERAM (Expanded RAM access by movx)
• XRAM (eXternal RAM)
• EEPROM DATA
• FM0 (user flash)
• Hardware byte
• XROW
• Boot Flash
• Flash Column latch The table below provide the different kind of memory which can be accessed from differ- ent code location. Note: 1. RWW: Read While Write

Table 28. Cross Memory Access

Table 30. Read MOVX A, @DPTR Table 31. Write MOVX @DPTR,A

46 A/T89C51CC01

Table 32. Read MOVC A, @DPTR

0 X NA

1 X OK

1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to

• Before mounting the chip on the PCB, FM0 Flash can be programmed with the application code. FM1 is always pre programmed by A tmel with a bootloader (chip can be ordered with CAN bootloader or UART bootloader). (1)
• Once the chip is mounted on the PCB, it can be pro grammed by serial mode via the CAN bus or UART. Note: 1. The user can also program his own bootloader in FM1. This In-System-Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel provide to the customer also all the needed Appli- cation-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory. This allow the customer to have a full use of the 32-Kbyte user memory. Flash Programming and Erasure There are three methods of programming the Flash memory:
• The Atmel bootloader located in FM1 is activated b y the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by the user’s bootloader located in FM0 at [SBV]00h.
• A further method exists in activating the Atmel bo ot loader by hardware activation. See Section “Hardware Security Byte”.
• The FM0 can be programmed also by the parallel mod e using a programmer.

Figure 25. Flash Memory Mapping

48 A/T89C51CC01

4129N–CAN–03/08 Boot Process Software Boot Process Example Many algorithms can be used for the software boot p rocess. Below are descriptions of the different flags and Bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a re set) is the default Atmel factory pro- gramming. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FCh (no user boot loader in FM0). - To read or modify this byte, the APIs are used. Extra Byte (EB) and Boot Status Byte (BSB): - These Bytes are reserved for customer use. - To read or modify these Bytes, the APIs are used. Hardware Boot Process At the falling edge of RESET, the bit ENBOOT in AUX R1 register is initialized with the value of Boot Loader Jump Bit (BLJB). Further at the falling edge of RESET if the followi ng conditions (called Hardware condi- tion) are detected. The FCON register is initialize d with the value 00h and the PC is initialized with F800h (FM1 lower byte = Bootloader entry point). Hardware Conditions:

• PSEN low (1)
• EA high,
• ALE high (or not connected). The Hardware condition forces the bootloader to be executed, whatever BLJB value is. Then BLBJ will be checked. If no hardware condition is detected, the FCON regi ster is initialized with the value F0h. Then BLJB value will be checked. Conditions are:
• If bit BLJB = 1: User application in FM0 will be started at @0000h (standard reset).
• If bit BLJB = 0: Boot loader will be started at @F800h in FM1. Note: 1. As PSEN is an output port in normal operatin g mode (running user applications or bootloader applications) after reset it is recommended to release PSEN after the fall- ing edge of Reset is signaled. The hardware conditions are sampled at reset signal Falling Edge, thus they can be released at any time when reset input is low. 2. To ensure correct microcontroller startup, the PS EN pin should not be tied to ground during power-on.

Figure 26. Hardware Boot Process Algorithm

• Datasheet Bootloader CAN T89C51CC01
• Datasheet Bootloader UART T89C51CC01 XROW Bytes Table 33. XROW Mapping RESET Hardware condition? BLJB = = 0 bit ENBOOT in AUXR1 register is initialized with BLJB inverted. HardwareSoftware ENBOOT = 1 PC = F800h ENBOOT = 1 PC = F800h FCON = 00h FCON = F0h Boot Loader in FM1 ENBOOT = 0 PC = 0000h Yes Yes No No Application in FM0 (Example, if BLJB=0, ENBOOT is set (=1) during reset, thus the bootloader is executed after the reset) Description Default Value Address Copy of the Manufacturer Code 58h 30h Copy of the Device ID#1: Family code D7h 31h Copy of the Device ID#2: Memories size and type F7h 6 0h Copy of the Device ID#3: Name and Revision FFh 61h

50 A/T89C51CC01

4129N–CAN–03/08 Hardware Security Byte Table 34. Hardware Security Byte After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: 1. Only the 4 MSB bits can be accessed by soft ware. 2. The 4 LSB bits can only be accessed by parallel m ode. 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description

7 X2B

Set this bit to start in standard mode. Clear this bit to start in X2 mode.

6 BLJB

• 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM 1. 5-3 - Reserved The value read from these bits are indeterminate. 2-0 LB2:0 Lock Bits

52 A/T89C51CC01

Figure 29. UART Timing in Mode 1 Figure 30. UART Timing in Modes 2 and 3 nication feature is enabled (SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

4129N–CAN–03/08 Given Address Each device has an individual address that is speci fied in the SADDR register; the SADEN register is a mask byte that contains don’t-c are bits (defined by zeros) to form the device’s given address. The don’t-care bits pro vide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b . For example: SADDR0101 0110b SADEN 1111 1100b Given0101 01XXb Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN 1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN 1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN 1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; f or slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. T he following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN 1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN 1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN 1111 1101b Given1111 1111b

54 A/T89C51CC01

and B, but not slave C, the master can send and address FBh. Clear to reset the error state, not cleared by a va lid stop bit. Set by hardware when an invalid stop bit is detecte d. Refer to SM1 for serial port mode selection.

6 SM1

5 SM2

Clear to disable multiprocessor communication featu re. Set to enable multiprocessor communication feature in mode 2 and 3.

4 REN

Clear to disable serial reception. Set to enable serial reception.

3 TB8

Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.

2 RB8

Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. Clear to acknowledge interrupt. stop bit in the other modes. Clear to acknowledge interrupt. Figure 30. in the other modes.

Table 36. SADEN Register Table 37. SADDR Register Table 38. SBUF Register

56 A/T89C51CC01

Table 39. PCON Register Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. The value read from this bit is indeterminate. Do n ot set this bit. Clear to recognize next reset type. Cleared by user for general-purpose usage. Set by user for general-purpose usage. Cleared by user for general-purpose usage. Set by user for general-purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.

4129N–CAN–03/08 Timers/Counters The T89C51CC01 implements two general-purpose, 16-b it Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be indepen dently configured to operate in a variety of modes as a Timer or an event Counter. Wh en operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter coun ts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter a re described in the following sections. Timer/Counter Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (T Rx) in TCON register (see Figure 40) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the T imer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx an d TLx Timer registers. Timer regis- ters can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behav- ior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Co unter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of o peration, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is F PER /6, i.e. F OSC /12 in standard mode or F OSC /6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer regist er counts the negative transitions on the Tx external input pin. The external input is sa mpled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock period s) to recognize a negative transition, the maximum count rate is F PER /12, i.e. F OSC /24 in standard mode or F OSC /12 in X2 mode. There are no restrictions on the duty cycle o f the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or event Counte r in four modes of operation. Figure 31 to Figure 34 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMO D register (see Figure 41) and bits 0, 1, 4 and 5 of TCON register (see Figure 40). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows ex ternal pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter- rupt request. It is important to stop Timer/Counter before changing mode.

58 A/T89C51CC01

ignored. Prescaler overflow increments TH0 register. Figure 31. Timer/Counter x (x = 0 or 1) in Mode 0 cascade (see Figure 32). The selected input increments TL0 register. Figure 32. Timer/Counter x (x = 0 or 1) in Mode 1

60 A/T89C51CC01

4129N–CAN–03/08 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol- lowing comments help to understand the differences:

• Timer 1 functions as either a Timer or event Count er in three modes of operation. Figure 31 to Figure 33 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.
• Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 41) and bits 2, 3, 6 and 7 of TCON register (see Figure 40). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
• Timer 1 can serve as the Baud Rate Generator for t he Serial Port. Mode 2 is best suited for this purpose.
• For normal Timer operation (GATE1 = 0), setting TR 1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation.
• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.
• When Timer 0 is in mode 3, it uses Timer 1’s overf low flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
• It is important to stop Timer/Counter before chang ing mode. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 31). The upper 3 bits of TL1 register ar e ignored. Prescaler overflow incre- ments TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH 1 and TL1 registers connected in cascade (see Figure 32). The selected input increments TL1 register. Mode 2 (8-bit Timer with Auto- Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 re gister) with automatic reload from TH1 register on overflow (see Figure 33). TL1 overfl ow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hol d its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags ar e cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 35. Timer Interrupt System

62 A/T89C51CC01

4129N–CAN–03/08 Registers Table 40. TCON Register TCON (S:88h) Timer/Counter Control Register Reset Value = 0000 0000b 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description

7 TF1

Cleared by hardware when processor vectors to inter rupt routine. Set by hardware on Timer/Counter overflow, when Tim er 1 register overflows.

6 TR1

Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.

5 TF0

Cleared by hardware when processor vectors to inter rupt routine. Set by hardware on Timer/Counter overflow, when Tim er 0 register overflows.

4 TR0

Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0.

3 IE1

Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin.

2 IT1

Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1.

1 IE0

Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin.

0 IT0

Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

Table 41. TMOD Register Notes: 1. Reloaded from TH1 at overflow.

1. Reloaded from TH0 at overflow.

7 GATE1

Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.

6 C/T1#

Clear for Timer operation: Timer 1 counts the divid ed-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

5 M11 Timer 1 Mode Select Bits

0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit pr escaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter.

4 M01

3 GATE0

Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

2 C/T0#

Clear for Timer operation: Timer 0 counts the divid ed-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

1 M10

0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit pre scaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 b its.

0 M00

64 A/T89C51CC01

Table 42. TH0 Register Table 43. TL0 Register Table 44. TH1 Register

Table 45. TL1 Register

66 A/T89C51CC01

Timer 2 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52.

1. C/T2 selects F T2 clock /6 (timer operation) or external pin T2 (counter op eration) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input.

• Auto-reload mode (up or down counter)
• Programmable clock-output Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto- matic reload. This feature is controlled by the DCE N bit in T2MOD register (See Table 48). Setting the DCEN bit enables timer 2 to c ount up or down as shown in

Figure 36. In this mode the T2EX pin controls the counting direction. in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. Figure 36. Auto-Reload Mode Up/Down Counter

• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
• Enter a 16-bit initial value in timer registers TH 2/TL2. It can be the same as the reload value or different depending on the application.
• To start the timer, set TR2 run control bit in T2C ON register. It is possible to use timer 2 as a baud rate genera tor and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 37. Clock-Out Mode

68 A/T89C51CC01

4129N–CAN–03/08 Registers Table 46. T2CON Register T2CON (S:C8h) Timer 2 Control Register Reset Value = 0000 0000b Bit addressable 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic Description

7 TF2

TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow.

6 EXF2

Set when a capture or a reload is caused by a negat ive transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software.

5 RCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for se rial port in mode 1 or 3.

4 TCLK

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for s erial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 oper ation. Set to cause a capture or reload when a negative tr ansition on T2EX pin is detected, if timer 2 is not used to clock the seria l port.

2 TR2

Clear to turn off timer 2. Set to turn on timer 2.

1 C/T2#

Timer/Counter 2 Select bit Clear for timer operation (input from internal cloc k system: F OSC ). Set for counter operation (input from T2 input pin) .

0 CP/RL2#

Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer i s forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negati ve transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

Table 47. T2MOD Register Table 48. TH2 Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.

1 T2OE

Clear to program P1.0/T2 as clock input or I/O port . Set to program P1.0/T2 as clock output.

0 DCEN

Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.

70 A/T89C51CC01

Table 49. TL2 Register Table 50. RCAP2H Register Table 51. RCAP2L Register 7-0 High Byte of Timer 2 Reload/Capture. 7-0 Low Byte of Timer 2 Reload/Capture.

ter. When exiting reset, the WDT is -by default- disable. Note: When the Watchdog is enable it is impossible t o change its period. Figure 38. Watchdog Timer

72 A/T89C51CC01

Table 52. Machine Cycle Count Table 53. Time-Out Computation

4129N–CAN–03/08 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which mean s the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting P ower-down with an interrupt is sig- nificantly different. The interrupt shall be held l ow long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter- rupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51CC01 while in Idle mode, the user should alwa ys set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. Register Table 54. WDTPRG Register WDTPRG (S:A7h) Watchdog Timer Duration Programming Register Reset Value = XXXX X000b 7 6 5 4 3 2 1 0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 6 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 4 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 3 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

2 S2 Watchdog Timer Duration selection bit 2

Work in conjunction with bit 1 and bit 0.

1 S1 Watchdog Timer Duration selection bit 1

Work in conjunction with bit 2 and bit 0.

0 S0 Watchdog Timer Duration selection bit 0

Work in conjunction with bit 1 and bit 2.

74 A/T89C51CC01

Table 55. WDTRST Register sequence without instruction between these two sequences.

achieves a bitrate of 1-Mbit/sec. at 8 MHz 1 Crystal frequency in X2 mode. Note: 1. At BRP = 1 sampling point will be fixed. and ISO 11519-2 for low speed. dynamically. The identifier with the lowest binary number has the highest priority. highest priority and do not re-attempt transmission until the bus is available again. as CAN 2.0 B, supports a length of 29 bits for the identifier. Figure 39. CAN Standard Frames

76 A/T89C51CC01

there is no following bus access by any node, the bus remains idle. Figure 40. CAN Extended Frames frame in CAN standard frame format, and transmitted as recessive in the other case. has priority over the message in extended format. ing edge SOF and on each recessive to dominant edge. the smallest discrete timing resolution used by a CAN node.

Figure 41. CAN Bit Construction Synchronization Segment The first segment is used to synchronize the various bus nodes. is expected to occur within this segment by the receiving nodes. Propagation Time Segment This segment is used to com pensate for signal delays across the network. through the transceivers of the bus nodes. Phase Segment 1 Phase Segment 1 is used to compensat e for edge phase errors. This segment may be lengthened during resynchronization. Phase Segment 2 This segment is also used to compens ate for edge phase errors. Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit. less than the Information processing Time. adjust the sample point and the end of the bit time.

78 A/T89C51CC01

4129N–CAN–03/08 Bit Shortening If, on the other hand, the transmitte r oscillator is faster than the receiver one, the n ext falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time Synchronization Jump Width The limit to the amount o f lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width. This segment may not be longer than Phase Segment 2. Programming the Sample Point Programming of the samp le point allows "tuning" of the characteristics to suit the bus. Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchroniza- tion Jump Width can be programmed to its maximum. T his maximum capacity to shorten or lengthen the bit time decreases the sens itivity to node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used. Late sampling allows more Time Quanta in the Propagation Time Segment which allows a poorer bus topology and maximum bus length. Arbitration Figure 42. Bus Arbitration The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”. During transmission, arbitration on the CAN bus can be lost to a competing device with a higher priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. The bus access conflict is resolved during the arbi tration field mostly over the identifier value. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. RTR bit). Errors The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: Error at Message Level • Cyclic Redundancy Check (CRC ) The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been a CRC error.

• Frame Check This mechanism verifies the structure of the transmitted frame by checking the bit fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". node A TXCAN node B TXCAN ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0SOFSOF RTR IDE CAN bus - - - - - - - - - Arbitration lost Node A loses the bus Node B wins the bus

4129N–CAN–03/08

• ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. Error at Bit Level • Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter.
• Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing. Error Signalling If one or more errors are discovere d by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". This prevents other nodes accepting the message and thus ensures the consiste ncy of data throughout the net- work. After transmission of an erroneous message th at has been aborted, the sender automatically re-attempts transmission. CAN Controller

The CAN Controller accesses are made through SFR. Several operations are possible by SFR:

• arithmetic and logic operations, transfers and pro gram control (SFR is accessible by direct addressing).
• 15 independent message objects are implemented, a pagination system manages their accesses. Any message object can be programmed in a reception buffer block (even non-consec- utive buffers). For the reception of defined messag es one or several receiver message objects can be masked without participating in the buffer feature. An IT is generated when the buffer is full. The frames following the b uffer-full interrupt will not be taken into account until at least one of the buffer message ob jects is re-enabled in reception. Higher priority of a message object for reception o r transmission is given to the lower message object number. The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP register. This timer starts counting as soon as the CAN con- troller is enabled by the ENA bit in the CANGCON register. The Time Trigger Communication (TTC) protocol is supported by the T89C51CC01.

80 A/T89C51CC01

Figure 43. CAN Controller Block Diagram register (CANPAGE) as illustrate in Figure 44.

Figure 44. CAN Controller Memory Organization

8 Bytes

82 A/T89C51CC01

each access. The range of this counter is 8. Note that the maibox is a pure RAM, dedicated to on e message object, without overlap. lations or tests can be executed in the mailbox area which provide quicker access.

• General Control (CANGCON),
• Bit Timing (CANBT 1, 2 and 3),
• And for each page of 15 message objects – message object Control (CANCONCH), – message object Status (CANSTCH). During operation, the CAN Enable message object reg isters 1 and 2 (CANEN 1 and 2) gives a fast overview of the message objects availability. The CAN messages can be handled by interrupt or polling modes. A message object can be configured as follows:
• Transmit message object,
• Receive message object,
• Receive buffer message object.
• Disable This configuration is made in the CONCH field of th e CANCONCH register (see Table 56). When a message object is configured, the correspond ing ENCH bit of CANEN 1 and 2 register is set.

Table 56. Configuration for CONCH1:2 message object, it is necessary to re-write the configuration in CANCONCH register.

sage objects, and with no limitation in number of message objects used up to 15. Figure 45. Buffer mode The same acceptance filter must be defined for each message objects of the buffer. When there is no mask on the identifier or the IDE, all messages are accepted. A received frame will always be stored in the lowest free message object. the message object re-enabled in buffer reception in order to free the message object. message objects is re-enabled in reception. This flag must be cleared by the software in order to acknowledge the interrupt.

84 A/T89C51CC01

• Transmission interrupt,
• Reception interrupt,
• Interrupt on error (bit error, stuff error, crc er ror, form error, acknowledge error),
• Interrupt when Buffer receive is full,
• Interrupt on overrun of CAN Timer.

Figure 46. CAN Controller Interrupt Structure

• Enable General CAN IT in the interrupt system regi ster,
• Enable interrupt by message object, EICHi,
• Enable transmission interrupt, ENTX. To enable a reception interrupt:
• Enable General CAN IT in the interrupt system regi ster,
• Enable interrupt by message object, EICHi, SIT i i=0 i=14 OVRIT ENRX CANGIE.5 ENTX CANGIE.4 ENERCH CANGIE.3 ENBUF CANGIE.2 ECAN IEN1.0 RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANSTCH.4 SERR i CANSTCH.3 FERR i CANSTCH.1 CERR i CANSTCH.2 AERR i CANSTCH.0 EICH i CANIE1/2 OVRTIM CANGIT.5 OVRBUF CANGIT.4 FERG CANGIT.1 AERG CANGIT.0 SERG CANGIT.3 CERG CANGIT.2 ENERG CANGIE.1 ETIM IEN1.2 SIT i CANSIT1/2 CANIT CANIT CANGIT.7

4129N–CAN–03/08

• Enable reception interrupt, ENRX. To enable an interrupt on message object error:
• Enable General CAN IT in the interrupt system regi ster,
• Enable interrupt by message object, EICHi,
• Enable interrupt on error, ENERCH. To enable an interrupt on general error:
• Enable General CAN IT in the interrupt system regi ster,
• Enable interrupt on error, ENERG. To enable an interrupt on Buffer-full condition:
• Enable General CAN IT in the interrupt system regi ster,
• Enable interrupt on Buffer full, ENBUF. To enable an interrupt when Timer overruns:
• Enable Overrun IT in the interrupt system register . When an interrupt occurs, the corresponding message object bit is set in the SIT register. To acknowledge an interrupt, the corresponding CANS TCH bits (RXOK, TXOK,...) or CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application. When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a message object error occurs and is set in CA NSTCH register, no general error are set in CANGIE register.

86 A/T89C51CC01

quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.

• BRP: Baud Rate Prescaler.
• TQ: Time Quantum (output of Baud Rate Prescaler).
• SYNS: SYNchronization Segment is 1 TQ long.
• PRS: PRopagation time Segment is programmable to b e 1, 2, ..., 8 TQ long.
• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
• PHS2: PHase Segment 2 is programmable to be superi or or equal to the INFORMATION PROCESSING TIME and inferior or equal to TPHS1.
• INFORMATION PROCESSING TIME is 2 TQ.
• SJW: (Re) Synchronization Jump Width is programmab le to be minimum of PHS1 and 4. The total number of TQ in a bit time has to be programmed at least from 8 to 25.

Figure 47. Sample And Transmission Point

Figure 48. General Structure of a Bit Period Verify that the CAN baud rate you want is an intege r division of FCAN clock.

88 A/T89C51CC01

• error active
• error passive
• bus off An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communica- tion, but when an error is detected, a passive erro r frame is sent. Also, after a transmission, an error passive unit will wait before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two error counters (TEC and REC) are implemented. See CAN Specification for details on Fault confinement.

Figure 49. Line Error Mode

11 Consecutive

ID+RTR+RB+IDE received are written over the ID TAG Registers. Figure 50. Acceptance filter block diagram To accept only ID = 318h in part A.

90 A/T89C51CC01

4129N–CAN–03/08 Data and Remote Frame Description of the different steps for:

• Data Frame
• Remote Frame, With Automatic Reply,
• Remote Frame u uu uu 0 1 x 0 0 u uu uu ENCH RTR RPLV TXOK RXOK 0 1 x 0 0 c uc uu 0 0 x 1 0 u cc uu 0 0 x 0 1 DATA FRAME Node A Node B ENCH RTR RPLV TXOK RXOK message object in reception message object disabled message object in message object disabled transmission u uu uu 1 1 x 0 0 c uu uc 0 1 x 1 0 u cc uu 0 0 x 0 1 REMOTE FRAME DATA FRAME u uu uu 1 1 1 0 0 u uu cc 0 1 0 0 0 c uc cu 0 0 0 1 0 ENCH RTR RPLV TXOK RXOK ENCH RTR RPLV TXOK RXOK (immediate) message object in reception message object in transmission message object disabled message object in message object in message object disabled by CAN controller by CAN controller transmission reception u uu uu 1 1 x 0 0 u uu uu ENCH RTR RPLV TXOK RXOK 1 1 0 0 0 c uu uc 0 1 x 1 0 u cc uu 1 0 0 0 1 REMOTE FRAME ENCH RTR RPLV TXOK RXOK u uu uu 0 1 x 0 0 c uc uu 0 0 x 1 0 u cc uc 0 0 x 0 1 DATA FRAME (deferred) u : modified by user i c : modified by CAN i message object in reception message object in transmission by user message object disabled message object disabled message object in message object in message object disabled reception by user transmission

• Time Trigger Communication: – Capture of this timer value in the CANTTCH and CAN TTCL registers on Start Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in the CANGCON register, when the network is configured in TTC by the TTC bit in the CANGCON register. Note: In this mode, CAN only sends the frame once, even if an error occurs .
• Message Stamping – Capture of this timer value in the CANSTMPH and CA NSTMPL registers of the message object which received or sent the frame. – All messages can be stamps. – The stamping of a received frame occurs when the R xOk flag is set. – The stamping of a sent frame occurs when the TxOk flag is set. The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base. When the timer roll-over from FFFFh to 0000h, an in terrupt is generated if the ETIM bit in the interrupt enable register IEN1 is set.

Figure 51. Block Diagram of CAN Timer

92 A/T89C51CC01

ing the received messages. It cannot send any messa ge. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 52. Autobaud Mode

4129N–CAN–03/08 // Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receiv e only standard (11-bit identi- fier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this message object CANIE2 = 08h // Clear the status and control register CANSTCH = 00h CANCONCH = 00h // Init the acceptance filter to accept only message 100h in standard mode CANIDT1 = 20h CANIDT2 = 00h CANIDT3 = 00h CANIDT4 = 00h CANIDM1 = FFh CANIDM2 = FFh CANIDM3 = FFh CANIDM4 = FFh // Enable channel in reception CANCONCH = 88h // enable reception Note: To enable the CAN interrupt in reception: EA = 1 ECAN = 1 CANGIE = 20h 3. Send a message on the message object 12 // Select the message object 12 CANPAGE = C0h // Enable the interrupt on this message object CANIE1 = 01h // Clear the Status register CANSTCH = 00h; // load the identifier to send (ex: 555h) CANIDT1 = AAh; CANIDT2 = A0h; // load data to send CANMSG = 00h CANMSG = 01h CANMSG = 02h CANMSG = 03h CANMSG = 04h CANMSG = 05h CANMSG = 06h CANMSG = 07h // configure the control register CANCONCH = 18h

94 A/T89C51CC01

4129N–CAN–03/08 4. Interrupt routine // Save the current CANPAGE // Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which k ind of interrupt is generated // Manage the interrupt // Clear the status register CANSTCH = 00h; // if it is not a channel interrupt but a general i nterrupt // Manage the general interrupt and clear CANGIT re gister // restore the old CANPAGE

Table 57. CAN SFR’s With Reset Values

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4129N–CAN–03/08 Registers Table 58. CANGCON Register CANGCON (S:ABh) CAN General Control Register Reset Value = 0000 0000b 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES Bit Number Bit Mnemonic Description

7 ABRQ

Not an auto-resetable bit. A reset of the ENCH bit (message object control and DLC register) is done for each message object. The pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate sta tus flags, TXOK or RXOK.

6 OVRQ

Overload frame request (initiator) Auto-resetable bit. Set to send an overload frame after the next receiv ed message. Cleared by the hardware at the beginning of transmi ssion of the overload frame.

5 TTC

Network in Timer Trigger Communication set to select node in TTC. clear to disable TTC features.

4 SYNCTTC

When this bit is set the TTC timer is caught on the last bit of the End Of Frame. When this bit is clear the TTC timer is caught on t he Start Of Frame. This bit is only used in the TTC mode.

3 AUTOBAUD

set to active listening mode. Clear to disable listening mode 2 TEST Test mode. The test mode is intended for factory te sting and not for customer use.

1 ENA/STB

Enable/Standby CAN Controller When this bit is set, it enables the CAN controller and its input clock. When this bit is clear, the on-going communication is terminated normally and the CAN controller state of the machine is frozen ( the ENCH bit of each message object does not change). In the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated and the input clock is st opped in the CAN controller. During the disable mode, the registers and the mail box remain accessible. Note that two clock periods are needed to start the CAN controller state of the machine.

0 GRES

General Reset (software reset) Auto-resetable bit. This reset command is ‘ORed’ wi th the hardware reset in order to reset the controller. After a reset, the c ontroller is disabled.

Table 59. CANGSTA Register The values read from this bit is indeterminate. Do not set this bit.

6 OVFG

The values read from this bit is indeterminate. Do not set this bit.

4 TBSY

bit is also active during an InterFrame Spacing if a frame must be sent. This flag does not generate an interrupt.

3 RBSY

This flag does not generate an interrupt.

2 ENFG

bit gives the true state of a chosen mode. This flag does not generate an interrupt.

1 BOFF

0 ERRP Error Passive Mode

98 A/T89C51CC01

Table 60. CANGIT Register Note: 1. This field is Read Only.

7 CANIT

It can be used in the case of the polling method. The values read from this bit is indeterminate. Do not set this bit.

5 OVRTIM

This status bit is set when the CAN timer switches 0xFFFF to 0x0000. If the bit ETIM in the IE1 register is set, an inte rrupt is generated. Clear this bit in order to reset the interrupt.

4 OVRBUF

This bit is set when the buffer is full.

3 SERG

Detection of more than five consecutive bits with t he same polarity. This flag can generate an interrupt. resetable by u ser.

2 CERG

from the start of frame up to the data field. This flag can generate an interrupt. resetable by u ser.

1 FERG

This flag can generate an interrupt. resetable by u ser.

0 AERG

No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt. resetable by u ser.

Table 61. CANTEC Register Table 62. CANREC Register

100 A/T89C51CC01

Table 63. CANGIE Register Table 64. CANEN1 Register The values read from these bits are indeterminate. Do not set these bits.

5 ENRX

4 ENTX

3 ENERCH

2 ENBUF

1 ENERG

The value read from this bit is indeterminate. Do n ot set this bit. The values read from this bit is indeterminate. Do not set this bit. 1 - message object is enabled.

Table 65. CANEN2 Register Table 66. CANSIT1 Register 1 - message object is enabled. The values read from this bit is indeterminate. Do not set this bit. 1 - IT turned on. Reset when interrupt condition is cleared by user.

102 A/T89C51CC01

Table 67. CANSIT2 Register Table 68. CANIE1 Register 1 - IT turned on. Reset when interrupt condition is cleared by user. The values read from this bit is indeterminate. Do not set this bit. IECH14:8 = 0b 0000 1100 -> Enable IT’s of message o bjects 11 and 10.

Table 69. CANIE2 Register Table 70. CANBT1 Register abled with the ENA bit of the CANGCON register set to 0. No default value after reset. IECH7:0 = 0b 0000 1100 -> Enable IT’s of message ob jects 3 and 2. The value read from this bit is indeterminate. Do n ot set this bit. determines the individual bit timing. The value read from this bit is indeterminate. Do n ot set this bit.

104 A/T89C51CC01

Table 71. CANBT2 Register abled with the ENA bit of the CANGCON register set to 0. No default value after reset. The value read from this bit is indeterminate. Do n ot set this bit. The synchronization jump width defines the maximum number of clock cycles. A bit period may be shortened or lengthened by a re -synchronization. The value read from this bit is indeterminate. Do n ot set this bit. bus line, the input comparator delay and the output driver delay. The value read from this bit is indeterminate. Do n ot set this bit.

Table 72. CANBT3 Register abled with the ENA bit of the CANGCON register set to 0. No default value after reset. The value read from this bit is indeterminate. Do n ot set this bit. be shortened by the re-synchronization jump width. be lengthened by the re-synchronization jump width.

0 SMP

0 - once, at the sample point. majority decision of the three values.

106 A/T89C51CC01

Table 73. CANPAGE Register Table 74. CANCONCH Register The available numbers are: 0 to 14 (see Figure 44).

3 AINC

0 - auto-increment of the index (default value). 1 - non-auto-increment of the index. Byte location of the data field for the defined mes sage object (see Figure 44).

5 RPLV

4 IDE

0 - CAN standard rev 2.0 A (ident = 11 bits). 1 - CAN standard rev 2.0 B (ident = 29 bits). Number of Bytes in the data field of the message. The range of DLC is from 0 up to 8. This value is updated when a frame is received (dat a or remote frame).

Table 75. CANSTCH Register No default value after reset.

7 DLCW

6 TXOK

The communication enabled by transmission is comple ted. This flag can generate an interrupt and it must be cleared by software.

5 RXOK

The communication enabled by reception is completed . message object (0 to 13) is updated first. This flag can generate an interrupt and it must be cleared by software.

4 BERR

The bit value monitored is different from the bit v alue sent. This flag can generate an interrupt and it must be cleared by software.

3 SERR

Detection of more than five consecutive bits with t he same polarity. This flag can generate an interrupt and it must be cleared by software.

2 CERR

from the start of frame up to the data field. This flag can generate an interrupt and it must be cleared by software.

1 FERR

This flag can generate an interrupt.

0 AERR

No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt and it must be cleared by software.

108 A/T89C51CC01

Table 76. CANIDT1 Register for V2.0 part A No default value after reset. Table 77. CANIDT2 Register for V2.0 part A No default value after reset. Table 78. CANIDT3 Register for V2.0 part A No default value after reset. The values read from these bits are indeterminate. Do not set these bits. The values read from these bits are indeterminate. Do not set these bits.

Table 79. CANIDT4 Register for V2.0 part A No default value after reset. Table 80. CANIDT1 Register for V2.0 part B No default value after reset. Table 81. CANIDT2 Register for V2.0 part B No default value after reset. The values read from these bits are indeterminate. Do not set these bits. 2 RTRTAG Remote Transmission Request Tag Value . The values read from this bit are indeterminate. Do not set these bit. 0 RB0TAG Reserved Bit 0 Tag Value.

110 A/T89C51CC01

Table 82. CANIDT3 Register for V2.0 part B No default value after reset. Table 83. CANIDT4 Register for V2.0 part B No default value after reset. Table 84. CANIDM1 Register for V2.0 part A No default value after reset.

2 RTRTAG Remote Transmission Request Tag Value

1 RB1TAG Reserved bit 1 Tag Value

0 RB0TAG Reserved bit 0 Tag Value

Table 85. CANIDM2 Register for V2.0 part A No default value after reset. Table 86. CANIDM3 Register for V2.0 part A No default value after reset. The values read from these bits are indeterminate. Do not set these bits. The values read from these bits are indeterminate.

112 A/T89C51CC01

Table 87. CANIDM4 Register for V2.0 part A Note: The ID Mask is only used for reception. No default value after reset. Table 88. CANIDM1 Register for V2.0 part B Note: The ID Mask is only used for reception. No default value after reset. The values read from these bits are indeterminate. Do not set these bits.

2 RTRMSK

The value read from this bit is indeterminate. Do n ot set this bit.

0 IDEMSK

Table 89. CANIDM2 Register for V2.0 part B Note: The ID Mask is only used for reception. No default value after reset. Table 90. CANIDM3 Register for V2.0 part B Note: The ID Mask is only used for reception. No default value after reset.

114 A/T89C51CC01

Table 91. CANIDM4 Register for V2.0 part B Note: The ID Mask is only used for reception. No default value after reset. Table 92. CANMSG Register No default value after reset. The value read from this bit is indeterminate. Do n ot set this bit.

Table 93. CANTCON Register Table 94. CANTIMH Register Table 95. CANTIML Register

10 CANGTIM 9 CANGTIM 8

116 A/T89C51CC01

Table 96. CANSTMPH Register Table 97. CANSTMPL Register Table 98. CANTTCH Register

10 TIMSTMP 9 TIMSTMP 8

Table 99. CANTTCL Register

118 A/T89C51CC01

4129N–CAN–03/08 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced soft ware overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals:

• PCA clock frequency/6 (see “clock” section)
• PCA clock frequency/2
• Timer 0 overflow
• External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or falling edge capture,
• software timer,
• high-speed output,
• pulse width modulator. Module 4 can also be programmed as a Watchdog timer . see the "PCA Watchdog Timer" section. When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules s hare Port 1 for external I/Os. These pins are listed below. If the pin is not used for the PCA, it can still be used for standard I/O. PCA Timer The PCA timer is a common time base for all five mo dules (see Figure 53). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 8) and can be programmed to run at:
• 1/6 the PCA clock frequency.
• 1/2 the PCA clock frequency.
• the Timer 0 overflow.
• the input on the ECI pin (P1.2). PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1 16-bit Module 2 P1.5/CEX2 16-bit Module 3 P1.6/CEX3 16-bit Module 4 P1.7/CEX4

Figure 53. PCA Timer/Counter The CMOD register includes three additional bits associated with the PCA.

• The CIDL bit which allows the PCA to stop during i dle mode.
• The WDTE bit which enables or disables the Watchdo g function on module 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF in CCON register to be set when the PCA timer overflows. The CCON register contains the run control bit for the PCA and the flags for the PCA timer and each module.
• The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit.
• The CF bit is set when the PCA counter overflows a nd an interrupt will be generated if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.
• The CCF0:4 bits are the flags for the modules (CCF 0 for module0...) and are set by hardware when either a match or a capture occurs. These flags also can be cleared by software. PCA Modules Each one of the five compare/capture modules has si x possible functions. It can perform:
• 16-bit Capture, positive-edge triggered
• 16-bit Capture, negative-edge triggered
• 16-bit Capture, both positive and negative-edge tr iggered
• 16-bit Software Timer
• 16-bit High Speed Output
• 8-bit Pulse Width Modulator. In addition module 4 can be used as a Watchdog Timer. CIDL CPS1 CPS0 ECF It CH CL 16 bit up counter To PCA modules FPca/6 FPca/2 T0 OVF P1.2 Idle CMOD 0xD9 WDTE CF CR CCON 0xD8 CCF4 CCF3 CCF2 CCF1 CCF0 overflow

120 A/T89C51CC01

• The ECCF bit enables the CCF flag in the CCON regi ster to generate an interrupt when a match or compare occurs in the associated module.
• The PWM bit enables the pulse width modulation mod e.
• The TOG bit when set causes the CEX output associa ted with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register.
• The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register.
• The two bits CAPN and CAPP in CCAPMn register dete rmine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled.
• The bit ECOM in CCAPM register when set enables th e comparator function. PCA Interrupt

Figure 54. PCA Interrupt System ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

122 A/T89C51CC01

each time a match occurs between the PCA counter and the module’s capture registers. Figure 57. PCA High Speed Output Mode

Figure 58. PCA PWM Mode not cause the RST pin to be driven high.

• periodically change the compare value so it will n ever match the PCA timer,
• periodically change the PCA timer value so it will never match the compare values, or
• disable the Watchdog by clearing the WDTE bit befo re a match occurs and then re- enable it. The first two options are more reliable because the Watchdog timer is never disabled as in the third option. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most appli- cations the first solution is the best option. CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CCAPnL CCAPnH 8-Bit Comparator CL (8 bits) “0” “1” CL < CCAPnL CL > = CCAPnL CEX PWMn CCAPMn.1 ECOMn CCAPMn.6

124 A/T89C51CC01

4129N–CAN–03/08 PCA Registers Table 100. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 00XX X000b 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description

7 CIDL

PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked.

6 WDTE

Clear to disable Watchdog Timer function on PCA Mod ule 4, Set to enable it. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 4 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 3 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 2-1 CPS1:0 EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca /4)

0 ECF

Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generat e an interrupt. Set to enable CF bit in CCON register to generate a n interrupt.

Table 101. CCON Register interrupt request if the ECF bit in CMOD register i s set. Must be cleared by software. Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. The value read from this bit is indeterminate. Do n ot set this bit.

4 CCF4

interrupt request if the ECCF 4 bit in CCAPM 4 regi ster is set. Must be cleared by software.

3 CCF3

interrupt request if the ECCF 3 bit in CCAPM 3 regi ster is set. Must be cleared by software.

2 CCF2

interrupt request if the ECCF 2 bit in CCAPM 2 regi ster is set. Must be cleared by software.

1 CCF1

interrupt request if the ECCF 1 bit in CCAPM 1 regi ster is set. Must be cleared by software.

0 CCF0

interrupt request if the ECCF 0 bit in CCAPM 0 regi ster is set. Must be cleared by software.

126 A/T89C51CC01

Table 102. CCAPnH Registers Table 103. CCAPnL Registers

Table 104. CCAPMn Registers The Value read from this bit is indeterminate. Do n ot set this bit.

6 ECOMn

Clear to disable the Compare function. Set to enable the Compare function. output, the Pulse Width Modulator (PWM) and the Wat chdog Timer (WDT).

5 CAPPn

Clear to disable the Capture function triggered by a positive edge on CEXx pin.

4 CAPNn

Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a n egative edge on CEXx pin.

3 MATn

CCFx bit in CCON register, flagging an interrupt.

2 TOGn

The toggle mode is configured by setting ECOMx, MAT x and TOGx bits.

1 PWMn

0 ECCFn

Clear to disable CCFx bit in CCON register to gener ate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.

128 A/T89C51CC01

Table 105. CH Register Table 106. CL Register

4129N–CAN–03/08 Analog-to-Digital Converter (ADC) This section describes the on-chip 10 bit analog-to -digital converter of the T89C51CC01. Eight ADC channels are available for sa mpling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). AD CIN is converted by the 10-bit cascaded potentiometric ADC. Two modes of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADC ON register and start conversion. The device is in a pseudo-idle mode, the CPU does n ot run but the peripherals are always running. This mode allows digital noise to b e as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of c onversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision co nversion, it will be served only after this conversion is completed. Features • 8 channels with multiplexed inputs

• 10-bit cascaded potentiometric ADC
• Conversion time 16 micro-seconds (typ.)
• Zero Error (offset) ± 2 LSB max
• Positive External Reference Voltage Range (VAREF) 2.4 to 3.0 Volt (typ.)
• ADCIN Range 0 to 3Volt
• Integral non-linearity typical 1 LSB, max. 2 LSB
• Differential non-linearity typical 0.5 LSB, max. 1 LSB
• Conversion Complete Flag or Conversion Complete In terrupt
• Selectable ADC Clock ADC Port 1 I/O Functions Port 1 pins are general I/O that are shared with th e ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as ge neral-purpose I/O or as the alter- nate function that is available. A conversion launched on a channel which are not se lected on ADCF register will not have any effect. VAREF VAREF should be connected to a low impedance point and must remain in the range specified in Table 122. If the ADC is not used, it is recommended to connect VAREF to VAGND.

130 A/T89C51CC01

Figure 59. ADC Description depicts the waveforms in idealized form and do not provide precise timing information. of the T89C51CC01 datasheet. Figure 60. Timing Diagram Notes: 1. Tsetup min, see the AC Parameter for A/D co nversion.

1. Tconv = 11 clock ADC = 1sample and hold + 10 bit conversion

The user must ensure that Tsetup time between setting ADEN and the start of the first conversion.

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. high. In this case one should wait Tsetup only before the first conversion. Table 107. Selected Analog input 3FFh if greater than VAREF and 000h if less than VAGND. Clock Selection The ADC clock is the same as CPU. caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.

132 A/T89C51CC01

Figure 61. A/D Converter clock in ADCON register. In this mode its power dissipation is reduced. EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 62. ADC Interrupt Structure

1. Start a standard conversion
2. Start a precision conversion (need interrupt ADC)

4129N–CAN–03/08 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt: EA = 1

134 A/T89C51CC01

Table 109. ADCON Register Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port.

6 PSIDLE

Clear to convert without idle mode.

5 ADEN

Clear for Standby mode (power dissipation 1 uW).

4 ADEOC

Must be cleared by software.

3 ADSST

Set to start an A/D conversion.

Table 110. ADCLK Register Table 111. ADDH Register Table 112. ADDL Register The value read from these bits are indeterminate. D o not set these bits. The value read from these bits are indeterminate. D o not set these bits.

136 A/T89C51CC01

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 63. Interrupt Control System

which must be cleared to disable all the interrupts at the same time. bit values and priority levels associated with each combination. Table 113. Priority Level Bit Values determined by the polling sequence, see Table 114. Table 114. Interrupt Priority Within level

138 A/T89C51CC01

4129N–CAN–03/08 Registers Table 115. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register Reset Value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enab led or disabled by setting or clearing its interrupt enable bit. 6 EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt.

5 ET2

Timer 2 Overflow Interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. 4 ES Serial Port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt.

3 ET1

Timer 1 Overflow Interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.

2 EX1

External Interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1.

1 ET0

Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.

0 EX0

External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.

Table 116. IEN1 Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.

2 ETIM

Clear to disable the timer overrun interrupt. Set to enable the timer overrun interrupt.

1 EADC

Clear to disable the ADC interrupt. Set to enable the ADC interrupt.

0 ECAN

Clear to disable the CAN interrupt. Set to enable the CAN interrupt.

140 A/T89C51CC01

Table 117. IPL0 Register The value read from this bit is indeterminate. Do n ot set this bit.

6 PPC PCA Interrupt Priority bit

5 PT2 Timer 2 Overflow Interrupt Priority bit

Refer to PT2H for priority level.

4 PS Serial Port Priority bit

Refer to PSH for priority level.

3 PT1 Timer 1 Overflow Interrupt Priority bit

Refer to PT1H for priority level.

2 PX1 External Interrupt 1 Priority bit

Refer to PX1H for priority level.

1 PT0 Timer 0 Overflow Interrupt Priority bit

Refer to PT0H for priority level.

0 PX0 External Interrupt 0 Priority bit

Refer to PX0H for priority level.

Table 118. IPL1 Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.

2 POVRL Timer Overrun Interrupt Priority Level Less Signifi cant Bit

Refer to PI2CH for priority level.

1 PADCL ADC Interrupt Priority Level Less Significant Bit

Refer to PSPIH for priority level.

0 PCANL CAN Interrupt Priority Level Less Significant Bit

Refer to PKBH for priority level.

142 A/T89C51CC01

Table 119. IPH0 Register The value read from this bit is indeterminate. Do n ot set this bit.

6 PPCH

5 PT2H

4 PSH

3 PT1H

2 PX1H

1 PT0H

0 PX0H

Table 120. IPH1 Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.

2 POVRH

1 PADCH

0 PCANH

144 A/T89C51CC01

4129N–CAN–03/08

Electrical Characteristics

DC Parameters for Standard Voltage TA = -40 °C to +85 °C; V SS = 0V; V CC = 3V to 5.5V; F = 0 to 40 MHz Ambiant Temperature Under Bias: °C to 85 °C Table 121. DC Parameters in Standard Voltage maximum rating conditions may affect device reliability.

if a crystal oscillator used (see Figure 64.).

1. Idle I CC is measured with all output pins disconnected; XTA L1 driven with T CLCH ,
2. Power-down I CC is measured with all output pins disconnected; EA = V CC , PORT 0 =

and the POF flag must be set.

1. Capacitance loading on Ports 0 and 2 may cause sp urious noise pulses to be super-

Trigger use is not necessary.

1. Typicals are based on a limited number of samples and are not guaranteed. The val-

ues listed are at room temperature.

1. Under steady state (non-transient) conditions, I OL must be externally limited as fol-

not guaranteed to sink current greater than the listed test conditions.

1. ICC_FLASH_WRITE operating current while a Flash b lock write is on going.
2. Flash Retention is guaranteed with the same formu la for V CC Min down to 0.

Figure 64. ICC Test Condition, Active Mode All other pins are disconnected.

146 A/T89C51CC01

Figure 65. ICC Test Condition, Idle Mode Figure 66. ICC Test Condition, Power-Down Mode Figure 67. Clock Signal Waveform for I CC Tests in Active and Idle Modes All other pins are disconnected. All other pins are disconnected.

Notes: 1. Typicals are based on a limited number of s amples and are not guaranteed. AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. Table 123, Table 126 and Table 129 give the description of each AC symbols. Table 124, Table 128 and Table 130 give for each range the AC parameter. value and use this value in the formula. LLIV and 20 MHz, Standard clock. Table 122. DC Parameters for AD Converter in Precision Conversion

148 A/T89C51CC01

Table 123. Symbol Description Table 124. AC Parameters for a Fix Clock (F = 40 MHz)

Table 125. AC Parameters for a Variable Clock

12 T CLCL

150 A/T89C51CC01

Table 126. Symbol Description Table 127. AC Parameters for a Variable Clock (F=40MHz)

Table 128. AC Parameters for a Variable Clock

152 A/T89C51CC01

Table 129. Symbol Description (F = 40 MHz)

Table 130. AC Parameters for a Fix Clock (F = 40 MHz) Table 131. AC Parameters for a Variable Clock Table 132. AC Parameters

154 A/T89C51CC01

4129N–CAN–03/08 External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at V CC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at V IH min for a logic “1” and V IL max for a logic “0”. Float Waveforms For timing purposes as port pin is no longer floati ng when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V OH /V OL level occurs. I OL /I OH ≥ ± 20 mA. VCC -0.5V 0.45V 0.7V CC 0.2V CC -0.1 TCHCL TCLCX TCLCL TCLCH TCHCX INPUT/OUTPUT 0.2 V CC + 0.9 0.2 V CC - 0.1 VCC -0.5V 0.45V FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V

4129N–CAN–03/08 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. This diagram indicates when signals are clocked int ernally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and componen t. Typically though (T A=25 °C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals ar e typically 85 ns. Propagation delays are incorpora ted in the AC specifications. DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 FLOAT FLOAT FLOAT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION INDICATES ADDRESS TRANSITIONS EXTERNAL PROGRAM MEMORY FETCH FLOAT DATA SAMPLED DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED RXD SAMPLED INTERNAL CLOCK XTAL2 ALE PSEN P2 (EXT) READ CYCLE WRITE CYCLE RD WR PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) DATA OUT DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED

156 A/T89C51CC01

Table 134. Memory AC Timing Figure 68. Flash Memory – ISP Waveforms Figure 69. Flash Memory – Internal Busy Waveforms

4129N–CAN–03/08

Ordering Information

• Factory default programming for T89C51CC01CA-xxxx is bootloader CAN and HSB=BBh – . X1 mode – . BLJB = 0; jump to Bootloader – . LB2 = 0 Security Level 4
• Factory default programming for T89C51CC01UA-xxxx is bootloader UART and HSB=BBh – . X1 mode – . BLJB = 0; jump to Bootloader – . LB2 = 0 Security Level 4 Note: Customer can change these modes by re-programm ing with a parallel programmer, this can be done by an Atmel distributor.

Table 136. Possible Order Entries

158 A/T89C51CC01

4129N–CAN–03/08 Package Drawings VQFP44

4129N–CAN–03/08 STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

160 A/T89C51CC01

4129N–CAN–03/08 PLCC44

4129N–CAN–03/08 STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.

162 A/T89C51CC01

4129N–CAN–03/08 Datasheet Change Log for T89C51CC01 Changes from 4129F - 11/02 to 4129G - 04/03 1. Changed the endurance of Flash to 100, 000 Write/ Erase cycles. 2. Added note on Flash retention formula for V IH1 , in Section "DC Parameters for Standard Voltage", page 144. Changes from 4129G - 04/03 to 4129H - 10/03 1. Updated “Electrical Characteristics” on page 144. 2. Corrected Figure 46 on page 84. Changes from 4129H - 10/03 to 4129I - 12/03 1. Correction in Registers CPA and CPS0. 2. Added note regarding PSEN during power On see Sec tion “Hardware Boot Pro- cess”, page 48. Changes from 4129I - 12/03 to 4129J - 08/04 1. Figure clock-out mode modified see, Figure 37 on page 67. 2. Added explanation on the CAN protocol, see Sectio n “CAN Controller”, page 75. 3. Corrected error in Table 53 on page 72, (1.25ms t o 1.25s) for Time-out Computation. Changes from 4129J - 08/04 to 4129K 01/05 1. Minor corrections throughout the document. 2. Clarification to Mode Switching Waveforms diagram . See page 16. Changes from 4129K 01/05 to 4129L 08/05 1. Added green product ordering information. Changes from 4129L 08/05 to 4129M 02/08 1. Removed non-green packages from ordering informat ion. Changes from 4129M 02/08 to 4129N 03/08 1. Removed CA-BGA package offering from ordering inf ormation. 2. Updated package drawings.

i Table of Contents

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