AT89C5122D-ALRUM

AT83C5122_08 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 208

Technical content

Features

• Clock Controller – 80C51 core with 6 clocks per instruction – 8 MHz On-Chip Oscillator – PLL for generating clock to supply CPU core, USB and Smart Card Interfaces – Programmable CPU clock from 500 KHz / X1 to 48 MHz / X1
• Reset Controller – Power On Reset (POR) feature avoiding an external reset capacitor – Power Fail Detector (PFD) –W a t c h - D o g T i m e r
• Power Management – Two power saving modes : Idle and Power Down – Four Power Down Wake-up Sources : Smart Card Detection, Keyboard Interrupt, USB Resume, External Interrupt – Input Voltage Range : 3.0V - 5.5V – Core’s Power Consumption (Without Smart Card and USB) :
• 30 mA Maximum Operating Current @ 48 MHz / X1
• 200 μA Maximum Power-down Current @ 5.5V
• Interrupt Controller – up to 9 interrupt sources – up to 4 Level Priority
• Memory Controller – Internal Program memory :
• up to 32KB of Flash or CRAM or ROM for AT8xC5122 or ROM for AT83R5122
• up to 30KB of ROM for AT83C5123 – Internal Data Memory : 768 bytes including 256 bytes of data and 512 bytes of XRAM – Optional : internal data E2PROM 512 bytes
• Two 16-bit Timer/Counters
• USB 2.0 Full Speed Interface –4 8 M H z D P L L – On-Chip 3.3V USB voltage regulator and transceivers – Software detach feature – 7 endpoints programmable with In or out directions and ISO, Bulk or Interrupt Transfers :
• Endpoint 0: 32 Bytes Bidirectionnal FIFO for Control transfers
• Endpoints 1,2,3: 8 bytes FIFO
• Endpoints 4,5: 64 Bytes FIFO
• Endpoint 6: 2*64 bytes FIFO with Pin-Pong feature
• ISO 7816 UART Interface Fully Compliant with EMV, GIE-CB and WHQL Standards – Programmable ISO clock from 1 MHz to 4.8 MHz – Card insertion/removal detection with automatic deactivation sequence – Programmable Baud Rate Generator from 372 to 11.625 clock pulses – Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention – Automatic character repetition on parity errors – 32 Bit Waiting Time Counter – 16 Bit Guard Time Counter – Internal Step Up/Down Converter with Programmable Voltage Output:
• VCC = 4.0V to 5.5V, 1.8V-30 mA, 3V-60 mA and 5V-60 mA
• VCC = 3.0V, 1.8V-30 mA, 3V-30 mA and 5V-30 mA – Current overload protection – 6 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Card Interface
• Alternate Smart Card Interface with CLK, IO and RST
• UART Interface with Integrated Baud Rate Generator (BRG)
• Keyboard interface with up to 20x8 matrix management capability
• Master/Slave SPI Interface
• Four 8 bit Ports, one 6 bit port, one 3-bit port – Up to Seven LED outputs with 3 level programmable current source : 2, 4 and 10 mA – Two General Purpose I/O programmable as external interrupts – Up to 8 input lines programmable as interrupts – Up to 30 output lines C51 Microcontroller with USB and Smart Card Reader Interfaces AT83C5122 AT83R5122 AT85C5122 AT89C5122 AT89C5122DS AT83C5123

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Reference Documents The user must get the following additionnal documents which are not included but which complete this product datasheet

• Product Errata Sheet
• Bootloader Datasheet

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Product Description AT8xC5122/23 products are high-performanc e CMOS derivatives of the 80C51 8-bit microcontrollers designed for USB smart card reader applications. The AT8xC5122 is proposed in four versions : - ROM version referenced AT83R5122 is only factory programmable. - CRAM version without internal data E2PROM. The CRAM device implements a vola- tile program memory which is programmed by means of an embedded ROMed bootloader which transfers the code from a remote software programming tool called FLIP through UART or USB interfaces. - Flash version without internal data E2PROM. At power-up, the program located in the flash memory is transferred into the CRAM then executed. The AT83C5123 is a low pin count of the AT8xC5122 and is proposed in ROM version with or without internal data E2PROM. The ROM device is only factory programmable. The AT8xC5122DS is a secure version of the AT8xC5122 on which the external pro- gram memory access mode is disabled. Table 1. Product versions AT83R5122 AT85C5122 AT89C5122 AT89C5122DS AT83C5123 Packages VQFP64 QFN64 Die Form PLCC68 VQFP64 Die Form VQFP64 QFN64 VQFP64 QFN64 VQFP32 QFN32 Die Form Program memory 32KB ROM 32KB CRAM 32KB E2PROM 32KB E2PROM 30KB ROM Internal Data E2PROM No No No No No Embedded bootloader No Yes Yes Yes No VQFP32, QFN32 packages Features not available : - Keyboard Interface - Master/Slave SPI Interface - External Program Memory Access Reduced features : - Only 12 I/O with up to 4 LED Outputs with Programmable Current PLCC68, VQFP64,QFN64 packages All features are available All features are available except External Program Memory Access

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT8xC5122/AT83R5122 Block Diagram AT83C5123 Block Diagram DC/DC Converter LI CVCC CVSS UART Interface TxD RxD 16-BIT TIMERS T[0-1] Interrupt Controller INT[0-1] Alternate Card CRST1 CCLK1 CIO1 3.3 V Regulator VCC VSS WATCH-DOG POR PFD RESET RST PLLPLLF XTAL1 XTAL2

8 MHz

INTERNAL ADDRESS AND DATA BUS 32K x 8 ROM (1) 32K x 8 E2PROM (1) 32K x 8 CRAM (1) External Memory Controller EA PSEN ALE A[8-15] AD[0-7] WR RD VREF USB Interface ISO 7816 Interface CCLK CRST CPRES CC8 CC4 CIO 3.3V Regulator AVSS AVCC DVCC Note 1 : the implementation of these f eatures depends on product v ersions 512 x 8 E2PROM (1) Parallel I/O Ports P0[0-7] 8-BIT PORT 8-BIT PORT P2[0-7] 8-BIT PORT P3[0-7] 6-BIT PORT P4[0-5] 8-BIT PORT P5[0-7] LED's LED[0-6] 3-BIT PORT P1[2,6-7] SPI InterfaceMISO MOSI SCK SS KBD Interface KB[0-7] DC/DC Conv erter LI CVCC CVSS UART Interface TxD RxD 16-BIT TIMERS T[0-1] Interrupt Controller INT[0-1] Alternate Card CRST1 CCLK1 CIO1 3.3 V Regulator VCC VSS WATCH-DOG POR PFD RESET RST PLLPLLF XTAL1 XTAL2 INTERNAL ADDRESS AND DATA BUS 30K x 8 ROM 512 x 8 E2PROM (1) Parallel I/O Ports 8-BIT PORT P3[0-7] VREF USB Interface ISO 7816 Interface CCLK CRST CPRES CC8 CC4 CIO 3.3V Regulator AVSS AVCC DVCC Note 1 : the implementation of these f eatures depends on product v ersions 1-BIT PORT P5.0 LED's LED[0-3] 3-BIT PORT P1[2,6-7]

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Pinout High Pin Count Package

Description

Figure 1. VQFP64 Package Pinout

Figure 2. PLCC68 Package Pinout (for engineering purpose only)

Figure 3. QFN64 Package Pinout

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT89C5122DS version Figure 4. VQFP64 Package Pinout 62 61 60 59 58 63 57 56 55 54 53 P0.1/AD1 P0.3/AD3 P0.5/AD5 P0.7/AD7 P4.1/MOSI P4.0/MISO P4.2/SCK P4.5/LED6 P3.1/TxD P4.3/LED4 P4.4/LED5 P3.6/WR/LED2 XTAL1 XTAL2 P2.5/A13 P2.4/A12 P2.2/A10 P2.1/A9 P2.0/A8 CRST CCLK LI P2.3/A11 VQFP64 64 52 13 36 VCC VSS P5.0/KB0 P3.7/RD/LED3 51 50 AVSS AVCC P3.3/INT1 P3.4/T0/LED1 P3.5/T1/CRST1 CVCC CVSS 31 32 P0.0/AD0 P1.2/CPRES P0.2/AD2 P0.4/AD4 P0.6/AD6 P1.6/SS P2.7/A15 P2.6/A14 P1.7/CCLK1 P5.1/KB1 P5.2/KB2 P5.3/KB3 P5.4/KB4 P5.5/KB5 P5.6/KB6 P5.7/KB7 P3.2/INT0/LED0/CIO1 CC4 PLLF ALE PSEN DVCC CC8 CIO P3.0/RxD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VREF VCC RST

Figure 5. QFN64 Package Pinout

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Low Pin Count Package AT83C5123 version Figure 6. VQFP32 Package Pinout Figure 7. QFN32 Package Pinout

Table 2. Pin Description with too weak internal pull-ups.

Table 2. Pin Description (Continued)

lower than VIL is applied, whether or not the oscillator is running. to be reset by connecting a capacitor between this pin and VSS. returns the chip to normal operation. voltage is controlled by software. this pin. If an external oscillator is used, leave XTAL2 unconnected. code from external memory locations 0000h to FFFFh. If security level 1 is programmed, EA will be latched on reset. condition is not met,the MCU may have an unpredictable behaviour.

activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. Receives the RC network of the PLL low pass filter. LI supplies the current for the charge pump of the DC/DC converter. can be configured either in regulator or in pump mode. 680nF decoupling capacitor if the USB interface is used. This output can be used by the application with a maximum of 10 mA. AVSS is used to supply the USB driver.

mented as close as possible from the microcontroller package. Table 3. External Components Bill Of Materials C4 USB pad decoupling capacitor 680 nF +/-30% All product versions. C5 Smart Card clock filter capacito r 27 pF +/-10% All product versions. application capacitance allowed by the USB standard is 10 μF. If DC/DC converter is not used at 5V, this inductance is optional.

8.0000 Mhz +/- 2500 ppm

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 USB Keyboard with Smart Card Reader Using AT83R5122, AT8xC5122/AT89C5122DS LEDx VCC KB1 KB2 KB3 KB4 KB5 KB6 KB7 R19 R18 R17 R16 R15 P3[0-1,3-4] P2[0-7] R14 R13 R12 R11 R10 R09 R08 P0[0-7] R07 R06 R05 R04 R03 R02 R01 R00 Keyboard Matrix KB0C0 GND EA/VCC (1) GND GND C8C9 VCC VCC VCC AVCC XTAL2XTAL1 VCC GND VREF VCC VBUS GND USB AVSS GND PLLF VSS GND GND DVCC 10mA Max GND CCLK1 CRST1 CIO1 RST CLK I/O VCCC1 GNDC5 Alternate Card VCC GND RST Optional CapacitorC10 Notes : 1 - Pin configuration depends on product versions LI Smart Card VCC RST CLK I/O GND S1CPRES S2 GND GND CC8 CIO CC4 CCLK CRST CVSS CVCC VCC 180Ohms 15pF

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 USB Smart Card Reader Using the AT83C5123 Version LEDx VCC GND RST Optional Capacitor GND GND GND GND C8C9 VCC VCC AVCC XTAL2XTAL1 VCC GND VREF VCC VBUS GND USB C10 CCLK1 CRST1 CIO1 RST CLK I/O VCCC1 GNDC5 Alternate Card AVSS GND PLLF VSS GND GND DVCC 10mA Max VCC LI Smart Card VCC RST CLK I/O GND S1CPRES S2 GND GND CC8 CIO CC4 CCLK CRST CVSS CVCC VCC

generated through the DPTR register. If EA is strapped to VCC, the MCU fetches the code from the internal program memory. If the EA is strapped to GND, the MCU fetches the code from external program memory. memory. In this mode, the internal program memories are disabled. The hardware configuration for external program execution is shown in Figure 8. Figure 8. Executing from External Program Memory

• 512 bytes of XRAM (Extended RAM) to store program data.
• The Lower 128 bytes (addresses 00h to 7Fh) are directly and indirectly addressable.
• The Upper 128 bytes (addresses 80h to FFh) are indirectly addressable only.
• The Special Function Registers (SFRs) (addresses 80h to FFh) are directly addressable only. The Upper 128 bytes and SFR’s have the same address space but are physically separated. When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is in the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timi ngs. If M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals. XRAM Achitecture Depending on the state of EXTRAM bit in AUXR register (See Table 5 on page 22), the MCU fetches data from internal or external XRAM. If EXTRAM=0 (reset condition), the MCU fetches the data from internal XRAM. The size of internal XRAM is configured by the bit XRS0 in AUXR register (See Table 5 on page 22). The XRAM logically occupies the first bytes of external data memory. The bit XRS0 can be used to hide a part of the available XRAM . This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. The XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. For example, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory.

Table 4. XRAM Size Configuration

and RD as respectively write and read signals. Accesses above XRAM size can only be done by the use of DPTR. to 64 KBytes of external XRAM Memory. Figure 9. Accessing to External XRAM Memory Note that external XRAM Memory access is only available on High Pin Count Packages. the gate as the read strobe to the external program/data memory. code to switch between them (Figure 10).

Figure 10. Use of Dual Pointer a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

0008 LOOP:

only the fact that DPS is toggled in the proper sequence matters, not its actual value. For example, the block move routine works the same whether DPS is '0' or '1' on entry.

Table 5. Auxiliary Register - AUXR (8Eh) The value read from this bit is indeterminate. Do not change these bits. Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR. Set to access external memory. (HSB), default setting , XRAM selected. Set , ALE is active only when a MOVX or MOVC instruction is used.

Table 6. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122 Table 7. Auxiliary Register 1 AUXR1- (0A2h) for AT83C5123 The value read from this bit is indeterminate. Do not change these bits. The value read from this bit is indeterminate. Do not change this bit. 3 GF3 This bit is a gener al-purpose user flag. The value read from this bit is indeterminate. Do not change this bit. Cleared to select DPTR0. Set to select DPTR1. The value read from this bit is indeterminate. Do not change these bits.

5 Reserved

The value read from this bit is indeterminate. Do not change these bits. The value read from this bit is indeterminate. Do not change this bit. 3 GF3 This bit is a gener al-purpose user flag. The value read from this bit is indeterminate. Do not change this bit.

datasheet for further details. the P3.7 Port is no more used. Table 8. CRAM Configuration Register - RCON (D1h) The value read from this bit is indeterminate. Do not change these bits. Clear to map the XRAM memory during MOVX. This bit has priority over the EXTRAM bit. The value read from this bit is indeterminate. Do not change these bits.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 When pin EA =1 and after the reset, the MCU begins the execution of the embedded bootloader from location F800h of the ROM. The bootloader implements an In-System Programming (ISP) mode which manages the transfer of the code in the volatile Pro- gram Memory (CRAM). For CRAM version, the code is supplied by the ATMEL’s FLexible In-system Program- ming software (FLIP) through USB or UART interface For E2PROM version, the code is supplied from the internal code E2PROM or by FLIP. The state of pin P3.7 at reset determines the code source. If P3.7=1 (reset condition) the source is the internal E2PROM and the transfer takes about 1.5 seconds. If P3.7=0 the source is FLIP and the transfer time depends mainly on external conditions not related to bootloader. Once the code is running in CRAM, the roll-over condition (code fetched beyond address 7FFFh) depends on the state of ENBOOT bit of AUXR1 register (Table 6 on page 23). If ENBOOT=1 (reset condition) the MCU fetches the code from bootloader ROM. If ENBOOT=0, the MCU fetches the code from the external Program Memory. In this last case, PSEN is activated and Ports P0 and P2 are used to emit data and address signals. Warning : external Program Memory access is not allowed on Low Pin Count Packages. 7FFFh 0000h 7EFFh 7F00h Reserved User code Bootloader FFFFh P3.7 AT8xC5122 Microcontroller

code executing in ROM while the CRAM is written. Figure 11. Read / Write Mechanisms in CRAM Memory

Figure 12. AT8xC5122’s CRAM and E2PROM Versions

128 Bytes

512 Bytes

ROM device is only factory programmable. this option, the size of ROM is reduced to 30K. Access to external Program Memory is not allowed. figured at factory and must be requested by the customer at order time. Table 9. Security Levels Description

1 No protection lock enabled

EA is sampled and latched on reset. External code execution is enabled.

Figure 13. AT83R5122, AT8xC5122’s ROM Version

AT83C5123 Version The AT83C5123 device is a low pin count version of the AT8xC5122. ROM device is only factory programmable. Figure 14. AT83C5123’s Device

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Special Function Registers (SFR’s) Introduction The Special Function Registers (SFRs) of the AT8xC5122/23 can be ranked into the fol- lowing categories:

• C51 Core Registers: ACC, B, DPH, DPL, PSW, SP
• System Configuration Registers: PC ON, CKRL, CKCON0, CKCON1, CKSEL, PLLCON, PLLDIV, AUXR, AUXR1, RCON
• I/O Port Registers: P0, P1, P2, P3, P4, P5, PMOD1, PMOD2
• Timer Registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Watchdog (WD) Registers: WDTRST, WDTPRG
• Serial I/O Port Registers: SADDR, SADEN, SBUF, SCON
• Baud Rate Generator (BRG) Registers: BRL, BDRCON
• System Interrupt Registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Smart Card Interface (SCI) Registers: SCSR, SCCON/SCETU0, SCISR/SCETU1, SCIER/SCIIR, SCIBUF, SCGT0/SCWT0, SCGT1/SCWT1, SCICR/SCWT2, SCICLK
• DC/DC Converter Registers: DCCKPS
• Keyboard Interface Registers: KBE, KBF, KBLS
• Serial Port Interface (SPI) Registers: SPCON, SPSTA, SPDAT
• Universal Serial Bus (USB) Registers:USBCON, USBADDR, USBINT, USBIEN, UEPNUM, UEPCONX, UEPSTAX, UEPRST, UEPINT, UEPIEN, UEPDATX, UBYCTX, UFNUML, UFNUMH
• LED Controller Registers: LEDCON0, LEDCON1

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT8xC5122 Version Notes: 1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in. Bit addressable Not bit addressable F8h UEPINT 0000 0000 F0h B 0000 0000 LEDCON0 0000 0000 E8h P5 1111 1111 E0h ACC 0000 0000 LEDCON1 XX00 0000 UBYCTX 0000 0000 D8h D0h PSW 0000 0000 RCON XXXX 0XXX UEPCONX 1000 0000 UEPRST 0000 0000 C8h UEPSTAX 0000 0000 UEPDATX 0000 0000 S C R S C0h P4 1111 1111 SCICLK (1) 0X10 1111 UEPIEN 0000 0000 SPCON 0001 0100 SPSTA 0000 0000 SPDAT 1111 1111 USBADDR 1000 0000 UEPNUM 0000 0000

0 SCWT3 (1)

S C R S B0h P3 1111 1111 IEN1 XXXX X000 IPL1 00XX 00X0 IPH1 00XX 00X0 SCGT0 (1) 0000 1100 SCGT1(1) XXXX XXX0 SCICR (1) 0000 0000 IPH0 X000 0000

0 SCWT0(1)

SCWT1 (1) 0010 0101 SCWT2 (1) 0000 0000 S C R S A8h IEN0 0000 0000 SADDR 0000 0000 SCIBUF XXXX XXXX SCSR X000 1000 SCETU0 (1) 0111 0100 SCETU1 (1) XXXX X001 SCIER (1) 0X00 0000

0 SCCON (1)

SCISR (1) 10X0 0000 SCIIR (1) 0X00 0000 A0h P2 1111 1111 ISEL 0000 0100 AUXR1 XX1X 0XX0 PLLCON XXXX X000 PLLDIV 0000 0000 WDTRST XXXX XXXX WDTPRG XXXX X000 98h SCON 0000 0000 SBUF XXXX XXXX BRL 0000 0000 BDRCON XXX0 0000 KBLS 0000 0000 KBE 0000 0000 KBF 0000 0000 90h P1 1111 1111 PMOD0(2) 0000 0000 CKRL XXXX 1111 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 TH0 0000 0000 TH1 0000 0000 AUXR 0XXX X000 CKCON0 X0X0 X000 80h P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 PMOD1 0000 0000 CKSEL XXXX XXX0 PCON 00X1 0000

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83C5123 Version Notes: 1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in. Bit addressable Not bit addressable F8h UEPINT 0000 0000 F0h B 0000 0000 LEDCON0 0000 0000 E8h P5 XXXX XXX1 E0h ACC 0000 0000 UBYCTX 0000 0000 D8h D0h PSW 0000 0000 UEPCONX 1000 0000 UEPRST 0000 0000 C8h UEPSTAX 0000 0000 UEPDATX 0000 0000 S C R S C0h P4 11XX XXXX SCICLK (1) 0X10 1111 UEPIEN 0000 0000 USBADDR 1000 0000 UEPNUM 0000 0000 S C R S B0h P3 1111 1111 IEN1 X0XX 0XXX IPL1 X0XX 0XXX IPH1 X0XX 0XXX SCGT0 (1) 0000 1100 SCGT1(1) XXXX XXX0 SCICR (1) 0000 0000 IPH0 X000 0000 SCWT1 (1) 0010 0101 SCWT2 (1) 0000 0000 S C R S A8h IEN0 0000 0000 SADDR 0000 0000 SCIBUF XXXX XXXX SCSR X000 1000 SCETU0 (1) 0111 0100 SCETU1 (1) XXXX X001 SCIER (1) 0X00 0000 CKCON1 XXXX XXX0 SCISR (1) 10X0 0000 SCIIR (1) 0X00 0000 A0h ISEL 0000 0100 AUXR1 XXXX 0XX0 PLLCON XXXX X000 PLLDIV 0000 0000 WDTRST XXXX XXXX WDTPRG XXXX X000 98h SCON 0000 0000 SBUF XXXX XXXX BRL 0000 0000 BDRCON XXX0 0000 90h P1 1111 1111 PMOD0 00XX 0XXX CKRL XXXX 1111 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 TH0 0000 0000 TH1 0000 0000 AUXR 0XXX X000 CKCON0 X0X0 X000 80h SP 0000 0111 DPL 0000 0000 DPH 0000 0000 PMOD1 XXXX 00XX CKSEL XXXX XXX0 PCON 00X1 0000

Table 10. C51 Core SFRs Table 11. Clock SFRs Table 12. I/O Port SFRs

Table 13. Timers SFRs Table 14. Watchdog SFRs Table 15. Serial I/O Ports SFRs Table 16. Baud Rate Generator SFRs Table 17. Interrupt SFRs

Table 18. SCIB SFRs

Table 19. DC/DC SFRs Table 20. Keyboard SFRs Table 21. SPI SFRs Table 22. USB SFRs

Table 23. LED SFRs

Figure 18. PLL Programming Flow

• a clock for the CPU core
• a clock for the peripherals which is used to generate the timers, watchdog, SPI, UART, and ports sampling clocks. This divided clock will be used to generate the alternate card clock.
• a clock for the USB
• a clock for the SCIB controller
• a clock for the DC/DC converter These clocks are enabled or not depending on the power reduction mode as detailed in Section “Power Management”, page 178. These clocks are generated using four presacalers defined in the table below: PLL Programming Configure Dividers N3:0= xxxxb R3:0= xxxxb Enable PLL PLLEN= 1 PLL Locked? PLOCK= 1? Prescaler Register Reload Factor Function PR1 CKRL CKRL[0:3] CPU & Peripheral clocks PR2 SCICLK SCICLK[0:5] Smart card PR3 SCSR ALTKPS[0:1] Alternate card PR4 DCCKPS DCCKPS[3:0] DC/DC

Figure 19. Clock Tree Diagram – a derivative of the PLL clock.

96 MHz

The CPU and peripherals clocks frequencies are defined in the table below. the hardware and the user does not need to take care of. bypassed in X2 mode (X2 bit set in CKCON0 register). Table 1. X1 and X2 Mode Selection

Figure 20. X1 mode Figure 21. X2 mode or at 1 MHz in X2 mode. So we can say that the CPU works at 2 MHz / X1 or 1MHz / X2.

8 MHz 1/2

4 MHz

4 MHz1/2

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Use of PLL Clock When the CPU clock is fed by the PLL, the X2 mode is forbidden. The bit X2 must always remain cleared in CKCON0 register. As the PR1 prescaler is always different from 1/2, the usual X1 mode can not be defined. So it is necessary to define an equiva- lent X1 or X2 mode from equivalent clock circuits, as in previous section. Example: PR1=1/4, PLL feeds the CPU. The CPU works in this case at 24 MHz. This frequency could also be obtained by an equivalent clock circuit where the on-chip oscil- lator would run at 48 MHz in X1 mode or at 24 Mhz in X2 mode. So we can say that in this configuration, the CPU works at 48 MHz / X1 or 24 MHz / X2 (See figures below). As the X2 bit is cleared in CKCON0 register, we have always F CK_IDLE = FCK_PERIPH.

1 MHz1/8

(Equivalent to)

2 MHz 1/2

External Clock X1 mode selected PERIPH frequency

1 MHz

(Equivalent to)

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 SCIB Clock The Smart Card Interface Block (SCIB) uses two clocks : – The first one, CK_IDLE, is the peripheral clock used for the interface with the microcontroller. – The second one, CK_ISO, is independant from the CPU clock and is generated from the PLL or XTAL1 output. PR2, a 6-bit prescaler, will be used to generate: SCIB clock frequency must be lower than CPU clock frequency. During SCIB Reset, the CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816. The SCIB clocks frequency is defi ned in Figure 41 on page 72 and Table 42 on page 72. Two conditions must be met for a correct use of the SCIB:

• CK_CPU > 4/3 * CK_ISO and

24 MHz

48 MHz 1/2

External Clock CPU frequency (Equivalent to) X1 mode selected (Equivalent to) X2 mode selected PERIPH frequency

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work. If the CK_CPU >= 6* CK_ISO, the programmer must take care of three cases:

• Read (or write) operation on a SCIB register followed immediatly with an other Read (or write) operation on the same register.
• Read (or write) operation on a SCIB register followed immediatly with an other Read (or write) operation on a linked register. The list of linked registers is in the table below.
• Write operation on a register of the list below followed immediatly with a read operation on a SCIB register. To avoid any trouble, a delay must be added between the two accesses on the SCIB register. The SCIB must complete the first read (or write) operation before to receive the second. A solution is to add NOP (no operation) instructions. The number of NOP to add depends of the rate between CK_CPU and CK_ISO (see table below). Alternate Card Clock The alternate Card uses the peripheral clock divided by the PR3 prescaler. (1; 1/2; 1/4; 1/8 division ratio). See Section "Alternate Card", page 76 for the definition of the alter- nate clock. DC/DC Converter Clock The DC/DC block needs a clock with a 50 % duty cycle. The frequency must also be included in the range 3.68 MHz and 6 MHz. The PR4 prescaler is used to configure the DC/DC frequency. Linked registers Write in SCICR and after read of SCETU0-1 Write in SCIBUF and after read of SCISR Wait after Write operation on this registers SCICR, SCIER, SCETU0-1,SCGT0-1, SCWT0-3,SCCON Min CLK_CPU Max CLK_CPU Number of CPU cycles to add CLK_CPU >= 6 * CLK_ISO CLK_CPU <= 12 * CLK_ISO 6 ( example1 NOP) CLK_CPU >= 12* CLK_ISO CLK_CPU <= 16 * CLK_ISO 12 ( example 2 NOP) XTAL1 (MHz) DCCKPS3:0 value Prescaler Factor DC/DC converter CLK (MHz) 802 4

Table 24. Clock Selection Register - CKSEL (S:85h) The value read from this bit is indeterminate. Do not set this bit. Set this bit to connect CPU and Peripherals to PLL output. Clear this to to connect CPU and Peripherals to XTAL1 clock input. Table 25. Clock Reload Register - CKRL (S:97h) The value read from this bit is indeterminate. Do not set this bit.

Table 26. Clock Configuration Register 0 - CKCON0 (S:8Fh) The value read from this bit is indeterminate. Do not set this bit. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. The value read from this bit is indeterminate. Do not set this bit. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. The value read from this bit is indeterminate. Do not set this bit. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. Cleared to select the PRT output for CPU and all the peripherals .

Table 27. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122 The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. Table 28. PLL Control Register - PLLCON (S:A3h) The value read from these bits is always 0. Do not set this bits. Set this bit to select XTAL1 as USB clock. Clear this bit to select PLL as USB clock. SCIB clock is controlled by EXT48 bit and XTSCS bit. Table 29. PLL Divider Register - PLLDIV (S:A4h)

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 I/O Port Definition Ports vs Packages Table 30. I/O Number vs Packages Port 0 Port 0 has the following functions: – Default function: Port 0 is an 8-bit I/O port. – Alternate function: Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application, it uses strong internal pull-ups when emitting 1’s and it can drive CMOS inputs without external pull-ups. Port 0 has the following configurations: – Default configuration: open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state they can be used as high- impedance inputs. – Configuration 2: Low speed output, “KB_OUT” – Configuration 3: Push-pull output P0 P1 P2 P3 P4 P5 Total VQFP64 QFN64 88886 8 4 6 VQFP32 QFN32 -8-8- 1 1 7 PLCC28 - 6 - 6 - 1 13

ports can be activated only with the SCIB function. – Alternate function and configuration: see Table 31. Table 31. Port 1 Description. – Default function: Port 2 is an 8-bit I/O port.

– Default function: Port 3 is an 8-bit I/O port. – Alternate configurations: See Table 32. Table 32. Port 3 Description

– Default function: Port 4 is an 6-bit I/O port. – Alternate configurations: See Table 33. Table 33. Port 4 Description – Default function: Port 5 is an 8-bit I/O port. – Alternate function 1: Port 5 is an 8-bit keyboard port KB0 to KB7. – Alternate configuration: see Table 34. Table 34. Port 5 Description

Standard I/O P0 The P0 port is described in Figure 22. Figure 22. Standard Input/Output Port type can be used as both an input and output without the need to reconfigure the port. an external device to pull the pin low. pull-up transistors in the quasi-bi-directional output that serve different purposes. the voltage on the port pin below its input threshold.

The “Port51” is described in Figure 23. Figure 23. Quasi Bi-directional Port source current is needed from a port output. The Push-pull port configuration is shown in Figure 24. Figure 24. Push-pull Output The input with pull-up (Input MPU and Input WPU) configuration is shown in Figure 25.

2 CPU

Figure 28. LED Source Current

1. The port must be configured as standard C51 port by means of PMOD0 and PMOD1

LEDCON1 registers before switching the led on. Table 35. LED Source Current

Table 36. Port Mode Register 0 - PMOD0 (91h) for AT8xC5122

00 Quasi bi-directional

01 Push-pull

10 Output Low Speed

11 Input with weak pull-up

11 Input with weak pull-down

The value read from this bit is indeterminate. Do not set this bit.

00 C51 Standard P0

01 Reserved

11 Push-pull

Table 37. Port Mode Register 0 - PMOD0 (91h) for AT83C5123 The value read from these bits are indeterminate. Do not set these bit. The value read from these bits are indeterminate. Do not set these bit.

Table 38. Port Mode Register 1 - PMOD1 (84h) for AT8xC5122

10 Input with weak pull-down

10 Input with medium pull-up

11 Input with medium pull-up

Table 39. Port Mode Register 1 - PMOD1 (84h) for AT83C5123 The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

Table 40. LED Port Control Register 0 - LEDCON0 (F1h)

00 LED control disabled

Table 41. LED Port Control Register 1- LEDCON1 (F1h) only for AT8xC5122 The value read from this bit is indeterminate. Do not set this bit.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Smart Card Interface Block (SCIB) The SCIB provides all signals to interface directly with a smart card. The compliance with the ISO7816, EMV’2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro- cessor card) are supported. The component supplies the different voltages requested by the smart card. The power off sequence is directly managed by the SCIB. The card presence switch of the smart card connector is used to detect card insertion or card removal. In case of ca rd removal, the SCIB de-activates the smart card using the de-activation sequence. An interrupt can be generated when a card is inserted or removed. Any malfunction is reported to the microcontroller (interrupt + control register). The different operating modes are configured by internal registers.

• Support of ISO/IEC 7816
• character mode
• one transmit/receive buffer
• 11 bits ETU counter
• 9 bits guard time counter
• 32 bits waiting time counter
• Auto character repetition on error signal detection in transmit mode
• Auto error signal generation on parity error detection in receive mode
• Power on and power off sequence generation
• Manual mode to drive directly the card I/O

Figure 29. SCIB Block Diagram dations. Please refer to the full recommendations for a complete list of terms. De-Activation Deactivation by the Terminal as a result of : unresponsive ICC, or ICC removal.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 ATR Answer To Reset. Response from the ICC to a Reset initiated by the Terminal F and D F = Clock Rate Conversion Factor, D = Bit rate adjustment factor. ETU is defined as : ETU = F/(D*f) with f = Card Clock frequency. If f is in Hertz, ETU is in second. F and D are available in the ATR (byte TA1). The default values are F=372, D=1. Guard Time The time between 2 leading edges of the start bit of 2 consecutive characters is com- prised of the character duration (10) plus the guard time. Be aware that the Guard Time counter and the Guard Time registers in the AT8xC5122/23 consider the time between 2 consecutive characters. So the equation is Guard Time Counter = Guard Time + 10. In other words, the Guard Time is the number of Stop Bits between 2 characters sent in the same direction. Extra Guard Time ISO IEC 7816-3 and EMV introduce the Extra Guard time to be added to the minimum Guard Time. Extra Guard Time only apply to consecutive characters sent by the termi- nal to the ICC. The TC1 byte in the ATR define the number N. For N=0 the character to character duration is 12 ETUs. For N=254 the character to character duration is 266. For N=255 (special case) The minimum character to character duration is to be used : 12 for T=0 protocol and 11 for T=1 protocol. Block Guard Time The time between the leading edges of 2 consecutive characters sent in opposit direc- tion. ISO IEC 7816-3 and EMV recommend a fixed Block Guard Time of 22 ETUs. Work Waiting Time (WWT) In T=0 protocol WWT is the interval between the leading edge of any character sent by the ICC, and the leading edge of the previous character sent either by the ICC or the Terminal. If no character is received by t he terminal after WWTmax time, the Terminal initiates a De-Activation Sequence. Character Waiting Time (CWT) In T=1 protocol CWT is the interval between the leading edge of 2 consecutive charac- ters sent by the ICC. If the next character is not received by the Terminal after CWTmax time, the Terminal initiates a De-Activation Sequence. Block Waiting Time (BWT) In T=1 protocol BWT is the interval between the leading edge of the start bit of the last character sent by the Terminal that gives the right to sent to the ICC, and the leading edge of the start bit of the first character sent by the ICC. If the first character from the ICC is not received by the Terminal after BWTmax time, the Terminal initiates a De-Acti- vation Sequence. Waiting Time Extention (WTX) In T=1 protocol the ICC can request a Waiting Time Extension with a S(WTX request) request. The Terminal should acknowlege it. The Waiting time between the leading edge of the start bit of the last character sent by the Terminal that gives the right to sent to the ICC, and the leading edge of the start bit of the first character sent by the ICC will be BWT*WTX ETUs. Parity error in T=0 protocol In T=0 protocol, a Terminal (respectively an ICC) detecting a parity error while receiving a character shall force the Card IO line at 0 starting at 10.5 ETUs, thus reducing the first Guard bit by half the time. T he Terminal (respectively an ICC) shall maintain a 0 for 1 ETU min and 2 ETUs max (according to ISO IEC) or to 2 ETUs (according to EMV). The ICC (respectively a Terminal) s hall monitor the Card IO to detect this error signal then attempt to repeat the character. According to EMV, following a parity error the character can be repeated one time, if parity error is detected again this procedure can be repeated 3 more times. The same character can be transmitted 5 times in total. ISO

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 IEC7816-3 says this procedure is mandatory in ATR for card supporting T=0 while EMV says this procedure is mandatory for T=0 but does not apply for ATR. Functional Description The architecture of the Smart Card Interface Block can be detailed as follows: Barrel Shifter The Barrel Shifter performs the translation between 1 bit serial data and 8 bits parallel data The barrel function is useful for character repetition since the character is still present in the shifter at the end of the character transmission. This shifter is able to shift the data in both directions and to invert the input or output value in order to manage both direct and inverse ISO7816-3 convention. Coupled with the barrel shifter is a parity checker and generator. There are 2 registers connected to this barrel shifter, one for the transmission and one for the reception. They act as buffers to relieve the CPU of timing constraints. SCART FSM (Smart Card Asynchronous Receiver Transmitter Finite State Machine) This is the core of the block. Its purpose is to control the barrel shifter. To sequence cor- rectly the barrel shifter for a reception or a transmission, it uses the signals issued by the different counters. One of the most important counters is the guard time counter that gives time slots corresponding to the character frame. The SCART FSM is enabled only in UART mode. The transition from the receipt mode to the transmit mode is done automatically. Priority is given to the transmission. Transmission re fers to Terminal transmission to the ICC. Reception refers to reception by the Terminal from the ICC. ETU Counter The ETU (Elementary Timing Unit) counter controls the working frequency of the barrel shifter, in fact it generates the enable signal of the barrel shifter. It receives the Card Clock, and generates the ETU clock. The Card Clock frequency is called “f” below. The ETU counter is 11 bit wide. A special compensation mode can be activated. It accomodates situations where the ETU is not an integer number of Card Clock (CK_ISO). The compensation mode is con- trolled by the COMP bit in SCETU1 register bit position 7. With COMP=1 the ETU of every character even bits is reduced by 1 Card Clock peri od. As a result, the average ETU is : ETU_average = (ETU - 0.5). One should bear in mind that the ETU counter should be programmed to deliver a faster ETU which will be reduced by the COMP mechanism, not the other way around. This allows to reach the required precision of the character duration specified by the ISO7816-3 standard. Example1 : F=372, D=32 => ETU= F/D = 11.625 clock cycles. We select ETU[10-0] = 12 , COMP=1. ETUaverage= 12 - (0.5*COMP) = 11.5 The result will be a full character duration (10 bit) = (10 - 0.107)*ETU. The EMV specifi- cation is (10 +/- 0.2)*ETU Guard Time Counter The minimum time between the leading edge of the start bit of 2 consecutive characters transmitted by the Terminal is controlled by the Guard Time counter, as described in Figure 32.

as a new transmission start, the Guard Time Counter is re-initialized at 1 decimal value. tion (10 ETU) plus the Guard Time as defined by the ISO and EMV recommendations. Figure 30. Guard Time. Guard Time counter is re-initialized at the start of each TERMINAL transmission. SCSR register. See Figure 32.

be used in T=1 protocol for the Character Waiting Time and for the Block Waiting Time. See the detailed explanation below. Figure 33. Waiting Time Counter bit. This mode will be detailed below in T=0 protocol and T=1 protocol. SCWT1, SCWT2 and SCWT3 registers to the WT counter. the load value. This is the case for T=1 protocol.

but the delay between signals is analog and not clock dependant. Figure 38. SCIB Deactivation Sequence after a Card Extraction Figure 39. SCIB Interrupt Sources interruption is delayed until the interrupt register is read by the microcontroller. the SCISR register must be used instead of the bits of the SCIIR register.

8 Clock Cycles

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Transmit / Receive Buffer The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into / from the Shift Register. The Shift Register is not accessible by microcontroller. Its role is to prepare the byte to be copied on the I/O pin for a transmission or in the SCIBUF buffer after a reception. During a character transmission process, as soon as the contents of the SCIBUF buffer is transferred to the shift register, the SCTBE bit is set in SCISR register to indicate that the SCIBUF buffer is empty and ready to accept a new byte. This mechanism avoids to wait for the complete transmission of the previous byte before writing a new byte in the buffer and enables to speed up the transmission. – If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the contents of the Shift Register is transferred to I/O pin, the SCTC bit is set in SCISR register to indicate that the byte has been transmitted. – If the Character repetition mode is selected (bit CREP=1 in SCICR) The TERMINAL will be able to repeat characters as requested by the ICC (See the Parity Error in T=0 protocol description in the definition paragraph above). The SCTC bit in SCISR register will be set after a successful transmission (no retry or no further retry requested by the ICC). If the number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still unsuccessful, the SCTC bit in SCISR will not be set and the SCPE bit in SCISR register will be set instead. During a character reception process, the contents of the Shift Register is transferred in the SCIBUF buffer. – If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the contents of the Shift Register is transferred to the SCIBUF the SCRC bit is set in SCISR register to indicate that the byte has been received, and the SCIBUF contains a valid character ready to be red by the microcontroller. – If the Character repetition mode is selected (bit CREP=1 in SCICR) The TERMINAL will be able to request repetition if the received character exhibit a parity error. Up to 4 retries can be requested depending on CREPSEL bit in SCSR. The SCRC bit will be set in SCISR register after a successful reception, first reception or after retry(ies). If the number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still unsuccessful, the SCRC bit and the SCPE bit in SCISR register will be set. It will be possible to read the erroneous character. Warning : the SCTBI, SCTI SCRI and SCPI bits have the same function as SCTBE, SCTC, SCRC and SCPE bits. The first ones are able to generate interruptions if the interruptions are enabled in SCIER register while the second ones are only status bits to be used in pulling mode. If the interruption mode is not used, the status bits must be used. The SCTBI, SCTI and SCRI bits do not contain valid information while their respective interrupt enable bits ESCTBI, EXCTI, ESCRI are cleared.

Figure 42. CharacterTransmission Diagram

Figure 43. Character Reception Diagram its registers. Table 43 defines the SCIB registers that are reset and their reset values. Table 43. Reset Values for SCI Registers

Alternate Card A second card named ‘Alternate Card’ can be controlled. ALTKPS1 in SCSR Register are used to set this factor. Figure 44. Alternate Card The Low significant byte register is implemented at the higher address.

Table 44. Smart Card Interface Control Register - SCICR (S:B6h, SCRS = 1)

7 RESET

Set this bit to reset and deactivate the Smart Card Interface. Clear this bit to activate the Smart Card Interface. This bit acts as an active high software reset.

6 CARDDET

Clear this bit to indicate the card presence detecto r is open when no card is inserted (CPRES is high). Set this bit to indicate the card presence detector is closed when no card is inserted (CPRES is low). Clear this bit to use the CARDIO bit (P1.0) bit to drive the Card I/O (P1.0) pin. Set this bit to use the Smart Card UART to drive the Card I/O pin (P1.0 pin). Clear this bit to stop the counter and enable the load of the Waiting Time counter hold registers. The hold registers are loaded with SCWT0, SCWT1, SCWT2 and SCWT3 values when SCWT2 is written. Set this bit to start the Waiting Time Counter. The counters stop when it reaches the timeout value.

1 CREP

character repetition in transmit mode. repetition when a parity error is indicated in transmit mode. is enabled, the SCPI bit in SCIIR register will be set too. register. If parity interrupt is enabled, the SCPI bit in SCIIR register will be set too. on the Card I/O pin represents a’0’. the Card I/O pin represents a’1’.

Table 45. Smart Card Contacts Register - SCCON (S:ACh, SCRS=0) Clear this bit to use the Card CLK bit (CARDCLK bit below) to drive Card CLK (P1.4) pin. Note: internal synchronization avoids glitches on the CLK pin when switching this bit. This bit can be changed by software but the read value is indeterminate.

5 CARDC8

Clear this bit to drive a low level on the Card C8 pin (CC8 = P1.1 pin). Set this bit to set a high level on the Card C8 pin (CC8 = P1.1 pin).. The CC8 pin can be used as a pseudo bi-directional I/O when this bit is set.

4 CARDC4

Clear this bit to drive a low level on the Card C4 pin (CC4 = P1.3 pin). Set this bit to set a high level on the Card C4 pin (CC4 = P1.3 pin). The CC4 pin can be used as a pseudo bi-directional I/O when this bit is set. bit to write a 0 in CIO (P1.0) port pin.

2 CARDCLK

When the CLK bit is cleared in SCCON Register, the value of this bit is driven to the Card CLK pin.

1 CARDRST

Clear this bit to drive a low level on the Card RST pin. Set this bit to set a high level on the Card RST pin.

0 CARDVCC

effect while this bit is cleared. Set this bit to power-on the Card interface. The activation sequence should be handled by software.

Table 46. Smart Card UART Interface Status Register - It is cleared by hardware when SCIBUF register is written.

6 CARDIN

This bit is set by hardware if there is a card presence (debouncing filter has to be done by software). This bit is cleared by hardware if there is no card presence.

5 ICARDOVF

4 VCARDOK

This bit is set when the output voltage is within the voltage range specified by VCARD[1:0] in SCICR register. This bit is set by hardware when th e Waiting Time Counter has expired. It is cleared by the reload of the counter or by the reset of the SCIB. It is cleared by software when this register is read.

1 SCRC

read the erroneous value if necessary. This bit is set when a parity error is detected on the received character. is found on the last allowed ICC character repetition.

Table 47. Smart Card UART Interrupt Identification Register (Read Only) Card UART. It generates an interrupt if ESCTBI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. The value read from this bit is indeterminate. Do not change this bit.

5 ICARDERR

It is cleared by hardware when this register is read.

4 VCARDERR

an interrupt if EVCARDER bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. generates an interrupt if ESCTI bit is set in SC IER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read.

1 SCRI

an interrupt if ESCRI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. generates an interrupt if ESCPI bit is set in SC IER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read.

Table 48. Smart Card UART Interrupt Enabling Register - SCIER (S:AEh, SCRS=1) Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt. Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt. The value read from this bit is indeterminate. Do not change this bit.

5 ICARDER

Clear this bit to disable the Card Current Overflow interrupt. Set this bit to enable the Card Current Overflow interrupt.

4 EVCARDER

Clear this bit to disable the Card Voltage Error interrupt. Set this bit to enable the Card Voltage Error interrupt. Clear this bit to disable the Waiting Time Counter timeout interrupt. Set this bit to enable the Waiting Time Counter timeout interrupt. Clear this bit to disable the Smart Ca rd UART Transmitted Character interrupt. Set this bit to enable the Smart Card UART Transmitted Character interrupt.

1 ESCRI

Clear this bit to disable the Smart Ca rd UART Received Character interrupt. Set this bit to enable the Smart Card UART Received Character interrupt. Clear this bit to disable the Smart Card Character Reception Parity Error interrupt. Set this bit to enable the Smart Card Character Reception Parity Error interrupt.

Table 49. Smart Card Selection Register - SCSR (S:ABh) The value read from this bit is indeterminate. Do not change this bit. counter is done on the rising edge of the BGTEN. Clear this bit to suppress the minimum time between reception and transmission. The value read from this bit is indeterminate. Do not change this bit.

4 CREPSEL

00 ALTKPS = 0: prescaler factor equals 1

01 ALTKPS = 1: prescaler factor equals 2

10 ALTKPS = 2: prescaler factor equals 4 (reset value)

11 ALTKPS = 3: prescaler factor equals 8

0 SCRS Smart Card Register Selection

The SCRS bit selects which set of the SCIB registers is accessed. Table 50. Smart Card Transmit / Receive Buffer - SCIBUF (S:AA)

• A new byte can be written in the buffer to be transmitted on the I/O pin when SCTBE bit is set.

The bits are sorted and copied on the I/O pin versus the active convention.

• A new byte received from I/O pin is ready to be read when SCRI bit is set.

The bits are sorted versus the active convention.

Table 51. Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1) integer with an error less than 1/4 of Card CLK period). Set this bit otherwise and reduce the ETU per iod by 1 Card CLK cycle for even bits. The value read from these bits is indeterminate. Do not change these bits. Warning : the ETU counter is reloaded at each register’s write operation. Table 52. Smart Card ETU Register 0 - SCETU0 (S:ACh, SCRS=1) The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK frequency. According to ISO 7816, ETU[10:0] can be set between 11 and 2048. The default reset value of ETU[10:0] is 372 (F=372, D=1).

Table 53. Smart Card Transmit Guard Time Register 0 - SCGT0 (S:B4h, SCRS=1) Guard Time +10 (see Guard Time Counter description. Table 54. Smart Card Transmit Guard Time Register 1 - SCGT1 (S:B5h, SCRS=1) The value read from these bits is indeterminate. Do not change these bits. Used together with the Transmit Guard Time LSB in SCGT0 register (Table 53). Table 55. Smart Card Character/Block Waiting Time Register 3 Used together with WT[23:0] in registers SCWT2,SCWT1, SCWT0 (see Table 56).

Table 56. Smart Card Character/Block Waiting Time Register 2 Used together with WT[31:24] and WT[15:0] in registers SCWT3,SCWT1, SCWT0 (see Table 58). Table 57. Smart Card Character/Block Waiting Time Register 1 Used together with WT[31:16] and WT[7:0] in registers SCWT3,SCWT2, SCWT0 (see Table 55). Table 58. Smart Card Character/Block Waiting Time Register 0 WT[31:0] is the reload value of the Waiting Time Counter (WTC) . page 77 and Section “Waiting Time (WT) Counter”, page 67). check the maximum time between to consecutive start bits.

• The SCICR register (Table 44 on page 77) controls the CVCC level by means of bits VCARD[1:0].
• The SCCON register (Table 45 on page 78) enables to switch the DC/DC converter on or off by means of bit CARDVCC.
• The DCCKPS register (Table 61 on page 92) controls the DC/DC clock and current. The DC/DC converter cannot be switched on while the CPRES pin remains inactive. If CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut down sequence of the DC/DC converter is initiated by the electronics. It is mandatory to switch off the DC/DC Converter before entering in Power-down mode. Configuration The DC/DC Converter can work in two different modes which are selected by bit MODE in DCCKPS register:
• Pump Mode: an external inductance of 10 μH must be connected between pins LI and VCC. VCC can be higher or lower than CVCC.
• Regulator mode : no external inductance is required but VCC must be always higher than CVCC+0.3V. The Regulation mode will work even if an external inductance of 10 μH is connected between pins LI and VCC The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS regis- ter must be configured to set the DC/DC clock to a working frequency of 4 MHz which depends upon the value of the crystal. There is no need to change the default configura- tion set by the reset sequence if an 8 MHz crystal is used by the application. The DC/DC Converter implements a current overflow controller which avoids permanent damage of the DC/DC converter in case of short circuit between CVCC and CVSS. The maximum limit is around 100 mA. It is possible to increase this limit in normal operating

Table 59. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1) If XTSCS bit is set OR EXT48 bit is set (in P LLCON register) , CK_PLL is used to generate CK_ISO. Otherwise, CK_XTAL1 is used to generate CK_ISO. See the Clock Tree diagram figure 17. The value read from this bit is indeterminate. Do not change these bits. Prescaler 2 reload value is used to defines the card clock frequency. SCICLK[5:0] must be smaller than 49.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 mode by 20% by means of bit OVFADJ in DCCKPS register. When the current overflow controller is operating, the ICARDOVF is set by the hardware in SCISR register. The current drawn from power supply by t he DC/DC converter is controlled during the startup phase in order to avoid high transient current mainly in Pump Mode which could cause the power supply voltage to drop dramatically. This control is done by means of bits BOOST[1:0], which increases progressively the startup current level. Initialization Procedure The initialization procedure is different depending upon the required Card Vcc. One pro- cedure apply for Card Vcc =< 3 volts and one procedure for Card Vcc = 5 volts. The initialization procedure involves :

• Select the CVCC level by means of bits VCARD[1:0] in SCICR register,
• Set bits BOOST[1:0] in DCCKPS register following the current level control wanted.
• Switch the DC/DC on by means of bit CARDVCC in SCCON register,
• Monitor bit VCARDOK in SCISR register in order to know when the DC/DC Converter is ready (CVCC voltage has reached the expected level) Procedure for CVcc =< 3 volts The DC/DC regulation mode must be selected for Card Vcc = 1.8 volts and Card Vcc = 3 volts (MODE = 1 in DCCKPS register) The detailed procedures is described in flow chart of Figure 45. for Card Vcc = 1.8 volts and in the flow chart of Figure 46. for Card Vcc = 3 volts

Figure 45. Card Vcc = 1.8V Initialization Procedure

Figure 46. Card Vcc = 3V Initialization Procedure

detailed procedure is described in flow chart of Figure 47. Figure 47. Card Vcc = 5V Initialization Procedure necessary to increment the BOOST[1:0] bits until the DC/DC converter is ready.

converter by means of bits VCARDOK and ICARDOVF in the SCISR register. Table 60. DC/DC converter status

• Not Started or switched off by application.

to start and both bits VCARDOK and ICARDOVF remains at 0. DC/DC converter in compliance with ISO/IEC 7816.

Table 61. DC/DC Converter Control Register - DCCKPS (S:BFh)

6 OVFADJ

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 USB Controller The AT8xC5122D implements a USB device controller supporting Full Speed data transfer. In addition to the default control endpoint 0, it provides 6 other endpoints, which can be configured in Control, Bulk, Interrupt or Isochronous modes:

• Endpoint 0: 32-byte FIFO, default control endpoint
• Endpoint 1,2,3: 8-byte FIFO
• Endpoint 4,5: 64-byte FIFO
• Endpoint 6: 2 x 64-byte Ping-pong FIFO This allows the firmware to be developed co nforming to most USB device classes, for example:
• USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.0 - December 14, 1998.
• USB Mass Storage Class Bulk-Only Transport, Revision 1.0 - September 31, 1999.
• USB Human Interface Device Class, Version 1.1 - April 7, 1999.
• USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999. USB Mass Storage Classes USB Mass Storage Class CBI Transport Within the CBI framework, the Control endpoint is used to transport command blocks as well as to transport standard USB requests. One Bulk-Out endpoint is used to transport data from the host to the device. One Bulk-In endpoint is used to transport data from the device to the host. And one interrupt endpoint may also be used to signal command completion (protocol 0); it is optional and may not be used (protocol 1). The following configuration adheres to these requirements:
• Endpoint 0: 8 bytes, Control In-Out
• Endpoint 4: 64 bytes, Bulk-Out
• Endpoint 5: 64 bytes, Bulk-In
• Endpoint 1: 8 bytes, Interrupt In USB Mass Storage Class Bulk- Only Transport Within the Bulk-Only framework, the Control endpoint is only used to transport class- specific and standard USB requests for device set-up and configuration. One Bulk-Out endpoint is used to transport commands and data from the host to the device. One Bulk- In endpoint is used to transport status and data from the device to the host. No interrupt endpoint is needed. The following configuration adheres to these requirements:
• Endpoint 0: 8 bytes, Control In-Out
• Endpoint 4: 64 bytes, Bulk-Out
• Endpoint 5: 64 bytes, Bulk-In USB Device Firmware Upgrade (DFU) The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip program memory of the AT8xC5122D. This allows the implementation of product enhancements and patches to devices that are already in the field. Two different config- urations and description sets are used to support DFU functions. The Run-Time configuration co-exists with the usual functions of the device, which may be USB Mass Storage for the AT8xC5122D. It is used to initiate DFU from the normal operating mode. The DFU configuration is used to perform the firmware update after device re-configura- tion and USB reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to support DFU services in both configurations.

which is the size of the FIFO implemented for endpoint 0. is compliant with the jitter specification of the USB bus. Figure 48. USB Device Controller Block Diagram

• NRZI data encoding and decoding.
• Bit stuffing and unstuffing.
• CRC generation and checking.
• Handshakes.
• TOKEN type identifying.
• Address checking.
• Clock generation (via DPLL). SIE DPLL USB D+/D- Buffer UFI 12MHz 48 MHz +/- 0.25% Up to 48 MHz UC_SYSCLK C51 Microcontroller Interface

Figure 51. Minimum Intervention from the USB Device Firmware

rectly generated (Section "Clock Controller", page 39).

• Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register. This action will allow the USB controller to answer to the requests sent at the address 0. When a SET_ADDRESS request has been received, the USB controller must only answer to the address defined by the request. The new address should be stored in the USBADDR register. The FEN bit and the FADD EN bit in the USBCON register should be set to allow the USB controller to answer only to requests sent at the new address.
• Set configuration The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should be cleared. Endpoint Configuration • Selection of an Endpoint The endpoint register access is performed us ing the UEPNUM register. The following registers correspond to the endpoint whose number is stored in the UEPNUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM register. – UEPSTAX, – UEPCONX, –U E P D A T X , – UBYCTX,

Figure 52. Endpoint Selection

• Endpoint enable Before using an endpoint, this one should be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests.
• Endpoint type configuration All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be conf igured in Bulk, Interrupt or Isochronous mode. The configuration of an endpoint is performed by setting the field EPTYPE with the following values: – Control: EPTYPE = 00b – Isochronous: EPTYPE = 01b – Bulk: EPTYPE = 10b – Interrupt: EPTYPE = 11b The Endpoint 0 is the Default Control Endpoint and should always be configured in Con- trol type.
• Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoint s, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: – IN:EPDIR = 1b –O U T : E P D I R = 0 b For Control endpoints, the EPDIR bit has no effect.
• Summary of Endpoint Configuration: Make sure to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers.

Table 62. Summary of Endpoint Configuration

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008

• Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the byte counter of the endpoint (UBYCTX register), and resets the data toggle bit (DTGL bit in UEPCONX). The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corre- sponding bit in the UEPRST register. For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000 0000b in the UEPRST register.

Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. counter is not updated when reading the FIFO. address vector, and the next data is then available in the UEPDATX register. Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register. automatically increased, and another write can be carried out. Warning 1: The byte counter is not updated. Warning 2: Do not write more bytes than supported by the corresponding endpoint. Figure 53. Endpoint FIFO Configuration

8 Bytes

32 Bytes

64 Bytes

Bulk and Interrupt transactions are managed in the same way. Figure 54. Bulk/Interrupt OUT transactions in Standard Mode to 0 and no data has to be read. answer a NAK handshake for each OUT requests. correct and the endpoint byte counter contains the number of bytes sent by the Host.

Figure 55. Bulk / Interrupt OUT Transactions in Ping-Pong Mode equal to 0 and no data has to be read. OUT requests on the bank 0 endpoint FIFO. OUT requests on the bank 1 endpoint FIFO. allow a new valid packet to be stored in the corresponding bank.

Figure 56. Bulk/Interrupt IN Transactions in Standard Mode should set the TXRDY bit without writing any data into the endpoint FIFO. handshake for each IN requests. The firmware should never write more bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller.

Figure 57. Bulk / Interrupt IN transactions in Ping-Pong mode and the firmware can immediately write into the endpoint FIFO bank 1. with new data. The FIFO banks are then automatically switched. firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1. The firmware will never write more bytes than supported by the endpoint FIFO.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Control Transactions Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the Rxsetup bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEP- STAX register are cleared and an interrupt is triggered if enabled. The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing the RXSETUP bit to free the endpoint FIFO for the next transaction. Data Stage: Control Endpoint Direction The data stage management is similar to Bulk management. A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register.

• If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the hardware. The firmware should clear the TXCMPL bit before any other transaction.
• If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new valid packet has been received on the endpoint. The firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction. The bit DIR is used to send the correct data toggle in the data stage. To send a STALL handshake, see “STALL Handshake” on page 108. Status Stage The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage. The status stage management is similar to Bulk management.
• For a Control Write transaction or a No-Data Control transaction, the status stage consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions In Standard Mode” on page 103). To send a STALL handshake, see “STALL Handshake” on page 108.
• For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 101).

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Isochronous Transactions Isochronous OUT Transactions in Standard Mode An endpoint should be first enabled and configured before being able to receive Isochro- nous packets. When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corre- sponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost. If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only the remaining bytes into the FIFO. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous OUT Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to receive Isochro- nous packets. When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the cor- responding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to store the next OUT packet data into the end- point FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost. If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB controller will store only the remaining bytes into the FIFO. When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt. The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous IN Transactions in Standard Mode An endpoint should be first enabled and configured before being able to send Isochro- nous packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more bytes than supported by the endpoint FIFO. Isochronous IN Transactions in Ping-Pong Mode An endpoint should be first enabled and configured before being able to send Isochro- nous packets. The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoi nt. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won’t send anything at each IN requests concerning this bank. The firmware should never write more bytes than supported by the endpoint FIFO.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Miscellaneous USB Reset The EORINT bit in the USBINT register is set by hardware when a End of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con- troller is still enabled, but all the USB regi sters are reset by hardware. The firmware should clear the EORINT bit to allow the next USB reset detection. STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled. The firmware should clear the STALLRQ and STLCRC bits after each STALL sent. The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on a CONTROL type endpoint. Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. Frame Number When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of Frame is valid (CRCOK set at 1) or corrupt (CRCERR set at 1). The UFNUML and UFNUMH registers are automatically updated when receiving a new Start of Frame. Data Toggle Bit The Data Toggle bit is set by hardware when a DATA 0 packet is received and accepted by the USB controller and cleared by hardware when a DATA 1 packet is received and accepted by the USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST register. For Control endpoints, each SETUP transaction starts with a DATA 0 and data toggling is then used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA 1 (for a control read transfer). For Isochronous endpoints, the device firmware should ignore the data-toggle. NAK Handshakes When a NAK handshake is sent by the USB controller to a IN or OUT request from the Host, the NAKIN or NAKOUT bit is set by hardware. This information can be used to determine the direction of the communication during a Control transfer. These bits are cleared by software.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Suspend/Resume Management Suspend The Suspend state can be detected by the U SB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-up event is detected. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS- PCLK bit in the USBCON register. 2. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an inter- rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware will first enable the 48 MHz gener- ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated.

Figure 58. Example of a Suspend/Resume Management Warning: The core must be switched in external clock mode before disabling the PLL.

Figure 59. Example of REMOTE WAKEUP Management

Figure 62. USB Interrupt Control System

• TXCMPL: Transmitted In Data (Table 70 on page 119). This bit is set by hardware when the Host accept a In packet.
• RXOUTB0: Received Out Data Bank 0 (Table 70 on page 119). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 70 on page 119). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1.
• RXSETUP: Received Setup (Table 70 on page 119). This bit is set by hardware when an SETUP packet is accepted by the endpoint.
• NAKIN and NAKOUT: These bits are set by hardware when a Nak Handshake has been received on the corresponding endpoint. These bits are cleared by software.
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table on page 120). This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ, and is reset by hardware when a SETUP packet is received.
• SOFINT: Start Of Frame Interrupt (Table 65 on page 116). This bit is set by hardware when a USB start of frame packet has been received.
• WUPCPU: Wake-Up CPU Interrupt (Table 65 on page 116). This bit is set by hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
• SPINT: Suspend Interrupt (Table 65 on page 116). This bit is set by hardware when a USB suspend is detected on the USB bus. EUSB IEN1.6 EA IEN0.7 USB Controller IPH/L Interrupt Enable Lowest Priority InterruptsPriority Enable

Table 63. Priority Levels

Figure 63. USB Interrupt Control Block Diagram

Table 64. USB Global Control Register - USBCON (S:BCh) Set this bit to enable the USB controller. transceiver and to disable the USB controller clock inputs. Set this bit to disable the 48MHz clock input (Resume Detection is still active). Clear this bit to enable the 48MHz clock input. below. This bit is cleared by software. Clear this bit to maintain VREF at 3.3V. This bit is cleared by hardware after the upstream resume has been sent. Set this bit to enabled request an upstream resume signaling to the host. request with a non-zero value has been correctly processed. bit times: typically 2.7 μs).

0 FADDEN

hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the def ault function address is used (0).

Table 65. USB Global Interrupt Register - USBINT (S:BDh) The value read from these bits is always 0. Do not change these bits.

5 WUPCPU

re-activated by a non-idle signal FROM US B line (not by an upstream resume). This triggers a USB interrupt when EWUPCP U is set in the Table on page 117. When receiving this interrupt, user has to enable all USB clock inputs. This bit should be cleared by software (USB clocks must be enabled before). This bit should be cleared by software. This bit should be cleared by software. The value read from these bits is always 0. Do not change these bits. ESPINT is set in USBIEN register (Table 66 on page 117). as it disables the USB pads to reduce the power consumption.

Table 66. USB Global Interrupt Enable Register - USBIEN (S:BEh) The value read from these bits is always 0. Do not change these bits. Set this bit to enable Wake-up CPU Interrupt. Clear this bit to disable Wake-up CPU Interrupt.

4 EEORINT

Set this bit to enable End of Reset Interrupt. This bit is set after reset. Clear this bit to disable End of Reset Interrupt. Set this bit to enable SOF Interrupt. Clear this bit to disable SOF Interrupt. The value read from these bits is always 0. Do not change these bits. Set this bit to enable Suspend Interrupts (See Table 65 on page 116). Clear this bit to disable Suspend Interrupts. Table 67. USB Address Register - USBADDR (S:C6h) Set this bit to enable the function. FADD is reset to 1. Cleared this bit to disable the function. This field contains the default address (0) after power-up or USB bus reset.

Table 68. USB Endpoint Number - UEPNUM (S:C7h) The value read from these bits is always 0. Do not change these bits. UEPCONX (S:D4h). This value can be 0, 1, 2, 3, 4, 5 or 6. Table 69. USB Endpoint X Control Register - UEPCONX (S:D4h)

7 EPEN

a hardware or USB bus reset and participate in the device configuration. Clear this bit to disable the endpoint according to the device configuration. Set this bit to enable NAKIN and NAKOUT Interrupt. Clear this bit to disable NAKIN and NAKOUT Interrupt. the Host. This generates an interrupt if the NAKIEN bit is set. This bit shall be cleared by software. Host. This generates an interrupt if the NAKIEN bit is set. This bit shall be cleared by software. This bit is set by hardware when a vali d DATA0 packet is received and accepted. This bit is cleared by hardware when a va lid DATA1 packet is received and accepted. Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. This bit has no effect for Control endpoints.

Table 70. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPNUM Register) This bit determines the Control data and status direction. firmware should clear this bit.

6 RXOUTB1

This bit is set by hardware after a new packet has been stored in the endpoint FIFO Data bank 1 (only in Ping-pong mode). This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO.

5 STALLRQ

Set this bit to request a STALL answer to the host for the next handshake. For CONTROL endpoints: cleared by hardwar e when a valid SETUP PID is received.

4 TXRDY

FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. enabled (see Table 65 on page 116). It should be cleared by the device firmware. This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when a new data is received.

2 RXSETUP

are cleared by hardware and the endpoint interrupt is triggered if enabled (see Table 65 on page 116). It should be cleared by the device firmware after reading the SETUP data from the endpoint FIFO.

1 RXOUTB0

overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. This bit should be cleared by the dev ice firmware before setting TXRDY.

Table 71. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register) - Table 72. USB Byte Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX The value read from these bits is always 0. Do not change this bit. is equal to the number of data bytes received after the Data PID.

Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h) The value read from these bits is always 0. Do not change this bit. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO.

Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only) The value read from these bits is always 0. Do not change this bit. This bit is set by hardware when an interrupt has been detected on the endpoint 6. the EP6INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared. This bit is set by hardware when an interrupt has been detected on the endpoint 5. the EP5INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared. This bit is set by hardware when an interrupt has been detected on the endpoint 4. the EP4INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared. This bit is set by hardware when an interrupt has been detected on the endpoint 3. the EP3INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared. This bit is set by hardware when an interrupt has been detected on the endpoint 2. the EP2INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared. This bit is set by hardware when an interrupt has been detected on the endpoint 1. the EP1INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared. This bit is set by hardware when an interrupt has been detected on the endpoint 0. the EP0INTE bit in the UEPIEN register is set. This bit is cleared by hardware when al l the interrupt sources are cleared.

Table 75. USB Endpoint Interrupt Enable Register - UEPIEN (S:C2h) The value read from these bits is always 0. Do not change this bit. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint.

Figure 66. UART Timings in Modes 2 and 3 nication feature is enabled (SM2 bit in SCON register is set). is not interrupted by command frames addressed to other devices. be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). slaves at a time. The following example illustrates how a given address is formed.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To commu- nicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t care bits, e.g.: SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that does not support automatic address recognition. Timer 1 When using the Timer 1, the Baud Rate is derived from the overflow of the timer. As shown in Figure 67 the Timer 1 is used in its 8-bit auto-reload mode). SMOD1 bit in PCON register allows doubling of the generated baud rate.

Table 77. Serial Control Register - SCON (98h) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection. Clear to disable multiprocessor communication feature. This bit should be cleared in mode 0. Clear to disable serial reception. Set to enable serial reception. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Clear to acknowledge interrupt. stop bit in the other modes. This bit can aslo be set by software. Clear to acknowledge interrupt. This bit can aslo be set by software.

Table 82. Baud Rate Control Register - BDRCON - (9Bh) Table 78. Slave Address Mask Register for UART - SADEN (B9h) Table 79. Slave Address Register for UART - SADDR (A9h) Table 80. Serial Buffer Register for UART - SBUF (99h) Table 81. Baud Rate Reload Register for the internal baud rate generator, The value read from this bit is indet erminate. Do not change these bits. Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Cleared to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Cleared to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. CK_SI /6 as the Baud Rate Generator. Set to select the internal Baud Rate Generator for UART in mode 0.

serial communication between the MCU and peripheral devices, including other MCUs.

• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master Mode fault error flag with MCU interrupt capability
• Write collision flag protection Signal Description Figure 82 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices:

Figure 82. Typical SPI Bus port to control the four SS pins of the Slave devices. This 1-bit signal is directly connected betw een the Master Device and a Slave Device. is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This 1-bit signal is directly connected betw een the Slave Device and a Master Device. word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. which allows to exchange one byte on the serial lines.

3 Slave 3Slave 4

low for any message for a Slave. Only one Master (SS high level) can drive the network. the Master for a transmission. SCK (see Section “Error Conditions”, page 140). pin puts the MISO line of a Slave SPI in a high-impedance state.

• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in the SPSTA will never be set (1).
• The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This kind of configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device. Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is con- troled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of six clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. Table 83 gives the different clock rates selected by SPR2:SPR1:SPR0

Table 83. SPI Master Baud Rate Selection

1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in

this mode, the SS is used to start the transmission.

000 Reserved N/A

010 F CK_SPI / 8 8

011 F CK_SPI /16 16

100 F CK_SPI /32 32

101 F CK_SPI /64 64

110 F CK_SPI /128 128

111 Reserved N/A

Functional Description Figure 83 shows a detailed structure of the SPI module. Figure 83. SPI Module Block Diagram

• The Serial Peripheral Control register (SPCON) Once the SPI is configured, the data exchange is made using:
• SPCON
• The Serial Peripheral Status register (SPSTA)
• The Serial Peripheral Data register (SPDAT) During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam- pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS ) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 84). Shift Register 01234567 Internal Bus Pin Control Logic MISO MOSI SCK M S Clock Logic Clock Divider Clock Select /64 /128 SPI Interrupt Request 8-bit bus 1-bit signal SS IntClk /32 /16 Receive Data Register SPDAT SPI Control SPSTA CPHA SPR0SPR1CPOLMSTRSSDISSPENSPR2 SPCON WCOL MODFSPIF - --- -

Figure 84. Full-duplex Master-Slave Interconnection SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin. the transmission is established again, the data present in the SPDAT is resent. device must be set to ’0’. SS must remain low until the transmission is complete. sampled and the edges on which the output data are shifted (Figure 85 and Figure 86).

1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also

the Master SPI should be configured before the Slave SPI.

1. The SPI module should be configured as a Slave before it is enabled (SPEN set).
2. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
3. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).

only one Slave driving the MISO data line. Error Conditions The following flags in the SPSTA signal SPI error conditions.

• An SPI receiver/error CPU interrupt request is generated.
• The SPEN bit in SPCON is cleared. This disable the SPI.
• The MSTR bit in SPCON is cleared. When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes ’0’. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master is attempting to drive the net- work. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin. Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its orig- inal set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes and the Slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. SS Error Flag ( SSERR ) A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit ( reset of the SPI state machine ). Interrupts Two SPI status flags can generate a CPU interrupt requests:

Table 84. SPI Interrupts has been completed. SPIF bit generates transmitter CPU interrupt requests.

Table 85. Serial Peripheral Control Register - SPCON (C3h)

6 SPEN RW

• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error) Reset Value = 00X0XXXXb

Table 86. Serial Peripheral Status and Control Register - SPSTA (C4h) approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected.

5 SSERR R

Set by hardware when SS is modified before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). level, or has been approved by a clearing sequence. The value read from this bit is indet erminate. Do not change these bits.

Table 87. Serial Peripheral Data Register - SPDAT (C5h)

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Timers/Counters The AT8xC5122D implements two general-purpose, 16-bit Timers/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an exter- nal pin. After a preset number of counts, the Counter issues an interrupt request. The Timer registers and associated control registers are implemented as addressable Special Function Registers (SFRs). Two of the SFRs provide programmable control of the Timers as follows:

• Timer/Counter mode control register (TMOD) and Timer/Counter control register (TCON) control respectively Timer 0 and Timer 1. The various operating modes of each Timer/Counter are described below. Timer/Counter Operations For example, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in the TCON register (see Table 88 on page 150) turns the Timer on by allowing the selected input to incre- ment TLx. When TLx overflows, it increments THx and when THx overflows it sets the Timer overflow flag (TFx) in the TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but the TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down system clock or the external pin Tx as the source for the counted signal. The TRx bit must be cleared when changing the operating mode, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx#= 0), the Timer register counts the divided-down system clock. The Timer register is incremented once every peripheral cycle. Exceptions are the Timer 2 Baud Rate and Clock- Out modes in which the Timer register is incremented by the system clock divided by two. For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on the Tx external input pin. The external i nput is sampled during every S5P2 state. The Programmer’s Guide describes the notation for the states in a peripheral cycle. When the sample is high in one cycle and low in the next one, the Counter is incremented. The new count value appears in the register during the next S3P1 state after the transition has been detected. Since it takes 12 states (24 oscillator periods) to recognize a nega- tive transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full periph- eral cycle. Timer 0 Timer 0 functions as either a Timer or an event Counter in four operating modes. Figure 89 through Figure 95 show the logic configuration of each mode. Timer 0 is controlled by the four lower bits of the TMOD register (see Table 89 on page 151) and bits 0, 1, 4 and 5 of the TCON register (see Table 88 on page 150). The TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and the operating mode (M10 and M00). The TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and inter- rupt type control bit (IT0).

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008

• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
• It is important to stop the Timer/Counter before changing modes. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 89). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre- ments the TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Ti mer with TH1 and TL1 registers connected in cascade (see Figure 91). The selected input increments the TL1 register. Mode 2 (8-bit Timer with Auto- Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from the TH1 register on overflow (see Figure 93). TL1 overflow sets the TF1 flag in the TCON register and reloads TL1 with the contents of TH1, which is preset by the soft- ware. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when the TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

Table 88. TCON (S:88h) Cleared by the hardware when processor vectors interrupt routine. Set by the hardware when Timer 1 register overflows. Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Set by the hardware when Timer 0 register overflows. Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. Cleared by the hardware when interrupt is processed if edge-triggered (see IT1). Set by the hardware when external in terrupt is detected on the INT1# pin. Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. Cleared by the hardware when interrupt is processed if edge-triggered (see IT0). Set by the hardware when external interrupt is detected on INT0# pin. Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

Table 89. Timer/Counter Mode Control Register - TMOD (S:89h) Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 0 0 Mode 0:8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1:16-bit Timer/Counter. 1 0 Mode 2:8-bit auto-reload Timer/Counter (TL1) reloaded from TH1 at overflow. 1 1 Mode 3:Timer 1 halted. Retains count. Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 0 0 Mode 0:8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1:16-bit Timer/Counter. 1 0 Mode 2:8-bit auto-reload Timer/Counter (TL0). Reloaded from TH0 at overflow. 1 1 Mode 3:TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

Table 90. Timer 0 High Byte Register - TH0 (S:8Ch) Table 91. Timer 0 Low Byte Register - TL0 (S:8Ah) Table 92. Timer 1 High Byte Register - TH1 (S:8Dh) Table 93. Timer 1 Low Byte Register - TL1 (S:8Bh)

Table 94. Keyboard Flag Register - KBF (9Eh) Keyboard interrupt request if the KBE.7 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.6 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.5 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.4 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.3 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.2 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.1 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard interrupt request if the KBE.0 bit in KBE register is set. Cleared by hardware after the read of the KBF register.

Table 95. Keyboard Input Enable Register - KBE (9Dh)

7 KBE7

Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request.

6 KBE6

Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request.

5 KBE5

Cleared to enable standard I/O pin. Set to enable KBF.5 bit in KBF register to generate an interrupt request.

4 KBE4

Cleared to enable standard I/O pin. Set to enable KBF.4 bit in KBF register to generate an interrupt request.

3 KBE3

Cleared to enable standard I/O pin. Set to enable KBF.3 bit in KBF register to generate an interrupt request.

2 KBE2

Cleared to enable standard I/O pin. Set to enable KBF.2 bit in KBF register to generate an interrupt request.

1 KBE1

Cleared to enable standard I/O pin. Set to enable KBF.1 bit in KBF register to generate an interrupt request.

0 KBE0

Cleared to enable standard I/O pin. Set to enable KBF.0 bit in KBF register to generate an interrupt request.

Table 96. Keyboard Level Selector Register - KBLS (9Ch) Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Interrupt System Introduction The AT83R5122, AT8xC5122/23 implements an interrupt controller with 15 inputs but only 9 are used for : – two external interrupts (INT0 and INT1) – two timer interrupts (timers 0, 1), – the UART interface – the SPI interface – the keyboard interface – the USB interface – the Smart Card Interface. Interrupt System Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable registers (Table 98 on page 160 and Table 99 on page 161). These registers also contain a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority lev- els by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on page 162 and Table 103 on page 164) and in the Interrupt Priority High register (Table 102 on page 163 and Table 105 on page 166) shows the bit values and priority levels associ- ated with each combination. A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. Thus within each priority level there is a second priority structure deter- mined by the polling sequence. Table 97. Priority Level Bit Values

Figure 99. Interrupt Control System

1 KBFx

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 INT1 Interrupt Vector The INT1 interrupt is multiplexed with the following three inputs:

• INT1 : Standard 8051 interrupt input
• RXD : Received data on UART
• CPRES: Insertion or remove of the main card The setting configurations for each input is detailed below. INT1 Input This interrupt input is active under the following conditions :
• It must be enabled by OEEN Bit (ISEL Register)
• It can be active on a level or falling edge following IT1 Bit (TCON Register) status
• If level triggering selection is set, the active level 0 or 1 can be selected with OELEV Bit (ISEL Register) The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is cleared when interrupt is processed. RXD Input A second vector interrupt input is the reception of a character. UART Rx input can gen- erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA must also be set. Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on P3.0/RXD input. CPRES Input The third input is the detection of a level change on CPRES input (P1.2). This input can generate an interrupt if enabled with PRESEN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7) Bits. This detection is done according to the level selected with Bit CPLEV (ISEL.7). Then the Bit PRESIT (ISEL.5) is set by hardw are when the triggering conditions are met. This Bit must be cleared by software.

Table 98. Interrupt Enable Register 0 - IEN0 (A8h) Cleared to disable all interrupts. Set to enable all interrupts. The value read from this bit is indeterminate. Do not change these bits. Cleared to disable serial port interrupt. Set to enable serial port interrupt. Cleared to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. Cleared to disable external interrupt 1. Set to enable external interrupt 1. Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. Cleared to disable external interrupt 0. Set to enable external interrupt 0.

Table 99. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5122 The value read from this bit is indeterminate. Do not change this bit. Cleared to disable USB interrupt . Set to enable USB interrupt. The value read from this bit is indet erminate. Do not change these bits. Cleared to disable SCIinterrupt . Set to enable SCI interrupt.

2 ESPI

Cleared to disable SPI interrupt . Set to enable SPI interrupt. The value read from this bit is indeterminate. Do not change this bit. Cleared to disable keyboard interrupt . Set to enable keyboard interrupt.

Table 100. Interrupt Enable Register 1 - IEN1 (B1h) for AT83C5123 The value read from this bit is indeterminate. Do not change this bit. Cleared to disable USB interrupt . Set to enable USB interrupt. The value read from this bit is indet erminate. Do not change these bits. Cleared to disable SCIinterrupt . Set to enable SCI interrupt.

2 Reserved

The value read from this bit is indeterminate. Do not change this bit. The value read from this bit is indeterminate. Do not change this bit.

0 Reserved

The value read from this bit is indeterminate. Do not change this bit. Table 101. Interrupt Priority Low Register 0 - IPL0 (B8h) The value read from this bit is indeterminate. Do not change these bits. Refer to PSH for priority level. Refer to PT1H for priority level.

2 PX1L External interrupt 1 Priority bit

Refer to PX1H for priority level. Refer to PT0H for priority level.

0 PX0L External interrupt 0 Priority bit

Refer to PX0H for priority level.

Table 102. Interrupt Priority High Register 0 - IPH0 (B7h) The value read from this bit is indeterminate. Do not change these bits.

Table 103. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC5122 The value read from this bit is indeterminate. Do not change this bit. Refer to PUSBH for priority level. The value read from this bit is indeterminate. Do not change these bits. Refer to PSPIH for priority level.

2 PSPIL SPI Interrupt Priority bit

Refer to PSPIH for priority level. The value read from this bit is indeterminate. Do not change this bit. Refer to PKBDH for priority level.

Table 104. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT83C5123 The value read from this bit is indeterminate. Do not change this bit. Refer to PUSBH for priority level. The value read from this bit is indeterminate. Do not change these bits. Refer to PSPIH for priority level. The value read from this bit is indeterminate. Do not change this bit.

1 Reserved

The value read from this bit is indeterminate. Do not change this bit. The value read from this bit is indeterminate. Do not change this bit.

Table 105. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5122 The value read from this bit is indeterminate. Do not change this bit. The value read from this bit is indeterminate. Do not change these bits. The value read from this bit is indeterminate. Do not change this bit.

Table 106. Interrupt Priority High Register 1 - IPH1 (B3h) for AT83C5123 The value read from this bit is indeterminate. Do not change this bit. The value read from this bit is indeterminate. Do not change these bits. The value read from this bit is indeterminate. Do not change these bits. The value read from this bit is indeterminate. Do not change this bit. The value read from this bit is indeterminate. Do not change these bits.

Table 107. Interrupt Enable Register - ISEL (S:A1h)

7 CPLEV

The value read from this bit is indeterminate. Do not change this bit.

5 PRESIT

4 RXIT

3 OELEV

Set this bit to indicate that high level is active. Clear this bit to indicate that low level is active.

2 OEEN

1 PRESEN

Clear to disable the card presence detection interrupt coming from SCIB. Set to enable the card presence detection interrupt coming from SCIB.

0 RXEN

Clear to disable the RxD interrupt.

Table 108. Interrupt Vectors

– the active state duration is at least two machine cycles. Figure 100. Reset bock diagram

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Power On Reset (POR) The role of the POR is to monitor the power supply rise of the microcontroller core and release the internal reset only when the internal voltage exceeds the VPFDP threshold from which the microcontroller core is stable (see Figure 101). This feature replaces the external reset function and therefore avoid the use of external components on the reset pin. Power Fail Detector (PFD) The role of the PFD is to monitor the power supply falls during a steady state condition in order to suspend the microcontroller and peripherals activity as soon as the power supply drops below the VPFDM threshold from which the microcontroller’s core might become instable (see Figure 101). The PDF sus pends the microcontroller’s activity by holding the microcontroller under a reset state to avoid an unpredictable behaviour. A filter prevents the system fr om reseting when glitches lower than 50 ns duration are carried on Vcore. See Figure 101 and Figure 102 on page 172.

be executed within the time required to prevent a WDT reset. The WDT is controlled by two registers (WDTRST and WDTPRG). Figure 107. Watchdog Timer

Table 109. Watchdog Timer Out Register - WDTPRG (0A7h) The value read from this bit is indeterminate. Do not change these bits.

2 S2 WDT Time-out select bit 2

1 S1 WDT Time-out select bit 1

0 S0 WDT Time-out select bit 0

Table 110. Machine Cycle Count

Table 111. Timeout value for FCK_WD = 24 MHz / X2 Table 112. Watchdog Timer Enable register (Write Only) - WDTRST (A6h)

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Power Management Before activating the Idle Mode or Power Down Mode, the CPU clock must be switched to on-chip oscillator source if the PLL is used to fed the CPU clock. Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high level. There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one fol- lowing the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured dur- ing normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. Power Down Mode To save maximum power, a power-down mode can be invoked by software (see Table 13, PCON register). WARNING: To minimize power consumption, all peripherals and I/Os with static current consumption must be set in the proper state. I/Os programmed with low speed output configuration (KB_OUT) must be switch to push-pull or Standard C51 configuration before entering power-down. The CVCC generator must also be switch off. In power-down mode, the oscillator is st opped and the instruction that invoked power- down mode is the last instruction execut ed. The internal RAM and SFRs retain their value until the power-down mode is terminated. V CC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power- down. To properly terminate power-down, the reset or external interrupt should not be executed before V CC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 , INT1, Keyboard, Card insertion/removal and USB Inter- rupts are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power-down mode, 1024 clocks are necessary to exit to power-down mode and enter in operating mode. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 108. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input is released. In this case, the higher pr iority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT83R5122, AT8xC5122/23 into power-down mode.

Figure 108. Power-down Exit Waveform interrupt does no affect the SFRs. Table shows the state of ports during idle and power-down modes. Note: 1. Port 0 can force a 0 level. A "one" will leave port floating. fetches. During ALE disabling, ALE pin is weakly pulled high.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 USB Interface Suspend The Suspend state can be detected by the U SB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-up event is detected. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS- PCLK bit in the USBCON register. 2. If CPU clock is fed from PLL, the on-chip oscillator must be selected to fed the CPU clock. 3. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an inter- rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware will first enable the 48 MHz gener- ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated.

Figure 109. Example of a Suspend/Resume Management Warning: The core must be switched in external clock mode before disabling the PLL.

• Set CRST pin at low level by clearing the bit CARDRST in SCCON register.
• Set CCLK pin at low level by clearing the bit CLK then the CARDCLK in SCCON register.
• Set CIO pin at low level by clearing the bit UART in SCICR register then the bit CARDIO in SCCON register.
• Power the Smart Interface off by clearing the CARDVCC bit in SCCON register. This instruction enables to switch DC/DC converter off. CPRES input:
• Set the bit PRSEN in ISEL register
• Set the bit EX1 in IE0 register
• Set the bit EA in the IE0 register
• Invert the bit CPLEV in ISEL register (INT1 interrupt vector)
• Clear the bit PRESIT in the ISEL register USB Controller Init Detection of a SUSPEND State SPINT Set SUSPCLK Disable PLL microcontroller in power-down Detection of a RESUME State WUPCPU Enable PLL Clear SUSPCLK Clear WUPCPU bit Clear SPINT Note : WUPCPU bit must be Cleared before enabling the PLL Put the USB pads in power down mode

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Exiting from Power-down Mode The microcontroller will exit from Power-down or Idle modes upon a reset or INT1 inter- rupt which is a multiplexing of the interruptions generated by the CPRES pin (Card detection), RxD flag (UART reception) and INT1 pin. Keyboard Interface The keyboard interface applies only to AT8xC5122 version. Entering in Power-down Mode In order to reduce the power consumption, the microcontroller can be set in power-down or idle mode by software (see Table 13, PCON register). Before activating these modes the application will need to configure the keyboard interface as follows:

• Set all keyboard’s ouputs pins KB Rx at low level by writing a 0 on the ports. This operation has a double effect: – any key that is pressed generates an interrupt capable of waking-up the microcontroller, – Set all bits KBE.x in KBE registers to enable interrupts. Exiting from Power-down Mode The microcontroller will exit from Power-down Mode upon a reset or any interrupt gener- ated by a key press. Note that 1024 clocks are necessary to exit from power-down mode when a keyboard interrupt occurs. This means that there will be a delay between the time at which the key is pressed and the time at which the application is able to identify the key. Watchdog Timer during Power-down and Idle Mode In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode the user does not need to service the WDT. There are 2 methods of exiting Power-down mode : by a hardware reset or by a level activated external interrupt which is enabled prior to entering power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever AT8xC5122D is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting while the microcontroller is in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.

doesn’t affect the value of this bit. Table 113. Power Control Register - PCON (S:87h) The value read from this bit is indeterminate. Do not change this bit. Warning : in CRAM and FLASH versions, this bit is reserved.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008

Electrical Characteristics

TA = -40 to +85°C; VSS = 0 V, FCK_CPU= 0 to 24 MHz , VCC = 3.0V to 5.5V Power Dissipation 1 W Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. Symbol Parameter Min Typ Max Unit Test Conditions VIL Input Low Voltage -0.5 0.2 V CC - 0.1 V VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 V CC + 0.5 V VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V VOL Output Low Voltage: P0, ALE, PSEN 0.45 V I OL = 1.6 mA VOH Output High Voltage: P0, ALE, PSEN 0.9 V CC VI OH = 10 μA VOL1 Output Low Voltage: P2, P3, P4, P5, P1.2, P1.6, P1.7 0.45 V I OL = 0.8 mA VOH1 Output High Voltage: P2, P3, P4, P5, P1.2, P1.6, P1.7 0.9 VCC VI OH = -10 μA IIL Logical 0 Input Current ports 2 to 5 and P1.2, P1.6, P1.7, if Weak pull-up enabled -50 μA Vin = 0.45 V ILI Input Leakage Current ±10 μA 0.45 V < V IN < VCC ITL Logical 1 to O transistion Current, Port 51 configuration −650 μAV IN = 2 V RMEDIUM Medium Pullup Resistor 10 k Ω RWEAK Weak Pullup Resistor 100 k Ω CIO Capacitance of I/O Buffer 10 pF Fc = 1MHz TA = 25°C DVCC Digital Supply Voltage 3 3.4 3.6 V C L = 470 nF DICC Digital Supply Output Current (DVcc pin) 10 mA CL = 100 nF FCK_CPU = 24 MHz VPFDP Power Fail High Level Threshold 2.8 3 V VPFDM Power Fail Low Level Threshold 2,5 2.6 V trise, tfall VDD rise and fall time 1 μs 600 second

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 RRST Internal reset pull-up resistor 5 10 30 k Ω IPD Power down consumption 60μA 40μA 200μA 200μA Vcc = 5.5V Vcc = 3.6V ICCIDLE Power Supply current in IDLE mode 0.4*F+2 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT89C5122) with DC/DC ON 1.6*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT85C5122) with DC/DC ON 1.6*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT83C5122) with DC/DC ON 1.6*F+2 mA Vcc = 5.5V (F in MHz) ICCWRITE Power Supply current in Active mode (AT89C5122) Flash or E2PROM write DC/DC ON 1.6*F+4 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT89C5122) with DC/DC OFF 0.8*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT85C5122) with DC/DC FF 0.8*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT83C5122) with DC/DC OFF 0.8*F+2 mA Vcc = 5.5V (F in MHz) ICCWRITE Power Supply current in Active mode (AT89C5122) Flash or E2PROM write DC/DC OFF 0.8*F+4 mA Vcc = 5.5V (F in MHz) Symbol Parameter Min Typ Max Unit Test Conditions

Figure 111. Active and Idle Mode All other pins are disconnected. All other pins are disconnected.

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Smart Card Interface Card VCC 5V (for IEC7816-3 Class A cards) Symbol Parameter Min Typ Max Unit Test Conditions Vcc Power Supply 3.0 5.5 V CI CC_ovf Card Supply Current overflow 100 mA CVCC Card Supply Voltage 4.6 5.4 V VccMin = 4.0V, CICC = 60 mA VccMin = 3.0V, CICC = 30 mA Ripple on Card Voltage 200 mV 0 < CIcc < 60 mA CVCC Card Supply Voltage during spike on Icc 4.5 5.5 Max. charge 20 nA.s Max. duration 400 ns Max. variation CI CC 100 mA TOFF CVcc to 0 750 μs Cload=10μF, Lload=10μH Vcard = CVcc to 0.4V TON 0 to CVcc 750 μs Cload=10μF, Lload=10μH Vcard = 0V to CVcc With Boost at 60% Card VCC 3V Power Supply (for IEC7816-3 Class B cards) Symbol Parameter Min Typ Max Unit Test Conditions Vcc Power Supply 3.0 5.5 V CI CC_ovf Card Supply Current overflow 100 mA CVCC Card Supply Voltage 2.76 3.24 V VccMin = 3.6V, CICC = 55mA VccMin = 3.0V, CICC = 30 mA Ripple on Vcard 200 mV 0 < CI CC < 55mA CVCC Card Supply Voltage during spike on Icc 2.7 3.3 V Maxi. charge 10nA.s Max. duration 400 ns Max. variation CI CC 50mA TOFF CVcc to 0 750 μs Cload=10μF, Lload=10μH Vcard = CVcc to 0.4V TON 0 to CVcc 750 μs Cload=10μF, Lload=10μH Vcard = 0V to CVcc With Boost at 60%

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Notes: 1. Test conditions, Capacitor 10 μF, Inductance 10 μH. 2. Ceramic X7R, SMD type capacitor with minimum ESR or 250 m Ω is mandatory Notes: 1. The voltage on CLK should remain between -0.3V and VCC+0.3V during dynamic operation. Card VCC 1.8V Power Supply (for IEC7816-3 Class C cards) Symbol Parameter Min Typ Max Unit Test Conditions Vcc Power Supply 3.0 5.5 V CI CC_ovf Card Supply Current overflow 100 mA CVCC Card Supply Voltage 1.68 1.92 V CI CC = 35 mA TOFF CVcc to 0 750 μs Cload=10μF, Lload=10μH Vcard = CVcc to 0.4V TON 0 to CVcc 750 μs Cload=10μF, Lload=10μH Vcard = 0V to CVcc With Boost at 60% Smart Card CCLK, DC parameters Symbol Parameter Min Typ Max Unit Test Conditions VOL Output Low Voltage 0 (1) 0.4

0.15 CVCC

V IOH = 50 μA (5V until 2009) IOH = 100 μA (5V from 2009) IOH = 100 μA (3V & 1.8V) IOL Output Low Current 15 mA VOH Output High Voltage CVCC-0,5

0.8 CVCC

IOH = 50μA (+5V until 2009) IOH = 100 μA (+5V from 2009) IOH = 100 μA (+3V & 1.8V) IOH Output High Current 15 mA tR tF Rise and Fall delays 14.5 15.5 32 ns CIN=30pF (5V) CIN=30pF (3V) CIN=30pF (1.8V) Voltage Stability -0.25 CVCC-0.5

0.4 CVCC

CVCC + 0.25 V Low level High level Frequency variation (Jitter) 1% Cycle ratio 45% 55% Smart Card CIO, DC Parameters Symbol Parameter Min Typ Max Unit Test Conditions V IL Input Low Voltage 0 (1) 0.2 CVCC V IIL Input Low Current 500 μA VIH Input High Voltage 0.6 CV CC CVCC V IIH Input High Current -20 / +20 μA VOL Output Low Voltage 0 (1) 0.15 CVCC V IOL = 1mA (5V & 3V)) IOL = 0.5 mA (1.8V) External 10K pull-up tied to CVCC

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Note: 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation. Note: 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation. IOL Output Low Current 15 mA VOH Output High Voltage 0.8 CV CC CVCC (1) V IOH = 20 μA External 10K pull-up resistor tied to CVCC IOH Output High Current 15 mA Voltage Stability -0.25 0.4 CVCC + 0.25 V Low level High level tR tF Rise and Fall delays 0.8 μsC IN=30pF. Smart Card RST, I/O, DC Parameters Symbol Parameter Min Typ Max Unit Test Conditions VOL Output Low Voltage 0 (1) 0.4

0.12 CVCC

V IOL = 50 μΑ (5V until 2009) IOL = 200 μΑ (5V from 2009) IOL = 200 μΑ (3V & 1.8V) IOL Output Low Current 15 mA VOH Output High Voltage CVCC-05 CVCC (1) V IOH = 50 μΑ (+5V until 2009) IOH = 150 μΑ (+5V from 2009) IOH = 150 μΑ (+3V & 1.8V) IOH Output High Current 15 mA tR tF Rise and Fall delays 0.8 μsC IN=30 pF Voltage Stability -0.25 CVCC-0.5 CVCC + 0.25 Low level High level Smart Card CIO, DC Parameters Symbol Parameter Min Typ Max Unit Test Conditions Card Presence (P1.2) DC Parameters Symbol Parameter Min Typ Max Unit Test Conditions IOL1 CPRES weak pull-up output current 3 10 25 μA P1.2=1, short to VSS Pull-up enabled

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 USB Interface Figure 112. USB Interface Symbol Parameter Min Typ (5) Max Unit VREF USB Reference Voltage 3.0 3.6 V VIH Input High Voltage for D+ and D- (driven) 2.0 4.0 V VIHZ Input High Voltage for D+ and D- (floating) 2.7 3.6 V VIL Input Low Voltage for D+ and D- 0.8 V VOH Output High Voltage for D+ and D- 2.8 3.6 V VOL Output Low Voltage for D+ and D- 0.0 0.3 V

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The firs t character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The fo llowing is a list of all the characters and what they stand for. Example:T AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40°C to +85°C; VSS = 0V; VCC = 3.0V to 5.5V ; FCK_CPU = 0 to 24 MHz. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table and Table 118 give the description of each AC symbols. Table 117 and Table 120 give for each range the AC parameter. Table 115, Table 117 and Table 119 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use this value in the formula. Example: T LLIV and 20 MHz, Standard clock. x = 30 ns T = 50 ns T CCIV = 4T - x = 170 ns External Program Memory Characteristics Table 114. Symbol Description Symbol Parameter T CPU clock period (F CK_CPU) TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float

Table 115. AC Parameters for a Variable Clock

12 TCLCL

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 External Data Memory Characteristics Table 116. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high

Table 117. AC Parameters for a Variable Clock

Table 118. Symbol Description (F = 40 MHz) Table 119. AC Parameters for a Variable Clock

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Shift Register Timing Waveform External Clock Drive Characteristics (XTAL1) Table 120. AC Parameters External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at V CC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. VALID VALID VALID VALID VALIDVALIDINPUT DATA VALID 0123456 8 7 ALE CLOCK OUTPUT DATA WRITE to SBUF CLEAR RI TXLXL TQVXH TXHQX TXHDV TXHDX SET TI SET RI INSTRUCTION 01234567 VALID Symbol Parameter Min Max Units TCLCL Oscillator Period 125 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns TCHCX/TCLCX Cyclic ratio in X2 mode 40 60 % VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCLCH TCHCX INPUT/OUTPUT 0.2 VCC + 0.9 0.2 VCC - 0.1 VCC -0.5V 0.45V

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20 mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 FLOAT FLOAT FLOAT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION INDICATES ADDRESS TRANSITIONS EXTERNAL PROGRAM MEMORY FETCH FLOAT DATA SAMPLED DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL OLD DATANEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED RXD SAMPLED INTERNAL CLOCK XTAL2 ALE PSEN P2 (EXT) READ CYCLE WRITE CYCLE RD WR PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) DATA OUT DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperatur e and pin loading. Propagation also varies from output to output and component. Typically though (T A=25°C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. USB Interface Rise Time Fall Time VCRS Differential Data Lines 90% 10% 90% 10% tR tF VHmin VLmax Symbol Parameter Min Typ (5) Max Unit tR Rise Time 4 20 ns tF Fall Time 4 20 ns tFDRATE Full-speed Data Rate 11.9700 12.0300 Mb/s VCRS Crossover Voltage 1.3 2.0 V tDJ1 Source Jitter Total to next transaction -3.5 3.5 ns tDJ2 Source Jitter Total for paired transactions -4 4 ns tJR1 Receiver Jitter to next transaction -18.5 18.5 ns tJR2 Receiver Jitter for paired transactions -9 9 ns

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Packaging Information

Ordering Information

Note: 1. Check avaibility with sales office Lead free/ RoHS Part Number Lead free/ RoHS Internal Part Number Memory Size (bytes) Supply Voltage (V) Temperature Range Max Frequency (MHz) Package Packing AT83R5122xxx-RDTUM AT83R5122xxx-ALTUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray AT83R5122xxx-RDRUM AT83R5122xxx-ALRUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel AT83R5122xxx-PSTUM AT83R5122xxxZ1TUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry Pack AT83R5122xxx-PSRUM AT83R5122xxx-Z1RUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel & Dry Pack AT85C5122D-RDTUM AT85C5122D-ALTUM 32K CRAM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray AT85C5122D-RDRUM AT85C5122D-ALRUM 32K CRAM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel AT89C5122D-RDTUM AT89C5122D-ALTUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray & Dry pack AT89C5122D-RDRUM AT89C5122D-ALRUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel & Dry pack AT89C5122D-PSTUM AT89C5122D-Z1TUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry Pack AT89C5122D-PSRUM AT89C5122D-Z1RUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel & Dry Pack AT89C5122DS-RDTUM AT89C5122DS-ALTUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray & Dry Pack AT89C5122DS-RDRUM AT89C5122DS-ALRUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel & Dry Pack AT89C5122D-PSTUM AT89C5122D-Z1TUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry Pack AT89C5122D-PSRUM AT89C5122D-Z1RUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel & Dry Pack AT83C5123xxx-RATUM AT83C5123xxx-ALTUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tray AT83C5123xxx-RARUM AT83C5123xxx-ALRUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tape & Reel AT83C5123xxx-PUTUM AT83C5123xxx-Z1TUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN32 Tray AT83C5123xxx-PURUM AT83C5123xxx-Z1RUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN32 Tape & Reel

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Mechanical Dimensions

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008

AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Datasheet Revision History Changes from 4202A to 4202B 1. Product AT8xEC5122 added. 2. Products AT83C5123 and AT83EC5123 added. Changes from 4202B to 4202C 1. All sections updated. 2. QFN64 and QFN32 packages added. 3. SCIB section : VCC must be higher than 4.0V when DC/DC is operated at 5V. Changes from 4202C to 4202D 1. Product AT89C5122DS added (EA pin changed to VCC) 2. Typical applications section: external pull-up shown on CIO pin 3. Ports section : Detailed explanations on CIO, CC4, CC8 quasi-bidirectional ports 4. Ordering information section: AT89C5122DS part-numbers added Changes from 4202D to 4202E 1. Changed input voltage frequency from 3.6V to 3.0V throughout the document. 2. Update of DC parameters of smart card interface to be EMV 4.1 compliant. Changes from 4202E to 4202F 1. Product AT83EC5122 and AT83EC5123 removed. 2. Product AT83R5122 added. 3. Package PLCC28 not supported anymore. 4. Global update.

4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table of Contents USB Keyboard with Smart Card Reader Using AT83R5122, AT8xC5122/AT89C5122DS

4202F–SCR–07/2008 AT83R5122, AT8xC5122/23

4202F–SCR–07/2008 AT83R5122, AT8xC5122/23

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