AT88SC0808CA-MJ

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Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 23

Technical content

Features

• One of a family of devices with user memories from 1Kbit to 8Kbits
• 8Kbit (1Kbyte) EEPROM user memory
• Eight 1Kbit (128-byte) zones
• Self-timed write cycle
• Single byte or 16-byte page write mode
• Programmable access rights for each zone
• 2Kbit configuration zone
• 37-byte OTP (One-Time Programmable) area for user-defined codes
• 160-byte area for user-defined keys and passwords
• High security features
• 64-bit mutual authentication protocol (under license of ELVA)
• Cryptographic Message Authentication Codes (MAC)
• Stream encryption
• Four key sets for authentication and encryption
• Eight sets of two 24-bit passwords
• Anti-tearing function
• Voltage and frequency monitors
• Smart card features
• ISO 7816 Class B (3V) operation
• ISO 7816-3 asynchronous T=0 Protocol (Gemplus® Patent) *
• Multiple zones, key sets and passwords for multi-application use
• Synchronous two-wire serial interface for faster device initialization *
• Programmable 8-byte answer-to-reset register (ATR)
• ISO 7816-2 compliant modules
• Embedded application features
• Low voltage supply: 2.7V – 3.6V
• Secure nonvolatile storage for sensitive system or user information
• Two-wire serial interface (TWI, 5V compatible)
• 1.0MHz compatibility for fast operation
• Standard 8-lead plastic packages, green compliant (exceeds RoHS)
• Same pin configuration as Atmel® AT24CXXX Serial EEPROM in SOIC and PDIP packages
• High reliability
• Endurance: 100,000 cycles
• Data retention: 10 years
• ESD protection: 2,000V min * Note: Modules available with either T=0 / 2-wire modes or 2-wire mode only 5204FS −CRYPTO −12/11 This is a summary document. The complete document is available on the Atmel website at www.atmel.com.

Table 1. Pin Assignments Figure 1. Pin Configuration

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 1. Description The Atmel AT88SC0808CA member of the Atmel CryptoMemory® family is a high-performance secure memory providing 8Kbit of user memory with advanced security and cryptographic features built in. The user memory is divided into eight 128-byte zones, each of which may be individually set with different security access rights or effectively combined together to provide space for one to eight data files. The AT88SC0808CA features an enhanced command set that allows direct communication with microcontroller hardware two-wire interface thereby allowing for faster firmware development with reduced code space requirements.

1.1 Smart Card Applications

The AT88SC0808CA provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. The embedded cryptographic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to four unique key sets may be used for these operations. The AT88SC0808CA offers the ability to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO 7816-3.

1.2 Embedded Applications

Through dynamic, symmetric-mutual authentication, data encryption, and the use of cryptographic Message Authentication Codes (MAC), the AT88SC0808CA provides a secure place for storage of sensitive information within a system. With its tamper detection circuits, this information remains safe even under attack. A two-wire serial interface running at speeds up to 1.0MHz provides fast and efficient communications with up to 15 individually addressable devices. The AT88SC0808CA is available in industry standard 8-lead packages with the same familiar pin configuration as Atmel AT24CXXX Serial EEPROM devices. Note: Does not apply to either the TSSOP or the Ultra Thin Mini-Map pinouts Figure 1-1. Block Diagram Random Generator Authentication, Encryption and Certification Unit EEPROM Answer to Reset Data Transfer Password Verification Reset Block Asynchronous ISO Interface Synchronous Interface Power Management VCC GND SCL/CLK SDA/IO RST

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 2. Connection Diagram Figure 2-1. Connection Diagram 2.7v - 5.5v 2.7v - 3.6v SDA SCL Microprocessor CryptoMemory 3. Pin Descriptions

3.1 Supply Voltage (VCC)

The VCC input is a 2.7V to 3.6V positive voltage supplied by the host.

3.2 Clock (SCL/CLK)

When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/ f. When using the synchronous protocol, data clocking is done on the positive edge of the clock when writing to the device and on the negative edge of the clock when reading from the device.

3.3 Reset (RST)

The AT88SC0808CA provides an ISO 7816-3 compliant asynchronous answer-to-reset (ATR) sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64-bit ATR register. An internal pull-up on the RST input pad allows the device to operate in synchronous mode without bonding RST. The AT88SC0808CA does not support an ATR sequence in the synchronous mode of operation.

3.4 Serial Data (SDA/IO)

The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open-drain or open-collector devices. An external pull-up resistor should be connected between SDA/IO and VCC. The value of this resistor and the system capacitance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power supply current. SDA/IO information applies to both asynchronous and synchronous protocols.

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 4. *Absolute Maximum Ratings Voltage on any pin *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Table 4-1. DC Characteristics Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40°C to +85°C (unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Units VCC (1) Supply Voltage 2.7 3.6 V ICC Supply Current Async Read at 3.57MHz 5 mA ICC Supply Current Async Write at 3.57MHz 5 mA ICC Supply Current Synch Read at 1MHz 5 mA ICC Supply Current Synch Write at 1MHz 5 mA ISB Standby Current VIN = VCC or GND 100 µA VIL SDA/IO Input Low Voltage 0 VCC x 0.2 V VIL CLK Input Low Voltage 0 VCC x 0.2 V VIL RST Input Low Voltage 0 VCC x 0.2 V VIH (1) SDA/IO Input High Voltage VCC x 0.7 5.5 V VIH (1) SCL/CLK Input High Voltage VCC x 0.7 5.5 V VIH (1) RST Input High Voltage VCC x 0.7 5.5 V IIL SDA/IO Input Low Current 0 < VIL < VCC x 0.15 15 µA IIL SCL/CLK Input Low Current 0 < VIL < VCC x 0.15 15 µA IIL RST Input Low Current 0 < VIL < VCC x 0.15 50 µA IIH SDA/IO Input High Current VCC x 0.7 < VIH < VCC 20 µA IIH SCL/CLK Input High Current VCC x 0.7 < VIH < VCC 100 µA IIH RST Input High Current VCC x 0.7 < VIH < VCC 150 µA VOH SDA/IO Output High Voltage 20K ohm external pull-up VCC x 0.7 VCC V VOL SDA/IO Output Low Voltage IOL = 1mA 0 VCC x 0.15 V IOH SDA/IO Output High Current VOH 20 µA IOL SDA/IO Output Low Current VOL 10 mA Note: 1. To prevent latch up conditions from occurring during power up of the AT88SC0808CA, VCC must be turned on before applying VIH. For powering down, VIH must be removed before turning VCC off.

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 Table 4-2. AC Characteristics Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40°C to +85°C, CL = 30pF (unless otherwise noted) Symbol Parameter Min Max Units fCLK Async Clock Frequency 1 4 MHz fCLK Synch Clock Frequency 0 1 MHz Clock Duty cycle 40 60 % tR “Rise Time - SDA/IO, RST” 1 µS tF “Fall Time - SDA/IO, RST” 1 µS tR Rise Time - SCL/CLK 9% x period µS tF Fall Time - SCL/CLK 9% x period µS tAA Clock Low to Data Out Valid 250 nS tHD.STA Start Hold Time 200 nS tSU.STA Start Set-up Time 200 nS tHD.DAT Data In Hold Time 10 nS tSU.DAT Data In Set-up Time 100 nS tSU.STO Stop Set-up Time 200 nS tDH Data Out Hold Time 20 nS tWR Write Cycle Time 5 mS 5. Device Operations for Synchronous Protocols

5.1 Clock and Data Transitions

The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-3 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below.

5.1.1 Start condition

A high-to-low transition of SDA with SCL high defines a start condition which must precede all commands (see Figure 5-4 on page 8).

5.1.2 Stop condition

A low-to-high transition of SDA with SCL high defines a stop condition. After a read sequence, the stop condition will place the EEPROM in a standby power mode (see Figure 5-4 on page 8).

5.1.3 Acknowledge

All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle (see Figure 5-5 on page 8).

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

5.2 Memory Reset

After an interruption in communication due protocol errors, power loss or any reason, perform "Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of sending a start condition followed by a valid CryptoMemory command byte and determining if the device responded with an acknowledge. Figure 5-1. Bus Time for Two-wire Serial Communications SCL: Serial Clock, SDA: Serial Data I/O SCL SDA IN SDA OUT tF tHIGH tLOW tLOW tR tAA tDH tBUF Figure 5-2. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O twr (1) STOP CONDITION START CONDITION WORDn ACK8th BIT SCL SDA Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 6. Device Architecture

6.1 User Zones

The EEPROM user memory is divided into eight zones of 1Kbits each. Multiple zones allow for storage of different types of data or files in different zones. Access to user zones is permitted only after meeting proper security requirements. These security requirements are user definable in the configuration memory during device personalization. If the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. Figure 6-1. User Zones User 0 $00 - 128 bytes $78 User 1 User 8 $00 $78 User 2 $00 - 128 bytes $78 7. Control Logic Access to the user zones occur only through the control logic built into the device. This logic is configurable through access registers, key registers and keys programmed into the configuration memory during device personalization. Also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device.

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 8. Configuration Memory The configuration memory consists of 2048 bits of EEPROM memory used for storage of passwords, keys, codes, and also used for definition of security access rights for the user zones. Access rights to the configuration memory are defined in the control logic and are not alterable by the user after completion of personalization. Figure 8-1. Configuration Memory $00 Answer To Reset Identifitcation $08 Fab Code MTZ Card Manufacturer Code $10 Lot History Code Read Only $18 DCR Identification Number Nc Access Control $20 AR0 PR0 AR1 PR1 AR2 PR2 AR3 PR3 $28 AR4 PR4 AR5 PR5 AR6 PR6 AR7 PR7 $30 Reserved $38 $40 Issuer Code $48 $50 For Authentication and Encryption use Cryptography $58 $60 $68 $70 $78 $80 $88 $90 For Authentication and Encryption use Secret $98 $A0 $A8 $B0 PAC Write 0 PAC Read 0 Password $B8 PAC Write 1 PAC Read 1 $C0 PAC Write 2 PAC Read 2 $C8 PAC Write 3 PAC Read 3 $D0 PAC Write 4 PAC Read 4 $D8 PAC Write 5 PAC Read 5 $E0 PAC Write 6 PAC Read 6 $E8 PAC Write 7 PAC Read 7 $F0 Reserved Forbidden $F8

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 9. Security Fuses There are three fuses on the device that must be blown during the device personalization process. Each fuse locks certain portions of the configuration zone as OTP (One-Time Programmable) memory. Fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step. 10. Communication Security Modes Communications between the device and host operate in three basic modes. Standard mode is the default mode for the device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is activated by a successful encryption activation following a successful authentication. Table 10-1. Communication Security Modes(1) Mode Configuration Data User Data Passwords Data Integrity Check Standard Clear Clear Clear MDC(1) Authentication Clear Clear Encrypted MAC(1) Encryption Clear Encrypted Encrypted MAC(1) Note: 1. Configuration data include viewable areas of the configuration zone except the passwords:  MDC: Modification Detection Code  MAC: Message Authentication Code 11. Security Options

11.1 Anti-Tearing

In the event of a power loss during a write cycle, the integrity of the device’s stored data is recoverable. This function is optional: the host may choose to activate the anti-tearing function, depending on application requirements. When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data is limited to a maximum of eight bytes for each write request. Data is written first into a buffer zone in EEPROM instead of the intended destination address, but with the same access conditions. The data is then written in the required location. If this second write cycle is interrupted due to a power loss, the device will automatically recover the data from the system buffer zone at the next power-up. Non-volatile buffering of the data is done automatically by the device. During power-up in applications using anti-tearing, the host is required to perform ACK polling in the event that the device needs to carry out the data recovery process.

11.2 Write Lock

If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. Example: The write lock byte at $080 controls the bytes from $081 to $087 Figure 11-1. Write Lock Example $080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 The write lock byte itself may be locked by writing its least significant (rightmost) bit to “0”. Moreover, when write lock mode is activated, the write lock byte can only be programmed – that is, bits written to “0” cannot return to “1”. In the write lock configuration, write operations are limited to writing only one byte at a time. Attempts to write more than one byte will result in writing of just the first byte into the device.

11.3 Password Verification

Passwords may be used to protect read and/or write access of any user zone. When a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or RST becomes active. There are eight password sets that may be used to protect any user zone. Only one password is active at a time. Presenting the correct write password also grants read access privileges.

11.4 Authentication Protocol

The access to a user zone may be protected by an authentication protocol. Any one of four keys may be selected to use with a user zone. Authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or RST becomes active. If the new authentication request is not validated, the card loses its previous authentication which must be presented again to gain access. Only the latest request is memorized. Figure 11-2. Password and Authentication Operations Device (Card) Card Number VERIFY A COMPUTE Challenge B Challenge B VERIFY RPW DATA Checksum (CS) VERIFY WPW VERIFY CS Write DATA Host (Reader) COMPUTE Challenge A Challenge A VERIFY B Read Password (RPW) VERIFY CS Write Password (WPW) DATA CS AUTHENTICATION READ ACCESS WRITE ACCESS Note: Authentication and password verification may be attempted at any time and in any order. Exceeding corresponding authentication or password attempts trial limit renders subsequent authentication or password verification attempts futile.

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

11.5 Cryptographic Message Authentication Codes

AT88SC0808CA implements a data validity check function in the standard, authentication or encryption modes of operation. In the standard mode, data validity check is done through a Modification Detection Code (MDC), in which the host may read an MDC from the device in order to verify that the data sent was received correctly. In authentication and encryption modes, the data validity check becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capability in the form of a Message Authentication Codes (MAC). Only the host/device that carried out a valid authentication is capable of computing a valid MAC. While operating in the authentication or encryption modes, the use of MAC is required. For an ingoing command, if the device calculates a MAC different from the MAC transmitted by the host, not only is the command abandoned but the security privilege is revoked. A new authentication and/or encryption activation will be required to reactivate the MAC.

11.6 Encryption

The data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. The issuer may choose to require encryption for a user zone by settings made in the configuration memory. Any one of four keys may be selected for use with a user zone. In this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. Even if not required, the host may still elect to activate encryption provided the proper keys are known.

11.7 Supervisor Mode

Enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords.

11.8 Modify Forbidden

No write access is allowed in a user zone protected with this feature at any time. The user zone must be written during device personalization prior to blowing the security fuses.

11.9 Program Only

For a user zones protected by this feature, data can only be programmed (bits change from a “1” to a “0”), but not erased (bits change from a “0” to a “1”).

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 12. Protocol Selection The AT88SC0808CA supports two different communication protocols.

• Smartcard Applications: Smartcard applications use ISO 7816- B protocol in asynchronous T = 0 mode for compatibility and interoperability with industry standard smartcard readers.
• Embedded Applications: A two-wire serial interface provides fast and efficient connectivity with other logic devices or microcontrollers. The power-up sequence determines establishes the com munication protocol for use within that power cycle. Protocol selection is allowed only during power -up.

12.1 Synchronous Two-wire Serial Interface

The synchronous mode is the default mode after power up. This is due to the presence of an internal pull-up on RST. For embedded applications using CryptoMemory in standard plastic packages, this is the only available communication protocol.

• Power-up VCC, RST goes high also
• After stable V CC, SCL(CLK) and SDA(I/O) may be driven
• Once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering off the device Figure 12-1. Synchronous Two-wire Protocol Vcc I/O-SDA RST CLK-SCL 1 2 3 4 5 Note: Five clock pulses must be sent before the first command is issued.

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

12.2 Asynchronous T = 0 Protocol

This power-up sequence complies to ISO 7816-3 for a cold reset in smart card applications.

• VCC goes high; RST, I/O (SDA) and CLK (SCL) are low
• Set I/O (SDA) in receive mode
• Provide a clock signal to CLK (SCL)
• RST goes high after 400 clock cycles The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the CryptoMemory family. Once asynchronous mode has been selected, it is not possible to switch to synchronous mode without first powering off the device. Figure 12-2. Asynchronous T = 0 Protocol (Gemplus Patent) Vcc I/O-SDA RST CLK-SCL ATR 13. Initial Device Programming Enabling the security features of CryptoMemory requires prior personalization. Personalization entails setting up of desired access rights by zones, passwords and key values, programming these values into the configuration memory with verification using simple write and read commands, and then blowing fuses to lock this information in place. Gaining access to the configuration memory requires successful presentation of a secure (or transport) code. The initial signature of the secure (transport) code for the AT88SC0808CA device is $22 E8 3F. This is the same as the Write 7 password. The user may elect to change the signature of the secure code anytime after successful presentation. After writing and verifying data in the configuration memory, the security fuses must be blown to lock this information in the device. For additional information on personalizing CryptoMemory, please see the application notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications from the product page at www.atmel.com/products/securemem.

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 14. Ordering Information Atmel Ordering Code Package Voltage Range Temperature Range AT88SC0808CA-MJ AT88SC0808CA-MP AT88SC0808CA-MJTG AT88SC0808CA-MPTG M2 – J Module- ISO M2 – P Module- ISO M2 – J Module -TWI M2 – P Module -TWI 2.7V–3.6V Commercial (0°C to 70°C) AT88SC0808CA-PU AT88SC0808CA-SH AT88SC0808CA-TH AT88SC0808CA-Y6H-T 8P3 8S1 8A2 8Y6 2.7V–3.6V Green compliant (exceeds RoHS) / Industrial(−40°C to 85°C) AT88SC0808CA-WI 7 mil wafer 2.7V–3.6V Industrial (−40°C to 85°C) Package Type(1) (2) Description M2 – J Module: ISO or TWI M2 ISO 7816 smart card module M2 – P Module: ISO or TWI M2 ISO 7816 smart card module with Atmel® logo 8P3 8-lead, 0.300” wide, Plastic Dual Inline (PDIP) 8S1 8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP) 8MA2 8-lead, 2.0 x 3.0mm body, 0.50mm pitch, Ultra Thin Mini-Map, Dual No Lead (DFN), (MLP 2x3) Note: 1. Formal drawings may be obtained from an Atmel sales office 2. Both the J and P module packages are used for either ISO (T=0 / 2-wire mode) or TWI (2-wire mode only)

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 15. Package Information Ordering Code: MJ or MJTG Ordering Code: MP or MPTG Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Round - ∅ 8.5 [mm] Thickness: 0.58 [mm] Pitch: 14.25mm Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square - 8.8 x 8.8 [mm] Thickness: 0.58 [mm] Pitch: 14.25mm Note: *The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4mm greater in both directions

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

15.1 Ordering Code: SH

8S1 – 8-lead SOIC Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV.TITLE GPC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 0° – 8° Ø E N TOP VIEW C END VIEW A b L e D SIDE VIEW 8S1 G 6/22/11 Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) SWB

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

15.2 Ordering Code: PU

8P3 – 8-lead PDIP Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV.TITLE GPC Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c

4 PLCS

A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0. 115 0.130 0.150 2 Top View Side View End View 8P3 D 06/21/11 8P3, 8-lead, 0.300” Wide Body, Plastic Dual In-line Package (PDIP) PTC

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

15.3 Ordering Code: TH

8X – 8-lead TSSOP Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV.TITLE GPC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF C 0.09 - 0.20 Side View End ViewTop View A L D N b Pin 1 indicator this corner E e Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8X D 6/22/11 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) TNR C

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11

15.4 Ordering Code: Y6H-T

8MA2 – 8-lead Ultra Thin Mini-Map TITLE DRAWING NO.GPC REV. Package Drawing Contact: packagedrawings@atmel.com 8MA2YNZ B 8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 E2 1.20 1.30 1.40 A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 – – 0.55 C 0.152 REF L 0.30 0.35 0.40 e 0.50 BSC b 0.18 0.25 0.30 3 K 0.20 – – 7/15/11 E e (6x) L (8x) b (8x) Pin#1 ID A Pin 1 ID D C K

Atmel AT88SC0808CA [Summary DATASHEET] 5204FS−CRYPTO−12/11 16. Revision History Doc. Rev. Date Comments 5204FS 12/2011 Update Template Update package drawings and - Replace 8A2 with 8X - Replace 8Y6 with 8MA2 Change AT88SC0808CA-SU to AT88SC0808CA-SH 5204ES 07/2009 Minor edits and TWI module update 5204DS 07/2009 Minor updates to package drawing information and ordering information. 5204CS 05/2009 Added Mini-MAP column to Table 1-1 and Mini-MAP pin-out drawing. 5204BS 02/2009 Connection Diagram inserted; DC Characteristics table updated. 5204AS 07/2008 Initial document release.

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