TSC80251G2D ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 76

Technical content

Features

  • Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/Rx/Rx+
  • Plug-In Replacement of Intel’s 8xC251Sx
  • C251 Core: Intel’s MCS®251 D-step Compliance
  • 40-byte Register File
  • Registers Accessible as Bytes, Words or Dwords
  • Three-stage Instruction Pipeline
  • 16-bit Internal Code Fetch
  • Enriched C51 Instruction Set
  • 16-bit and 32-bit ALU
  • Compare and Conditional Jump Instructions
  • Expanded Set of Move Instructions
  • Linear Addressing
  • 1 Kbyte of On-Chip RAM
  • External Memory Space (Code/Data) Programmable from 64 kilobytes to 256 kilobytes
  • TSC87251G2D: 32 kilobytes of On-Chip EPROM/OTPROM – SINGLE PULSE Prog ramming Algorithm
  • TSC83251G1D: 16 kilobytes of On-Chip Masked ROM
  • TSC83251G1D: 32 kilobytes of On-Chip Masked ROM
  • TSC80251G1D: ROMless Version
  • Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of the Standard 80C51)
  • Serial I/O Port: Full Duplex UART (80C51 Compatible) With Independent Baud Rate Generator
  • SSLC: Synchronous Serial Link Controller
  • TWI Multi-master Protocol
  • μWire and SPI Master and Slave Protocols
  • Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the Standard 80C51)
  • EWC: Event and Waveform Controller
  • Compatible with Intel’s Programmable Counter Array (PCA)
  • Common 16-bit Timer/Counter Reference with Four Possible Clock Sources (Fosc/4, Fosc/12, Timer 1 and External Input)
  • Five Modules, Each with Four Programmable Modes: – 16-bit Software Timer/Counter – 16-bit Timer/Counter Capture Input and Software Pulse Measurement – High-speed Output and 16-bit Software Pulse Width Modulation (PWM) – 8-bit Hardware PWM Without Overhead
  • 16-bit Watchdog Timer/Counter Capability
  • Secure 14-bit Hardware Watchdog Timer
  • Power Management
  • Power-On Reset (Integrated on the Chip)
  • Power-Off Flag (Cold and Warm Resets)
  • Software Programmable System Clock
  • Idle Mode
  • Power-down Mode
  • Keyboard Interrupt Interface on Port 1
  • Non Maskable Interrupt Input (NMI)
  • Real-Time Wait States Inputs (WAIT#/AWAIT#)
  • ONCE Mode and Full Speed Real-time In-circuit Emulation Support (Third Party Vendors)
  • High Speed Versions: – 4.5V to 5.5V – 16 MHz and 24 MHz
  • Typical Operating Current: 35 mA at 24 MHz 24 mA at 16 MHz
  • Typical Power-down Current: 2 μA
  • Low Voltage Version: – 2.7V to 5.5V – 16 MHz 8/16-bit Microcontroller with Serial Communication Interfaces TSC80251G2D TSC83251G2D TSC87251G2D AT80251G2D AT83251G2D AT87251G2D

4135D–8051–08/05

  • Typical Operating Current:11 mA at 3V
  • Typical Power-down Current: 1 μA
  • Temperature Ranges: Commercial (0°C to +70°C), Industrial (-40°C to +85°C)
  • Option: Extended Range (-55°C to +125°C)
  • Packages: PDIL 40, PLCC 44 and VQFP 44, CDIL 40 and CQPJ 44 with Window
  • Options: Known Good Dice and Ceramic Packages

Description

The TSC80251G2D products are derivatives of the Atmel Microcontroller family based on the 8/16-bit C251 Architecture. This family of products is tailored to 8/16-bit microcontro ller applications requiring an in creased instruction throughput, a reduced operating frequency or a larger addressable memory spac e. The architecture can pr ovide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines. The TSC80251G2D derivatives are pin and software compat ible with standard 80C51/Fx/Rx/Rx+ with extended on-chip data memory (1 Kbyte RAM) and up to 256 kilobytes of exte rnal code and data. Additionally, the TSC83251G2D and TSC87251G2D provide on-chip code memory: 32 kilobytes ROM and 32 kilobytes EPROM/OTPROM respectively. They provide transparent enhancements to Intel’s 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting TWI, μWire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for UART, and Power Management features. TSC80251G2D derivatives are optimized for speed and for low power consumption on a wide voltage range. Note: 1. This Datasheet provides the technical description of th e TSC80251G2D derivatives. For further information on the device usage, please request the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide and errata sheet. Typical Applications • ISDN Terminals

  • High-Speed Modems
  • PABX (SOHO)
  • L i n e C a r d s
  • DVD ROM and Players
  • Printers
  • P l o t t e r s
  • Scanners
  • Banking Machines
  • Barcode Readers
  • Smart Cards Readers
  • High-End Digital Monitors
  • High-End Joysticks
  • High-end TV’s

4135D–8051–08/05 Block Diagram 16-bit Memory Code 16-bit Memory Address 16-bit Instruction Bus 24-bit Program Counter Bus 8-bit Data Bus 24-bit Data Address Bus 8-bit Internal Bus Peripheral Interface Unit VDD VSS VSS1 P3(A16) P1(A17)P2(A15-8) P0(AD7-0) RST XTAL2 XTAL1 NMI EA#/VPP ALE/PROG# PSEN# Timers 0, 1 and 2 Event and Waveform Controller TWI/SPI/mWire Controller Watchdog Timer Power Management Clock Unit Clock System Prescaler Keyboard Interface Bus Interface Unit CPU PORTS 0-3 Interrupt Handler Unit RAM

1 Kbyte

AWAIT# EPROM OTPROM 32 KB VSS2

Figure 2. TSC80251G2D 44-pin PLCC Package

Figure 3. TSC80251G2D 44-pin VQFP Package

Table 1. TSC80251G2D Pin Assignment

Table 2. Product Name Signal Description byte (see Table 13, Page 20). byte (see Table 13, Page 20). latch can use ALE to demultiplex the address from address/data bus. compatibility or power consumption increase (on-chip pull-up). Not available on DIP package. the PCA compare and PWM modes. EA# directs program memory accesses to on-chip or off-chip code memory. For EA# = 0, all program memory accesses are off-chip. For devices without ROM on-chip, EA# must be strapped to ground. When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#.

Holding this pin high for 24 oscillator periods triggers an interrupt. consumption increase (on-chip pull-down). Not available on DIP package. interrupt capability for a keyboard interface. and RD1 in UCONFIG0 byte (see ). bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20). IH1 is applied, whether or not the oscillator is running. reset by connecting a capacitor between this pin and VDD. the chip to normal operation. serial I/O modes 1, 2 and 3. clock from the master controller. When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in slave mode, SCK receives clock from the master controller. Table 2. Product Name Signal Description (Continued)

clock-out mode, T2 is the clock output. count direction: 1 = up, 0 = down. supply bypassing. Connection of this pin to ground is recommended. 8xC51 product, VSS1 can be unconnected without loss of compatibility. Not available on DIP package. supply bypassing. Connection of this pin to ground is recommended. 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. with a period of one half the oscillator frequency. pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing.

pin. If an external oscillator is used, leave XTAL2 unconnected.

  • On-chip ROM program/code memory (not present in ROMless devices)
  • On-chip RAM data memory
  • Special Function Registers (SFRs)
  • Configuration array Program/Code Memory The TSC83251G2D and TSC87251G2D implement 32 KB of on-chip program/code memory. Figure 4 shows the split of the internal and external program/code memory spaces. If EA# is tied to a high level, th e 32-Kbyte on-chip program memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The rest of the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the TSC87251G2D products provide it in an EPROM memory. For the TSC80251G2D products, there is no internal program/code memory and EA# must be tied to a low level.

Figure 4. Program/Code Memory Mapping

32 KBEA# = 0 EA# = 1

from its going into the reserved area). are redirected to the external memory. Figure 5. Data Memory Mapping

categories detailed in Table 1 to Table 9. SFRs are bit-addressable using the C251 instruction set. Table 1. C251 Core SFRs Table 2. I/O Port SFRs Table 3. Timers SFRs

Table 4. Serial I/O Port SFRs Table 5. SSLC SFRs Table 6. Event Waveform Control SFRs

Table 7. System Management SFRs Table 8. Interrupt SFRs Table 9. Keyboard Interface SFRs

Notes: 1. These registers are described in the TSC8 0251 Programmer’s Guide (C251 core registers).

  1. In TWI and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in TWI mode and
  2. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000

Table 10. SFR Descriptions

4135D–8051–08/05 Configuration Bytes The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device reset. These features fall into the following categories:

  • external memory interface (Page mode, address bits, programmed wait states and the address range for RD#, WR#, and PSEN#)
  • source mode/binary mode opcodes
  • selection of bytes stored on the stack by an interrupt
  • mapping of the upper portion of on-chip code memory to region 00: Two user configuration by tes UCONFIG0 (see Table 11) and UCONFIG1 (see Table 12) provide the information. When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G2D derivatives reserve the top eight bytes of the mem- ory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h. For the mask ROM devices, configuration info rmation is stored in on-chip memory (see ROM Verifying). When EA# is tied to a hi gh level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory.

Table 11. Configuration Byte 0 used, otherwise the subsequent fetches are performed in Non-Page mode.

  1. This selection provides compatibility with the standard 80C51 hardware which is mul-

tiplexing the address LSB and the data on Port 0. Set this bit when writing to UCONFIG0.

6 WSA1# Wait State A bits

memory accesses (all regions except 01:).

5 WSA0#

4 XALE#

Set to minimize the duration of the ALE pulse to 1·TOSC.

3 RD1 Memory Signal Select bits

1 PAGE#

Clear to select the binary mode. Set to select the source mode.

Table 12. Configuration Byte 1 Notes: 1. The CSIZE is only available on EPROM/OTPROM products.

  1. Two or four bytes are transparently p opped according to INTR when using the RETI
  2. Use only for Step A compatibility; set this bit when WSB1:0# are used.

Set to select 32 KB of on-chip code memory (TSC87251G2D product). Set this bit when writing to UCONFIG1. Set this bit when writing to UCONFIG1. Set this bit when writing to UCONFIG1. of the PC register and the PSW1 register). Clear to generate one wait state for memory region 01:. Set for no wait states for memory region 01:.

2 WSB1# Wait State B bits

external memory accesses (only region 01:).

1 WSB0#

0 EMAP#

FF:7FFFh) to the data space (at 00:C000h-00:FFFFh). FF:7FFFh) to the data space.

4135D–8051–08/05 Configuration Byte 1 Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals Notes: 1. This selection provides compatibili ty with the standard 80C51 hardware which has separate external memory spaces for data and code. RD1 RD0 P1.7 P3.7/RD# PSEN# WR# External Memory

00 A 1 7 A 1 6

regions 00: and 01: Read signal for regions FE: and FF: Write signal for all external memory locations 2 × 64 KB (1)

  • Instruction Fetch
  • Instruction Execution Table 20 to Table 32 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and this is never limiting the execution speed. If the code is fetched from external memo ry, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. However, the effective s peed may be limited depending on the average size of instructions (for the considered section of the program flow). The maximum aver- age instruction throughput is provided by Table 14 depending on the external memory configuration (from Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values.

Table 14. Minimum Number of States per Instruction for given Average Sizes tion speed but only the actual code execution can provide the final value. Table 15 to Table 19 provide notation for Instruction Operands. Table 15. Notation for Direct Addressing

0 Wait

1 Wait

depending on the other operand.

Table 16. Notation for Immediate Addressing Table 17. Notation for Bit Addressing Table 18. Notation for Destination in Control Instructions

Table 19. Notation for Register Operands

Table 20. Summary of Add and Subtract Instructions Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

  1. If this instruction addresses external me mory location, add N+2 to the number of

states (N: number of wait states).

  1. If this instruction addresses external me mory location, add 2(N+2) to the number of

states (N: number of wait states). Table 21. Summary of Increment and Decrement Instructions Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.

Add 3 if it addresses a Peripheral SFR.

Table 22. Summary of Compare Instructions Notes: 1. If this instruction addr esses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.

  1. If this instruction addresses external me mory location, add N+2 to the number of

states (N: number of wait states).

  1. If this instruction addresses external me mory location, add 2(N+2) to the number of

states (N: number of wait states).

4135D–8051–08/05 Logical AND(1)ANL <dest>, <src>dest opnd ← dest opnd Λ src opnd Logical OR(1)ORL <dest>, <src>dest opnd ← dest opnd ς src opnd Logical Exclusive OR(1)XRL <dest>, <src>dest opnd ← dest opnd ∀ src opnd Clear(1)CLR A(A) ← 0 Complement(1)CPL A(A) ← ∅ (A) Rotate LeftRL A(A)n+1 ← (A)n, n = 0..6 (A)0 ← (A)7 Rotate Left CarryRLC A(A)n+1 ← (A)n, n = 0..6 (CY) ← (A)7 (A)0 ← (CY) Rotate RightRR A(A)n-1 ← (A)n, n = 7..1 (A)7 ← (A)0 Rotate Right CarryRRC A(A)n-1 ← (A)n, n = 7..1 (CY) ← (A)0 (A)7 ← (CY) Mnemonic <dest>, <src> (1) Comments Binary Mode Source Mode Bytes States Bytes States ANL ORL XRL A, Rn register to ACC 1 1 2 2 A, dir8 Direct address (on-chip RAM or SFR) to ACC 2 1 (3) 21 (3) A, at Ri Indirect address to ACC 1 2 2 3 A, #data Immediate data to ACC 2 1 2 1 dir8, A ACC to direct address 2 2 (4) 22 (4) dir8, #data Immediate 8-bit data to direct address 3 3 (4) 33 (4) Rmd, Rms Byte register to byte register 3 2 2 1 WRjd, WRjs Word register to word register 3 3 2 2 Rm, #data Immediate 8-bit data to byte register 4 3 3 2 WRj, #data16 Immediate 16-bit data to word register 5 4 4 3 Rm, dir8 Direct address (on-chip RAM or SFR) to byte register 43 (3) 32 (3) WRj, dir8 Direct address (on-chip RAM or SFR) to word register 44 3 3 Rm, dir16 Direct address (64K) to byte register 5 3 (5) 42 (5) WRj, dir16 Direct address (64K) to word register 5 4 (6) 43 (6) Rm, at WRj Indirect address (64K) to byte register 4 3 (5) 32 (5) Rm, at DRk Indirect address (16M) to byte register 4 4 (5) 33 (5) CLR A Clear ACC 1 1 1 1 CPL A Complement ACC 1 1 1 1 RL A Rotate ACC left 1 1 1 1 RLC A Rotate ACC left through CY 1 1 1 1 RR A Rotate ACC right 1 1 1 1 RRC A Rotate ACC right through CY 1 1 1 1

Notes: 1. Logical instructions that affect a bit are in Table 27.

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  3. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
  4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
  5. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 23. Summary of Logical Instructions (2/2) Note: 1. A shaded cell denotes an instruction in the C51 Architecture.

Table 24. Summary of Multiply, Divide and Decimal-adjust Instructions Note: 1. A shaded cell denotes an instruction in the C51 Architecture.

Table 25. Summary of Move Instructions (1/3) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. Extended memory addressed is in the r egion specified by DPXL (reset value = 01h).
  2. If this instruction addresses external me mory location, add N+1 to the number of

states (N: number of wait states).

  1. If this instruction addresses external me mory location, add N+2 to the number of

states (N: number of wait states).

Table 26. Summary of Move Instructions (2/3) Notes: 1. Instructions that move bits are in Table 27.

  1. Move instructions from the C51 Architecture.
  2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

  1. Apply note 3 for each dir8 operand.

4135D–8051–08/05 Move(1)MOV <dest>, <src>dest opnd ← src opnd Mnemonic <dest>, <src> (1) Comments Binary Mode Source Mode Bytes States Bytes States MOV Rmd, Rms Byte register to byte register 3 2 2 1 MOV WRjd, WRjs Word register to word register 3 2 2 1 MOV DRkd, DRks Dword register to dword register 3 3 2 2 MOV Rm, #data Immediate 8-bit data to byte register 4 3 3 2 MOV WRj, #data16 Immediate 16-bit data to word register 5 3 4 2 MOV DRk, #0data16 zero-ext 16bit immediate data to dword register 5 5 4 4 MOV DRk, #1data16 one-ext 16bit immediate data to dword register 5 5 4 4 MOV Rm, dir8 Direct address (on-chip RAM or SFR) to byte register 4 3 (3) 32 (3) MOV WRj, dir8 Direct address (on-chip RAM or SFR) to word register 4 4 3 3 MOV DRk, dir8 Direct address (on-chip RAM or SFR) to dword register 4 6 3 5 MOV Rm, dir16 Direct address (64K) to byte register 5 3 (4) 42 (4) MOV WRj, dir16 Direct address (64K) to word register 5 4 (5) 43 (5) MOV DRk, dir16 Direct address (64K) to dword register 5 6 (6) 45 (6) MOV Rm, at WRj Indirect address (64K) to byte register 4 3 (4) 32 (4) MOV Rm, at DRk Indirect address (16M) to byte register 4 4 (4) 33 (4) MOV WRjd, at WRjs Indirect address (64K) to word register 4 4 (5) 33 (5) MOV WRj, at DRk Indirect address (16M) to word register 4 5 (5) 34 (5) MOV dir8, Rm Byte register to direct address (on-chip RAM or SFR) 4 4 (3) 33 (3) MOV dir8, WRj Word register to direct address (on-chip RAM or SFR) 4 5 3 4 MOV dir8, DRk Dword register to direct address (on-chip RAM or SFR) 4 7 3 6 MOV dir16, Rm Byte register to direct address (64K) 5 4 (4) 43 (4) MOV dir16, WRj Word register to direct address (64K) 5 5 (5) 44 (5) MOV dir16, DRk Dword register to direct address (64K) 5 7 (6) 46 (6) MOV at WRj, Rm Byte register to indirect address (64K) 4 4 (4) 33 (4) MOV at DRk, Rm Byte register to indirect address (16M) 4 5 (4) 34 (4) MOV at WRjd, WRjs Word register to indirect address (64K) 4 5 (5) 34 (5) MOV at DRk, WRj Word register to indirect address (16M) 4 6 (5) 35 (5) MOV Rm, at WRj +dis16 Indirect with 16-bit displacement (64K) to byte register 5 6 (4) 45 (4) MOV WRj, at WRj +dis16 Indirect with 16-bit displacement (64K) to word register 5 7 (5) 46 (5) MOV Rm, at DRk +dis24 Indirect with 16-bit displacement (16M) to byte register 5 7 (4) 46 (4)

4135D–8051–08/05 Notes: 1. Instructions that move bits are in Table 27. 2. Move instructions unique to the C251 Architecture. 3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states). MOV WRj, at WRj +dis24 Indirect with 16-bit displacement (16M) to word register 5 8 (5) 47 (5) MOV at WRj +dis16, Rm Byte register to indirect with 16-bit displacement (64K) 5 6 (4) 45 (4) MOV at WRj +dis16, WRj Word register to indirect with 16-bit displacement (64K) 5 7 (5) 46 (5) MOV at DRk +dis24, Rm Byte register to indirect with 16-bit displacement (16M) 5 7 (4) 46 (4) MOV at DRk +dis24, WRj Word register to indirect with 16-bit displacement (16M) 5 8 (5) 47 (5)

Table 27. Summary of Bit Instructions Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.

Add 3 if it addresses a Peripheral SFR.

Table 28. Summary of Exchange, Push and Pop Instructions Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.

Add 3 if it addresses a Peripheral SFR.

Table 29. Summary of Conditional Jump Instructions (1/2) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. States are given as jump not-taken/taken.
  2. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-

tination address is internal and odd.

Table 30. Summary of Conditional Jump Instructions (2/2) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. States are given as jump not-taken/taken.
  2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.

Add 3 if it addresses a Peripheral SFR.

  1. If this instruction addresses an I/O Port (Px, x = 0-3), add 3 to the number of states.

Add 5 if it addresses a Peripheral SFR.

  1. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-

tination address is internal and odd. Table 31. Summary of Unconditional Jump Instructions Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. In internal execution only, add 1 to the nu mber of states if the destination address is
  2. Add 2 to the number of states if the destination address is external.
  3. Add 3 to the number of states if the destination address is external.

Table 32. Summary of Call and Return Instructions Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

  1. In internal execution only, add 1 to the number of states if the destination/return

address is internal and odd.

  1. Add 2 to the number of states if the destination address is external.
  2. Add 5 to the number of states if INTR = 1.

4135D–8051–08/05 Programming and Verifying Non-volatile Memory Internal Features The internal non-volatile memory of the TS C80251G2D derivatives contains five differ- ent areas:

  • Code Memory
  • Configuration Bytes
  • L o c k B i t s
  • Encryption Array
  • Signature Bytes EPROM/OTPROM Devices All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D prod- ucts is made of EPROM cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM. The TSC87251G2D products are programmed and verified in the same manner as Atmel’s TSC87251G1A, using a SINGLE-PULSE algorithm, which programs at V PP = 12.75V using only one 100µs pulse per byte. This results in a programming time of less than 10 seconds for the 32 kilobytes on-chip code memory. The EPROM of the TSC87251G2D products in Window package is erasable by Ultra- Violet radiation(1) (UV). UV erasure set all the EPROM memory cells to one and allows reprogramming. The quartz window must be covered with an opaque label (2) when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as to protect the RAM and other on-c hip logic. Allowing light to impinge on the silicon die during device operation may cause a logical malfunction. The TSC87251G2D products in plastic pa ckages are One Time Programmable (OTP). An EPROM cell cannot be reset by UV once programmed to zero. Notes: 1. The recommended erasure procedure is ex posure to ultra-violet light (at 2537 Å) to an integrated dose of at least 20 W-sec/cm 2. Exposing the EPROM to an ultra-violet lamp of 12000 µW/cm2 rating for 30 minutes should be sufficient. 2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000 Å. Since sunlight and fluor escent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. Mask ROM Devices All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM cells. They can only be verified by the us er, using the same algorithm as the EPROM/OTPROM devices. ROMless Devices The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array. They only includ e Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the EPROM/OTPROM devices. Security Features In some microcontroller applications, it is desirable that the user’s program code be secured from unauthorized access. The TSC83251G2D and TSC87251G2D offer two kinds of protection for program code stored in the on-chip array:
  • Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array isprogrammed.
  • A three-level lock bit system restricts ex ternal access to the on-chip code memory.

Level 0 is the level of an erased part and does not enable any security features. Bytes and the Encryption Array. Level 3 locks the external execution. Table 33. Lock Bits Programming Notes: 1. Returns encrypted data if Encryption Array is programmed.

  1. Returns non encrypted data.
  2. x means don’t care. Level 2 always enables level 1, and level 3 always enables levels

The security level may be verified according to Table 34. Table 34. Lock Bits Verifying Note: 1. x means don’t care. all 1s), the user program code is placed on the data bus in its original, unencrypted form. encrypted and cannot be used without knowledge of the key byte sequence.

always be set when encryption is used.

  1. If the encryption feature is implemented, the portion of the on-chip code memory that

the encryption key sequence from being revealed. values are listed in Table 35. Table 35. Signature Bytes (Electronic ID)

  • The chip has to be put under reset and maintained in this state until completion of the programming sequence.
  • PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
  • Then PSEN# has to be to forced to a low le vel after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence (see below).
  • The voltage on the EA# pin must be set to V DD.
  • The programming mode is selected according to the code applied on Port 0 (see Table 36). It has to be applied until the completion of this programming operation.
  • The programming address is applied on Po rts 1 and 3 which are respectively the Most Significant Byte (MSB) and the Least Significant Byte (LSB) of the address.
  • The programming data are applied on Port 2.
  • The EPROM Programming is done by raising the voltage on the EA# pin to V PP, then by generating a low level pulse on ALE/PROG# pin.
  • The voltage on the EA# pin must be lowered to V DD before completing the programming operation.
  • It is possible to alternate programming and verifying operation (See Paragraph Verify Algorithm). Please make sure the voltage on the EA# pin has actually been lowered to V DD before performing the verifying operation. Signature Address Signature Data Vendor Atmel 30h 58h Architecture C251 31h 40h Memory 32 kilobytes EPROM or OTPROM 60h F7h 32 kilobytes MaskROM or ROMless 77h derivative 61h FDh
  • PSEN# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations.

Figure 6. Setup for Programming Table 36. Programming Modes Notes: 1. Signature Bytes are not user-programmable.

  1. The ALE/PROG# pulse waveform is shown in Figure 23 page 59.
  • The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
  • PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
  • Then PSEN# has to be to forced to a low le vel after two clock cycles or more and it has to be maintained in this state until the completion of the verifying sequence (see below).
  • The voltage on the EA# pin must be set to V DD and ALE must be set to a high level.
  • The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion of this verifying operation.
  • The verifying address is applied on Port s 1 and 3 which are respectively the MSB and the LSB of the address. ROM Area(1) RST EA#/VPP PSEN # ALE/PROG# (2) P0 P2 P1(MSB) P3(LSB) On-chip Code Memory 1V PP 01 P u l s e 6 8 h D a t a 16-bit Address 0000h-7FFFh (32 kilobytes) Configuration Bytes 1V PP 01 P u l s e 6 9 h D a t a CONFIG0: FFF8h CONFIG1: FFF9h Lock Bits 1 V PP 0 1 Pulse 6Bh X LB0: 0001h LB1: 0002h LB2: 0003h Encryption Array 1 V PP 0 1 Pulse 6Ch Data 0000h-007Fh VDD PSEN# ALE/PROG# EA#/VPP XTAL1 VDD 4 to 12 MHz RST VPP 100 ms pulses VSS/VSS1/VSS2 Mode VDD A[7:0] A[14:8] Data P0[7:0] P3[7:0] P1[7:0] P2[7:0] TSC87251G2D
  • Then device is driving the data on Port 2.
  • It is possible to alternate programming and verification operation (see Paragraph Programming Algorithm). Please make sure the voltage on the EA# pin has actually been lowered to VDD before performing the verifying operation.
  • PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a sequence of programming and verifying operations.

Table 37. Verifying Modes Figure 7. Setup for Verifying

4135D–8051–08/05 AC Characteristics - Commercial & Industrial AC Characteristics - External Bus Cycles Definition of Symbols Table 38. External Bus Cycles Timing Symbol Definitions Timings Test conditions: capacitive load on all pins = 50 pF. Table 39 and Table 40 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External wait stat es can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states. Figure 8 to Figure 13 show the bus cycles with the timing parameters. Signals Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD#/PSEN# Z Floating WW R #

Table 39. Bus Cycles AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to 85°C Notes: 1. Specification for PSEN# ar e identical to those for RD#.

  1. If a wait state is added by extending ALE, add 2·TOSC.
  2. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).

12 MHz 16 MHz 24 MHz

Table 40. Bus Cycles AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C Notes: 1. Specification for PSEN# ar e identical to those for RD#.

  1. If a wait state is added by extending ALE, add 2·TOSC.
  2. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).

12 MHz 16 MHz

Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40. Figure 9. External Bus Cycle: Data Read (Non-Page Mode) Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40.

Figure 10. External Bus Cycle: Data Write (Non-Page Mode) Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40. Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40.

  1. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch)

a page miss requires two states (4·TOSC).

  1. During a sequence of page hits, PSEN# rema ins low until the end of the last page-hit

4135D–8051–08/05 AC Characteristics - Real-Time Asynchronous Wait State Definition of Symbols Table 43. Real-Time Asynchronous Wait Timing Symbol Definitions Timings Table 44. Real-Time Asynchronous Wait AC Timings; V DD = 2.7 to 5.5 V, T A = -40 to 85°C Note: 1. N is the number of wait states added (N ≥ 1). Waveforms Figure 16. Real-time Asynchronous Wait State Timings AC Characteristics - Serial Port in Shift Register Mode Definition of Symbols Table 45. Serial Port Timing Symbol Definitions Signals Conditions S PSEN#/RD#/WR# L Low Y AWAIT# V Valid X No Longer Valid Symbol Parameter Min Max Unit TSLYV PSEN#/RD#/WR# Low to Wait Set-up T OSC - 10 ns TSLYX Wait Hold after PSEN#/RD#/WR# Low (2N-1)·T OSC + 10 ns (1) TSLYV TSLYX RD#/PSEN#/WR# AWAIT# Signals Conditions D Data In H High Q Data Out L Low XC l o c k V V a l i d X No Longer Valid

Note: 1. For high speed versions only. Figure 17. Serial Port Waveforms - Shift Register Mode Note: 1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.

12 MHz 16 MHz 24 MHz (1)

  1. Determined by the external bus-line capa citance and the external bus-line pull-up

resistor, this must be < 1 μs.

  1. Spikes on the SDA and SCL lines with a duration of less than 3·T CLCL will be filtered
  2. T CLCL = TOSC = one oscillator clock period.

Figure 18. TWI Waveforms

0.7 VDD

0.3 VDD

4135D–8051–08/05 AC Characteristics - SSLC: SPI Interface Definition of Symbols Table 48. SPI Interface Timing Symbol Definitions Signals Conditions CC l o c k H H i g h I Data In L Low O Data Out V Valid S SS# X No Longer Valid Z Floating

4135D–8051–08/05 Timings Table 49. SPI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C Notes: 1. Capacitive load on all pins = 200 pF in slave mode. 2. The value of this parameter depends on software. 3. Capacitive load on all pins = 100 pF in master mode. Symbol Parameter Min Max Unit Slave Mode(1) TCHCH Clock Period 8 T OSC TCHCX Clock High Time 3.2 T OSC TCLCX Clock Low Time 3.2 T OSC TSLCH, TSLCL SS# Low to Clock edge 200 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TCLOV, TCHOV Output Data Valid after Clock Edge 100 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TCLSH, TCHSH SS# High after Clock Edge 0 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TSLOV SS# Low to Output Data Valid 130 ns TSHOX Output Data Hold after SS# High 130 ns TSHSL SS# High to SS# Low (2) TILIH Input Rise Time 2 μs TIHIL Input Fall Time 2 μs TOLOH Output Rise time 100 ns TOHOL Output Fall Time 100 ns Master Mode(3) TCHCH Clock Period 4 T OSC TCHCX Clock High Time 1.6 T OSC TCLCX Clock Low Time 1.6 T OSC TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns TCLOV, TCHOV Output Data Valid after Clock Edge 65 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TILIH Input Data Rise Time 2 μs TIHIL Input Data Fall Time 2 μs TOLOH Output Data Rise time 50 ns TOHOL Output Data Fall Time 50 ns

Note: 1. SS# handled by software. Figure 20. SPI Master Waveforms (SSCPHA = 1) Note: 1. Not Defined but normally MSB of character just received.

Figure 23. EPROM Programming Waveforms

Figure 24. EPROM Verifying Waveforms

  1. Timing measurements are made on all outputs at V IH min for a logic 1 and VIL max for

4135D–8051–08/05 Absolute Maximum Rating and Operating Conditions Absolute Maximum Ratings Ambient Temperature Under Bias V DD *NOTICE: Stressing the device beyond the “Absolute Maxi- mum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.

Table 55. DC Characteristics; VDD = 4.5 to 5.5 V, TA = -40 to +85°C

  1. Capacitive loading on Ports 0 and 2 may cause spurious nois e pulses above 0.4 V on the low-level outputs of ALE and Ports

0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.

  1. Capacitive loading on Ports 0 and 2 causes the V OH on ALE and PSEN# to drop below the specification when the address
  2. Typical values are obtained using V DD = 5 V and TA = 25°C. They are not tested and there is not guarantee on these values.
  3. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3·V DD will be recog-

nized as a logic 0 while an input voltage above 0.7·VDD will be recognized as a logic 1. Figure 28. IDD/IDL Versus Frequency; VDD = 4.5 to 5.5 V Note: 1. The clock prescaler is not used: F OSC = FXTAL.

Table 56. DC Characteristics; VDD = 2.7 to 5.5 V, TA = -40 to +85°C

5 MHz, V

  • CDIL 40 with window
  • PLCC 44
  • CQPJ 44 with window
  • VQFP 44 (10x10) PDIL 40 - Mechanical Outline

Figure 33. Plastic Dual In Line Table 57. PDIL Package Size

Figure 34. Ceramic Dual In Line Table 58. CDIL Package Size

Figure 35. Plastic Lead Chip Carrier Table 59. PLCC Package Size

Figure 36. Ceramic Quad Pack J Table 60. CQPJ Package Size

Figure 37. Shrink Quad Flat Pack (Plastic) Table 61. VQFP Package Size

4135D–8051–08/05 AT/TSC8x251G2D

Ordering Information

Note: 1. xxx: means ROM code, is Cxxx in case of encrypted code. Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC80251G2D-16CB ROMless 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC80251G2D-24CB ROMless 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC80251G2D-24CE ROMless 24 MHz, Commercial 0 ° to 70°C, VQFP 44 TSC80251G2D-24IA ROMless 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC80251G2D-24IB ROMless 24 MHz, Industrial -40 ° to 85°C, PLCC 44 AT80251G2D-SLSUM ROMless 24 MHz, Industrial & Green -40 ° to 85°C, PLCC 44 AT80251G2D-3CSUM ROMless 24 MHz, Industrial & Green -40 ° to 85°C, PDIL 40 AT80251G2D-RLTUM ROMless 24 MHz, Industrial & Green -40 ° to 85°C, VQFP 44 Low Voltage Versions 2.7 to 5.5 V TSC80251G2D-L16CB ROMless 16 MHz, Commercial, PLCC 44 TSC80251G2D-L16CE ROMless 16 MHz, Commercial, VQFP 44 AT80251G2D-SLSUL ROMless 16 MHz, Industrial & Green, PLCC 44 AT80251G2D-RLTUL ROMless 16 MHz, Industrial & Green, VQFP 44 Part Number(1) ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC251G2Dxxx-16CB 32K MaskROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G2Dxxx-24CB 32K MaskROM 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G2Dxxx-24CE 32K MaskROM 24 MHz, Commercial 0 ° to 70°C, VQFP 44 TSC251G2Dxxx-24IA 32K MaskROM 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC251G2Dxxx-24IB 32K MaskROM 24 MHz, Industrial -40 ° to 85°C, PLCC 44 AT251G2Dxxx-SLSUM 32K MaskROM 24 MHz, Industrial & Green -40 ° to 85°C, PLCC 44 AT251G2Dxxx-3CSUM 32K MaskROM 24 MHz, Industrial & Green -40° to 85°C, PDIL 40 AT251G2Dxxx-RLTUM 32K MaskROM 24 MHz, Industrial & Green -40 ° to 85°C, VQFP 44 Low Voltage Versions 2.7 to 5.5 V TSC251G2Dxxx-L16CB 32K MaskROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G2Dxxx-L16CE 32K MaskROM 16 MHz, Commercial 0 ° to 70°C, VQFP 44 AT251G2Dxxx-SLSUL 32K MaskROM 16 MHz, Industrial & Green, PLCC 44 AT251G2Dxxx-RLTUL 32K MaskROM 16 MHz, Industrial & Green, VQFP 44

4135D–8051–08/05 AT/TSC8x251G2D AT/TSC87251G2D OTPROM Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC87251G2D-16CB 32K OTPROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC87251G2D-24CB 32K OTPROM 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC87251G2D-24CED 32K OTPROM 24 MHz, Commercial 0 ° to 70°C, VQFP 44 TSC87251G2D-24IA 32K OTPROM 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC87251G2D-24IB 32K OTPROM 24 MHz, Industrial -40 ° to 85°C, PLCC 44 AT87251G2D-SLSUM 32K OTPROM 24 MHz, Industrial & Green -40 ° to 85°C, PLCC 44 AT87251G2D-3CSUM 32K OTPROM 24 MHz, Industrial & Green -40 ° to 85°C, PDIL 40 AT87251G2D-RLTUM 32K OTPROM 24 MHz, Industrial & Green -40 ° to 85°C, VQFP 44 Low Voltage Versions 2.7 to 5.5 V TSC87251G2D-L16CB 32K OTPROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC87251G2D-L16CED 32K OTPROM 16 MHz, Commercial 0 ° to 70°C, VQFP 44 AT87251G2D-SLSUL 32K OTPROM 16 MHz, Industrial & Green, 0 ° to 70°C, PLCC 44 AT87251G2D-RLTUL 32K OTPROM 16 MHz, Industrial & Green, 0 ° to 70°C, VQFP 44

4135D–8051–08/05 AT/TSC8x251G2D Options (Please consult Atmel sales)

  • ROM code encryption
  • Tape & Reel or Dry Pack
  • Known good dice
  • Extended temperature range: -55 °C to +125°C Product Markings ROMless versions ATMEL Customer Part number Part Number YYWW . Lot Number Mask ROM versions ATMEL Part number YYWW . Lot Number OTP versions ATMEL Part number YYWW . Lot Number

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