Download PDFAT76C101 ATMEL
Document overview
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- PDF pages: 13
Technical content
Features
- Compatible with the JPEG Baseline Standard as Defined by ISO IS 109 18-1
- Highly-integrated, Low-cost Single Chip Solution
- Up to 40 Mbytes/sec Sustained Compression Rate
- Maximum Processing Rate of 1.6 million pixels/sec
- Supports 8-bit Grayscale and YUV 4:2:2 Color Space Input and Output Formats
- Handles Images of Size up to 1024 x 1024 Pixels
- Fast DCT/IDCT Processor On-chip
- User-defined Quantization and Huffman Tables
- Support for Fast as well as Slow/Inexpensive Memories
- Provides Direct Interface for Microcontroller/Microprocessor Access
Applications
The AT76C101 JPEG Processor is optimized for use in the following applications:
- Digital Cameras
- Color Printers and Plotters
- Low-cost Image Compression Systems
- Video Editing (3-4 frames/sec at CCIR 720 x 480 Image Resolution) Hardware Resources
- On-chip Video Interface
- Custom Discrete Cosine T ransform and Quantization Processor
- Variable Length and Huffman Encoder/Decoder
- Programmable Memory Interface (Supports Slow Memories)
- Microcontroller/Microprocessor Access Bus Pin Configuration SRDATA 15-0 SRADDR 14-0 PXWE PXRE PXIN PXOUT STOP_PIXEL SRDRIVE H_SYNC V_SYNC PX_CLK CLK_IN M_ADDR 19-0 M_DATA 7-0 MEM_CS TEST RESET FRAMEND FREEZE MASTER_CS MASTER_WR MASTER_OE BUSY BST_TEST 100-Pin QFP JPEG Image Compression Processor AT76C101 Rev. 0751A–04/98
Description
The AT76C101 is an Image Compression/Decompression Processor that performs the JPEG Baseline Algorithm. The system is capable of high quality compression and decom- pression of continues-tone color or monochrome images. The AT76C101 performs the Discrete Cosine Transform, Quantization, and Entropy Encoding during the compres- sion stage and carries out all inverse operations during the decompression phase. The AT76C101 uses an external SRAM as working memory, which is accessed by an on- chip video interface. The AT76C101 is designed to operate with minimum host intervention. A host processor is required to program the chip in the required operating mode, and to extract the JPEG header from the compressed bit stream during the decompression phase. Based on this information, it then initializes the internal registers. Once the chip has been ini- tialized, the AT76C101 operates continuously until it has completed compression/decompression of a image frame. The image compression ratio is controlled by the user sup- plied quantization tables, which are loaded before the com- pression/decompression operation. Compression ratios from 1:1 to 50:1 are possible depending on the quality and storage requirements of the application. Basic System Configuration An AT76C101-based image compression system is shown in Figure 1. The AT76C101 requires the following external devices:
- A microcontroller to program and initialize the chip in the required operating mode. This device is also used to strip the JPEG header during decompression and to provide the A T76C101 with the header information.
- An external working memory (SRAM) for handling uncompressed/decompressed images. The size of this memory depends on the size of the image being processed. The formula to assess the memory size is given in the Pixel Interface section of this manual.
- An external memory device to store the compressed data stream. This external memory can be either a fast memory or a slow inexpensive memory. The size of this memory depends on the needs of the specific application.
Figure 1. AT76C101-based Image Compression System
sion, the AT76C101 generates images in the same format. HSyncWidth, the width of active HSync in number of pixels. mation for VSync in terms of scan lines, rather than pixels. line. HActive contains the number of active blocks in a line.
- Buffer bus width = 16 bits [For YUV data], 8 bits [For Grayscale data]
- Buffer size = 16 x (No. of pixels per line) As an example, a system designed to process images of the maximum size of 1024 x 1024 pixels would have the following external buffer requirements:
- Buffer size = 16 x 1024 = 16,384 words Thus, this system would require 16K x 16 working memory to process YUV images (color) and 16K x 8 working mem- ory to process grayscale images. As the minimum size of available SRAM is 32K x 8, the SRAM requirements are as follows: YUV/grayscale images: two 32K x 8 SRAM’s to form a 32K x 16 SRAM.
Figure 2. Memory Organization
1024 PIXELS
16 BITS
8 BITS 8 BITS
SRAM ORGANIZATION FOR MAXIMUM SCAN LINE SIZE OF 1024 PIXELS. EACH DATABANK STORES 8 SCAN LINES OF THE RAW IMAGE.
fer the compressed data to an external memory device. internal memory (registers and tables) of the AT76C101. that allows the chip to interface with slow memory devices. memory while the AT76C101 is in the operating mode. start address of the compressed data memory. cessor) to access the internal memory of the JPEG chip. of the chip for testing purposes. When the AT76C101 chip is operating in normal mode (i.e. AT76C101 is activated by setting the Start_Reg register. between frames and not during normal mode of operation. pressed data FIFO (Figure 3). Figure 3. Data Control
the last compressed data into the Mem_End_Addr register. have to load the internal Huffman and Quantization Tables. tioned initialization sequence. required values before the normal operation of the chip. Figure 4. Internal Memory Organization (Quantization and MaxMin Tables)
40 BITS
8 BITS 16 BITS 16 BITS
to the AT76C101 specific format (AT76C101_Q_Table).
- The Quantization T ables are stored in the zigzag form in the JPEG interchange format. Convert these tables to the normal (un-zigzagged) form.
- Convert to A T76C101 format using the following algorithm where, M_Factor[i][j] = 16,384, if (i=1 and j=1) 32,768/sqrt(2), if (i=1 and j=2.8) or (i=2.8 and j=1) 32,768 otherwise: for (i = 1..8) begin for (j = 1..8) begin if (mode = COMPRESS) AT76C101_Q_Table[i][j] = (M_Factor[i][j]/ JPEG_Q_Table[i][j]) + 0.5 else if (mode = DECOMPRESS) AT76C101_Q_Table[i][j] = JPEG_Q_Table[i][j] end end The Quantization tables are 16 bits wide and are loaded using the host bus. The host bus accesses the quantization table values in two 8-bit halves, with the lower address cor- responding to the lower order byte and the higher address corresponding to the higher order byte (Figure 4). Huffman Table Loading Like the Quantization tables, the AT76C101 Huffman tables are specific to the chip. Before normal operation of the chip, the Huffman tables must be loaded in the AT76C101 specific format into the on-chip RAM. The INT_Table_Load_Enable register has to be set to load the Huffman tables. When the Huffman tables are loaded into the internal RAM, they remain valid until the power is switched off or until they are reprogrammed (they are not affected by RESET). The Huffman_Table_Load_Enable register has to be reset after the tables are loaded and before normal operation of the chip can begin. The AT76C101 can store up to four Huffman tables: 2 Huff- man AC tables and 2 Huffman DC tables. The memory organization and address mapping of the Huffman tables are given in Figure 5. The Huffman tables are 28 bits wide and consist of three fields, the size of the Huffman code (stored as 1 less than actual size), the Huffman code and the 8-bit symbol corresponding to the Huffman code. Each Huffman table value is accessed from the host bus in four 8-bit slices, with the lower order 8 bits corresponding to the lowest address (for e.g. 2000H) and the highest 8-bit slice (bit 24 through bit 31) corresponding to the highest address (2003H).
Figure 5. Internal Memory Organization (Huffman Tables)
28 BITS
0000 CODE (BITS 15-12)
0000 CODE SIZE - 1 8-BIT SYMBOL
16 BITS 4 BITS 8 BITS
The Huffman tables have the same format in both the com- pression and decompression mode, but the arrangement of the codes within the tables varies for the two modes. In the compression mode, the Huffman tables are indexed by the 8-bit symbol corresponding to the code. For example, the luminance AC Huffman table value corresponding to the 8- bit symbol value of 17 will be stored in the 17th location of the table, i.e. in the address locations 4068 to 4071. In the decompression mode, the Huffman tables are arranged in consecutive locations in increasing order of Huffman size. All codes of the same Huffman size are then arranged in terms of increasing Huffman code value. Appendix A, annex C of the JPEG International Standard gives the pro- cedure for generating the Huffman codes and sizes from the Huffman table information extracted from the com- pressed JPEG header. MaxMin Table Loading The Maxmin tables are an extra set of tables which are required only for the decompression operation. Similar to the Huffman tables, these tables can be loaded only after the INT_Table_Load_Enable register has been set, and this register has to be reset before normal operation of the AT76C101 can commence. This table is required to keep track of the maximum and minimum Huffman code values for each Huffman code length. Since there is a maximum of
4 Huffman tables allowed and the longest Huffman code is
16 bits wide, the required maxmin table size is 64 words. The four maxmin tables are arranged in increasing order of size and each word of the maxmin table is 40 bits wide with three fields, a pointer to the position of the minimum code of that Huffman size, the minimum Huffman code and the maximum Huffman code corresponding to that Huffman code size. The maxmin tables are accessed by the host bus in terms of five 8-bit slices with the lowest address cor- responding to bit 0-7 of the maxmin table value and the highest address corresponding to bit 32-39 (Figure 4). These tables are generated from the AT76C101 specific decompression mode Huffman tables and the algorithm to develop them is given below: for (i = 1..16) begin maxmin_min_code[i] = -1 maxmin_max_code[i] = -1 end for (i=1..total_num_of_huffman_codes) if (maxmin_min_code[size[i]] == -1) begin maxmin_min_code[size[i]] = code[i] maxmin_val_ptr[size[i]] = i end maxmin_max_code[size[i]] = code[i]
Figure 6. Symbol
30 M_ADD5
29 M_ADD6
28 M_ADD7
27 M_ADD8
26 M_ADD9
25 M_ADD10
23 M_ADD11
22 M_ADD12
21 M_ADD13
19 M_ADD14
18 M_ADD15
17 M_ADD16
16 M_ADD17
15 M_ADD18
14 PWR
13 M_ADD19
12 BUSY
11 FRAMEND
9 SRDRIVE
8 PWR
7 PX_CLK
6 HSync
5 VSync
4 Vcc
2 PXOUT
1 PXIN
50 M_DATA749 M_DATA648 GND47 M_DATA546 M_DATA445 M_DATA344 M_DATA243 M_DATA142
41 M_DATA040 MAST_WR39 MAST_OE38 MEM_CS37 PWR36 M_ADD035 M_ADD134 M_ADD233 M_ADD332 M_ADD431 PWR
Table 1. Signal Description BST_TEST Input BIST test pin (used only for testing), should be grounded. block and then remains in that state until freeze is pulled low. MAST_CS Input Master Chip Select Input. Used by microcontroller to access the JPEG chip. Active low. PX_CLK Input Video Interface Clock (27 MHz fixed). RESET_ Input Global Reset Signal, active high, minimum pulse width is three CLK_IN 40 MHz cycles. HSync Bidirectional Indicates start of a horizontal line of the frame. memory, and used by microcontroller to access the JPEG chip. M_DA T A[7:0] Bidirectional Memory/ Microcontroller Data Bus. Used to transfer compressed data to the external storage unit. Also used by microcontroller to program the JPEG chip. chip and used by JPEG chip to read compressed data from memory. used by JPEG to write to compressed data memory. decompressed image data in decoding mode. VSync Bidirectional Indicates the start of a frame. BUSY Output Microcontroller bus busy. Signals whether the JPEG chip (high) or microcontroller (low) controls the bus. until the Start Register is set by the host. device used to store the compressed data stream. frame into the strip buffer. PXRE Output Active low. Controls reading data from external memory. PXWE Output Active low. Controls writing to the external memory. SRDRIVE Output Indicates that the A T76C101 is driving the SRDA TA Bus. are full, or when the ext. video logic is not ready.
Table 2. Register File Description HPeriod_Low 0F800 R/W HPeriod-low byte (bit 0 to 7). HSYNC pulse (in terms of pixels). between successive Hsync pulses. HPeriod_High 0F801 R/W HPeriod - high byte (bit 8 to 15). HSyncWidth_Low 0F802 R/W HSyncWidth - low byte. Used only in Master mode. HSyncWidth_High 0F803 R/W HSyncWidth - high byte. HDelay_Low 0F804 R/W HDelay - low byte. Delay from falling edge of HSYNC to the first active pixel. HDelay_High 0F805 R/W HDelay - high byte. HActive_Low 0F806 R/W HActive - low byte. For color images: size of active horizontal line divided by 8. For grayscale images: size of active horizontal line in pixels divided by 16. HActive_High 0F807 R/W HActive - high byte. VPeriod_High 0F809 R/W VPeriod - high byte. VSyncWidth_Low 0F80A R/W VSyncWidth - low byte. VSyncWidth_High 0F80B R/W VSyncWidth - high byte. VDelay_Low 0F80C R/W VDelay - low byte. VDelay_High 0F80D R/W VDelay - high byte. VActive_Low 0F80E R/W VActive - low byte. Number of active vertical lines. VActive_High 0F80F R/W VActive - high byte. Start_Reg 0F810 R/W Bit 0 is used to initiate the compression/decompression pipeline. Mode 0F812 R/W Determine the device operating mode. The function of each bit is shown below. Bit 0: Encode(0)/Decode(1) operation. Bit 1: Color(0)/Grayscale(1) Image. Bit 2: Video Master(1)/Slave(0) Mode. Rest of bits are reserved and should be set to zero. enables loading the Huffman T ables, including the MAXMIN tables. Decoder_Error 0F814 R The chip sets this register to 1, if an error occurs while decoding. Decoder_Error_Code_Low 0F815 R Decoder_Error_Code - high byte. Decoder_Error_Code_High 0F816 R Decoder_Error_Code - high byte.
programmed into this register. programmed into this register. frame written into the external memory. Mem_End_Addr_Med 0F81E R Mem_End_Addr - middle byte (bit 16 to 31). Mem_End_Addr_High 0F81F R Mem_End_Addr - high byte (bit 32 to 39). Table 3. Internal Memory Addressing
Table 5. Absolute Maximum Ratings Table 6. Recommended Operating Conditions Table 7. DC Characteristics