AT73C203

AT73C203_14 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 106

Technical content

Features

(Dynamically Adjustable 1.65V/1.70V/1.80V) 2.5V (Dynamically Adjustable 2.3V/2.4V/2.6V)  DC to DC Step Up/Down 520 mA, 3.3V (Dynamically Adjustable to 3.0V/3.1V/3.4V)  Dual Battery Chargers: Li+ Precharge, Fast Charge, Top-up Charge, 4.1V (or Adjustable), Processor Tuned Algorithms – USB Trickle Charge: Precharge Flat Battery from USB Pre-enumeration, then Auto- wake of Processor at 3.8V Battery Level – Battery Charge Select: 25 mA to 500 mA – Real-time Charge Inhibit: Allows Charge Suspend (e.g. During TX Slots)  Supply Monitor of Four Power Sources: Thermistors, Temperature, DC/DC Rails, all Supplied with Out-of-regulation Threshold Detection  SIM Interface: SIM / USIM, 1.8V / 3.0V Standards, Integrated TX and RX Data FIFO  SPI Control Interface: Up to 13 MHz; Tuned for SA1110/PXA250/PXA255 1.2 MHz SPI, 128 8-bit Registers  Power on Reset: For SA1110/PXA250/PXA255 Architectures plus Additional Sequenced System Level Resets  Voltage and Temperature Supervision  Calibrated Voltage Reference  8-bit ADC with 5-input Multiplexer  Integrated Oscillator, Start-up and Self-protection Circuitry  Off Power: 60 µA with External “Button Select” for Restart  Applications Include: PDAs, PCMCIA Cards, SMART Phones, Pocket PCs, 3G Applications, Intel® XScale™ Powered Applications

Description

The AT73C203 device provides an integrated solution to portable and handheld appli- cations built around microprocessors requiring “smart” power management functions, such as PDAs, Palmtop computers, point-of-sales terminals, 3G modems, etc. Its compact package outline and small size of external components make the AT73C203 suitable for PCMCIA card power management as well. The AT73C203 integrates a power switch controller that, when connected to an exter- nal power switch, may be used for automatically selecting one of four possible power sources:  Internal battery  External battery  Plugtop power supply unit 5V (PSU)  PC Host USB supply The power switch output (VDD-PSU line) is connected directly to external auxiliary components such as a radio or any other “current hungry” module. The AT73C203 is also equipped with four digital rails from VDD-PSU to supply a base- band chip, a reset generator for the baseband chip, and a SPI interface to control the AT73C203 via an internal register set. The USIM interface allows the application pro- cessor to communicate with and control a USIM card. Charge control enables the application processor to charge the battery from the PSU or USB. A state machine can also determine whether to charge the internal battery through USB at start-up. Additionally, hardware monitoring gives information to the application processor when a voltage drop occurs (programmed via internal registers). Power Management AT73C203 Power Management IC for Datacom Platforms

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Figure 1. AT73C203 Functional Diagram

Table 1. AT73C203 Pin Description

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Table 1. AT73C203 Pin Description (Continued)

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Figure 2. AT73C203 Application Schematic

2742B–PMGMT–03/04 Architecture Overview Figure 3. AT73C203 Architecture Overview Several power sources may be used to power the AT73C203 circuitry including an inter- nal or external battery, external PSU or USB. The internal battery is always physically present in the unit, but any or all of the other sources may be connected or disconnected at any time. The AT73C203 enables one application to be powered up from the correct source of up to four possible power sources under hardware control. When powered, the external processor can monitor the input power sources and initiate battery charging as required via the SPI. The application processor is also able to enable/disable the circuit power rails and configure a low power sleep state. An input-multiplexed 8-bit ADC is available that allows the application processor to mon- itor the presence of and measure the voltage of the power sources, batteries and rails. An associated threshold and comparator circuit may be used to indicate to the proces- sor that an out-of limit event has occurred. The battery charging circuitry is designed to allow charging from the PSU input and to allow current-limited 'supplement' charging from the USB input. In both cases, the chargers operate under processor control and monitoring with hardware safety lockout. When the PSU is present, a power path is selected (e.g. from a DC jack) through the power switching circuitry to the external components (e.g. radio and companion chips or chipset, baseband chip etc.) This power path enables the application processor to boot up. A parallel path exists from the PSU input (e.g. jack) through current limiting devices to two battery chargers. The current switches only block reverse current when disabled so care must be taken when controlling them. When a USB input is powered, a single power path exists through the current limiting devices to the two battery chargers. The hardware defaults to a current limit of 100 mA Digital Supply Rails SPI SIM Powerswitch Controller Charger Controller Monitoring Digital I/O Bat 1 Bat 2 PSU USB Radio VOUT1 VOUT2 VOUT3 VOUT4 Li+ 1600 mAh Li+ AC/DC PC Host USB Plug Top 800 mAh Companion Chip or Chipset, eg: Application Processor, Baseband SOC Core and Digital Powerswitch VDD-PSU

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2742B–PMGMT–03/04 but the application processor may set 500 mA after negotiation with the PC. This power should always be used to charge the batteries in the absence of the PSU power source. SIM/USIM interface hardware is provided, allowing the application processor to commu- nicate and control a SIM/USIM card according to the required analog and digital specifications. Most of the blocks are switched on or off by the digital control block (not all the control lines are drawn on the block diagram). Only the supply monitor, digital control, power on reset, 10 kHz internal oscillator and internal regulator are always on. All these blocks are designed to have very low power consumption, capable of achiev- ing three months standby time for the application. Functional Integration The AT73C203 integrates the following functions: Supply Monitor The supply monitor block enables the AT73C203 to correctly switch the four main sup- plies (two batteries, PSU and USB). All the outputs are sent to the digital control. Internal Regulator The internal regulator is a low drop out regulator generating VSAUV at 2.5V with a maxi- mum load of 5 mA. Its input is VSW . Power-on Reset The internal power-on reset is supplied by VSAUV and resets the AT73C203 digital cir- cuitry at 2V. 10 kHz Internal Oscillator The 10 kHz low power oscillator is the clock source for the AT73C203 digital circuitry. V SAUV supplies it. Digital Control The digital block controls each block and drives the SPI interface and the different inter- rupts (external and internal). The controls, inputs and outputs are level shifted when necessary and protected to avoid current flowing between the blocks (not represented in the block diagram). A state machine controls the AT73C203 circuitry according the sup- plies and inputs states. A table of registers is accessible via SPI to command or read status of the AT73C203. Reference Generator The reference generator provides the AT73C203 with a precise bandgap voltage (VREF ) and current bias (IREF ) used by all analog blocks (DC/DC, ADC, charger) except the core blocks. It is turned off under digital control when necessary and is VSAUV supplied. 900 kHz Oscillator and Clock Distribution The 900 kHz oscillator provides the clock to all DC/DC converters. The clock distributor provides phased clocks to the DC/DC converters to avoid switching at the same time. The frequency of the oscillator is trimmed during production to optimize the DC/DC efficiency. DC to DC Step Down 1.2 A, 0.9V 1.2V) is a programmable buck DC/DC converter dedicated to advanced sub-micron pro- cessors and SoC ASIC logic cores requiring dynamic power management at low voltages and high currents. The default voltage is 0.9V for which the device is optimized. The external components needed include a current sensing resistor, a dual PMOS- NMOS, an inductor and an output capacitor.

2742B–PMGMT–03/04 The application processor can change the output voltage via registers accessible by SPI. When the cell is off, the output is in high impedance state. If not used, this section can be permanently deactivated. DC to DC Step Down 1.2A, 1.2V OR 1.75V a programmable buck synchronous DC/DC converter dedicated to the application pro- cessor core and/or a “companion” ASIC SoC Processor Core. The default voltage is 1.65V. The entire cell is optimized for 1.2V. The application processor can change the output voltage as described above via registers accessible by SPI. The external components needed include a current sensing resistor, a dual PMOS- NMOS, one inductor and one output capacitor. When the cell is off, the output is pulled to ground. If not used, this section can be permanently deactivated DC to DC Step Down 1.2A, 1.8V OR 2.5V The DC to DC step Down 1.2A, 1.8V (dynamically adjustable to 1.70V/1.75V/1.80V/1.85V) is a programmable buck synchronous DC/DC converter ded- icated to the supply of recent and future Flash and SDRAM memories and their associated buses on the application processor I/O section as well as additional memory extension modules such as CF cards, MMCards, Memory Stick, etc. The default voltage The entire cell is optimized for 1.8V. The application processor can change the output voltage as described above via registers accessible by SPI. The external components needed include a current sensing resistor, a dual PMOS- NMOS, an inductor and an output capacitor. A low quiescent current mode is implemented when a very low standby current is needed with a parallel voltage regulator. When the cell is off, the output is in high impedance state. DC to DC Step Up/ Down 520 mA, 3.3V The DC to DC step Up/Down 520 mA, 3.3V (dynamically adjustable to 3.0V/3.1V/ 3.4V) is a boost DC/DC 3.6V converter followed by a linear drop out regulator. It is intended to supply 3.3V I/Os needed in the application (Audio Codec, LCD, Memories). The external components needed include a current sensing resistor, an NMOS, a Schottky diode, an inductor and an output capacitor. The default value of the LDO is 3.3V but three other values can be programmed: 3.1V, change the output voltage as described above via registers accessible by SPI. When the cell is off, the output is pulled to ground. Power Switch Controller The power switch controller drives an external PMOS switch to multiplex VDD-PSU from the internal or external battery or USB. The purpose of this cell is to guarantee a suffi- cient supply for VDD-PSU and to limit voltage drops even during switchover. In-rush current and current flow between the inputs must be avoided. When this cell is off, VDD-PSU is left in high impedance. Current Generators Two accurate current generators allow the measurement of the resistance of two exter- nal battery thermistors. The outputs VTHE1 and VTHE2 go to the measurement bridge. The

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2742B–PMGMT–03/04 current generators are supplied by VSAUV and controlled by the digital control for use during battery charging. Temperature Sensor The temperature sensor voltage output depends linearly on temperature. It is supplied by V SAUV and driven by the digital control. The temperature seen by the sensor is directly related to the chip activity and the power internally dissipated. To get a good indication of the ambient temperature, the software must take into account this offset. Measurement Bridge/ Multiplexer The measurement bridge provides adapted voltages of the internal and external batter- ies, DC/DC converter outputs, USB, VDD-PSU, V THE1 and VTHE2 to the multiplexed input of the serial analog to digital converter. Analog to Digital Converter An 8-bit analog to digital converter is integrated into the AT73C203 to give information about voltage and temperature to the application processor via the SPI interface. Li-Ion/Battery Chargers The battery chargers both have stand-alone constant current (CC) precharge and micro- processor-controlled CC fast charge as well as top-off mode end-of-charge algorithm. The digital block controls this cell. All current and voltage settings are programmable via registers. The charger controller is divided into two similar parts, one for the internal battery and one for the external battery. Each charger multiplexes the source (USB or PSU) and lim- its the programmable current charge (via sense resistor). An external PMOS and a Schottky diode are needed for each charger. The application processor must check that the temperature allows charging via the cur- rent generator, measurement bridge and ADC. USIM Voltage Regulator A regulator is provided to power up the USIM card. It is supplied directly from VDD_PSU. One of two different voltages can be selected:  2.8V (50 mA)  1.8V (30 mA) By default, the regulator is in power-down mode. The pins connected to the USIM (SIM_CLK, SIM_IO, SIM_PWR) must have driver specification according to ETS TS 102 221. USIM Digital Section The main part of the USIM digital section is an ISO7816 UART compatible interface. Reset Generation A reset is generated via the internal state machine. The timer for this internal reset gen- erator is 150 ms (typical). The application processor can set the AT73C203 to off mode via the POWER_EN pin. The “internal” reset is active at low level. Another way to generate a reset is to program it through the monitoring function (ADC with measurement bridge and data registers). The “monitoring” reset is active at low level. A logical AND of the “internal” and the “monitoring” reset drives the reset of the external application processor (NPROC_RESET pin). Other pins are used to generate separated resets for external “companion” chips such as baseband chips. NSHUTDOWN forces the AT73C203 internal digital block to the reset state. This turns all the supplies off and then restarts the internal state machine.

Table 2. Recommended External Components

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Table 3. Recommended Operating Conditions

Figure 4. Start-up Overview The system has two modes: Off and Active. are controlled by software (via internal registers).

2.5 V 5 mA

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AT73C203 voltage drop in order to maximize battery life. See Figure 4 on page 13. SW_IN which minimizes the voltage drop across the Schottky diodes. AT73C203 under the following conditions.  One supply is present (PSU), the others are connected to ground or not present.  Both V SW and VSAUV must be stable for the digital block to operate correctly.  The reset for the digital core is the logical OR of POR1 and POR2. Figure 5. PSU Rising Sequence Note: 1. t STARTUPREG = Startup time of the internal regulator.

Figure 6. PSU Drop Sequence Note: 1. t SHUTDOWNREG = Shutdown time of the internal regulator. State Machine Description State machines for the start-up and off modes are described in the following pages. has charged the internal battery from USB with a minimal amount of charge.  Temperature to allow precharging through USB: 0°C to 60°C.

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Figure 7. Startup State Machine (1of 3)

Figure 8. Startup State Machine (2 of 3)

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Figure 9. Startup State Machine (3 of 3)

Figure 10. USB Sleep State Machine

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Figure 11. Stop Off State Machine

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Table 4. AT73C203 User Interface

Table 4. AT73C203 User Interface (Continued)

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2742B–PMGMT–03/04 General-purpose Registers Chip Identification Register Name: GP_IDENT Access: Read-only  VERSION_ID: Version Identification These four bits correspond to device version. For the first version, VERSION_ID = 0x0.  ATMEL_ID: ATMEL Identification These four bits give the company identification. ATMEL_ID = 0xA Note that GP_IDENT can only be changed by metal mask. For 56H05A and 56H05B, GP_IDENT = 0xA0. For 56H05C, GP_IDENT = 0xA2. GPIO Status Register Name: GP_GPIO_READ Access: Read-only  GPIO_RD_0: Value of ID_BITS0 pin 0: ID_BITS0 = 0 1: ID_BITS0 = 1  GPIO_RD_1: Value of ID_BITS1 pin 0: ID_BITS1 = 0 1: ID_BITS1 = 1  GPIO_RD_2: Value of ID_BITS2 pin 0: ID_BITS2 = 0 1: ID_BITS2 = 1  GPIO_RD_3: Value of ID_BITS3 pin 0: ID_BITS3 = 0 1: ID_BITS3 = 1 76543210 ATMEL_ID VERSION_ID 76543210 - - - - GPIO_RD_3 GPIO_RD_2 GPIO_RD_1 GPIO_RD_0

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2742B–PMGMT–03/04 GPIO Control Register Name: GP_GPIO_WRITE Access: Read/Write  GPIO_OE_0: Output enable for ID_BITS0 pin 0: ID_BITS0 pin configures as input 1: ID_BITS0 pin configures as output  GPIO_OE_1: Output enable for ID_BITS1 pin 0: ID_BITS1 pin configures as input 1: ID_BITS1 pin configures as output  GPIO_OE_2: Output enable for ID_BITS2 pin 0: ID_BITS2 pin configures as input 1: ID_BITS2 pin configures as output  GPIO_OE_3: Output enable for ID_BITS3 pin 0: ID_BITS3 pin configures as input 1: ID_BITS3 pin configures as output  GPIO_DO_0: Output data for ID_BITS0 pin 0: ID_BITS0 pin sets to 0 (if GPIO_OE_0 = 1) 1: ID_BITS0 pin sets to 1 (if GPIO_OE_0 = 1)  GPIO_DO_1: Output data for ID_BITS1 pin 0: ID_BITS1 pin sets to 0 (if GPIO_OE_1 = 1) 1: ID_BITS1 pin sets to 1 (if GPIO_OE_1 = 1)  GPIO_DO_2: Output data for ID_BITS2 pin 0: ID_BITS2 pin sets to 0 (if GPIO_OE_2 = 1) 1: ID_BITS2 pin sets to 1 (if GPIO_OE_2 = 1)  GPIO_DO_3: Output data for ID_BITS3 pin 0: ID_BITS3 pin sets to 0 (if GPIO_OE_3 = 1) 1: ID_BITS3 pin sets to 1 (if GPIO_OE_3 = 1) 76543210

2742B–PMGMT–03/04 Digital Rail Trimming Register Name: DC _TRIM Access: Read/Write  DC_TRIM_1: Trimming for rail 1 output voltage If SELDC175 = 0: If SELDC175 = 1:  DC_TRIM_2: Trimming for rail 2 output voltage If SELDC25 = 0: If SELDC25 = 1: 76543210 DC_TRIM_1 00 Rail 1 output voltage = 1.2V (default value) 01 Rail 1 output voltage = 1.3V 10 Rail 1 output voltage = 1.1V 11 Rail 1 output voltage = 1.5V DC_TRIM_1 00 Rail 1 output voltage = 1.75V (default value) 01 Rail 1 output voltage = 1.80V 10 Rail 1 output voltage = 1.70V 11 Rail 1 output voltage = 1.65V DC_TRIM_2 00 Rail 2 output voltage = 1.80V (default value) 01 Rail 2 output voltage = 1.85V 10 Rail 2 output voltage = 1.75V 11 Rail 2 output voltage = 1.70V DC_TRIM_2 00 Rail 2 output voltage = 2.50V (default value) 01 Rail 2 output voltage = 2.60V 10 Rail 2 output voltage = 2.40V 11 Rail 2 output voltage = 2.30V

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2742B–PMGMT–03/04  DC_TRIM_3: Trimming for rail 3 output voltage  DC_TRIM_4: Trimming for rail 4 output voltage DC_TRIM_3 00 Rail 3 output voltage = 3.3V (default value) 01 Rail 3 output voltage = 3.1V 10 Rail 3 output voltage = 3.2V 11 Rail 3 output voltage = 3.4V DC_TRIM_4 00 Rail 4 output voltage = 0.9V (default value) 01 Rail 4 output voltage = 1.20V 10 Rail 4 output voltage = 0.87V 11 Rail 4 output voltage = 1.10V

2742B–PMGMT–03/04 Power Switch Control Register Name: PWS _CR (0x4C) Access: Read/Write With PWS_FORCE, the microprocessor can force selection of an input source. This may be used to test the AT73C203 or by the microprocessor to force use of one of the batteries.  PWS_FORCE: Force an input source to be selected  PWS_ENBAT1: Reset FLATBAT1 (refer to “Power Switch Status Register” on page 30) 0: No action (default value) 1: FLATBAT1 is reset to 0  PWS_ENBAT2: Reset FLATBAT2 (refer to “Power Switch Status Register” on page 30) 0: No action (default value) 1: FLATBAT2 is reset to 0 7654 3 2 1 0 ---- P W S _ E N B A T 2 P W S _ E N B A T 1 P W S _ F O R C E PWS_FORCE Input Selected 0 0 Power switch runs automatically (default mode) 0 1 PSU 1 0 Battery 2 1 1 Battery 1

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2742B–PMGMT–03/04 Power Switch Status Register Name: PWS _SR Access: Read-only  PWS_STATUS: Status of the power switch With PWS_STATUS (bits accessible via SPI), the microprocessor can read which supply is currently selected by the A T73C203.  FLATBAT1: BAT1 flat threshold indication 0: Default and reset value 1: Bat1 voltage has reached flat threshold during selection (latched value). Bat1 cannot be used as input source (until reset by the microprocessor)  FLATBAT2: BAT2 flat threshold indication 0: Default and reset value 1: Bat2 voltage has reached flat threshold during selection (latched value). Bat2 cannot be used as input source (until reset by the microprocessor) 7654 3 2 1 0 ---- F L A T B A T 2 F L A T B A T 1 P W S _ S T A T U S PWS_STATUS Input Selected 0 0 Power switch off or no input selected 0 1 PSU 1 0 Battery 2 1 1 Battery 1

2742B–PMGMT–03/04 USB Flag Status Name: USB_FST Access: Read-only  USB_FST: USB flag status 0: USB has not been used to precharge (stand alone mode) 1: USB has been used to precharge (stand alone mode) Refer to “State Machine Description” on page 15. USB Flag Control Name: USB_FCR (0x4E) Access: Write-only  USB_FCR: USB flag control 0: No action 1: Resets USB_FST to 0  USB_SCR: USB sleep control 0: No action 1: Enter in “USB SLEEP STA TE MACHINE” Refer to “State Machine Description” on page 15. 7654 3 2 1 0 ---- - - - U S B _ F S T 7654 3 2 1 0 ---- - - U S B _ S C R U S B _ F C R

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2742B–PMGMT–03/04 USIM Interface Registers Channel Status Register Name: SIM_CSR (0x32) Access: Read-only  RXRDY: Receiver Ready 0: The receiver FIFO is empty. 1: At least one complete character has been received.  RXFULL: Receiver Full 0: The receiver FIFO is not full. 1: The receiver FIFO is full.  OVRE: Overrun Error 0: No byte has been transferred from the Receive Shift Register to the receiver FIFO when RXFULL was asserted since the last Reset Status Bits command. 1: At least one byte has been transferred from the Receive Shift Register to the receiver FIFO when RXFULL was asserted since the last Reset Status Bits command.  PARE: Parity Error 0: No parity bit has been detected as false since the last Reset Status Bits command. 1: At least one parity bit has been detected as false since the last Reset Status Bits command.  TXRDY: Transmitter Ready 0: The transmitter FIFO is full. 1: The transmitter FIFO is not full.  TXEMPTY: Transmitter Empty 0: There are characters in either the transmitter FIFO or the Transmit Shift Register. 1: There are no characters in either the transmitter FIFO or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if SIM_TTGR is not 0.  TXNACK: Non Acknowledge 0: A Non Acknowledge has not been detected during a transmission 1: A Non Acknowledge has been detected during a transmission. 7654 3 2 1 0 - TXNACK TXEMPTY TXRDY PARE OVRE RXFULL RXRDY

2742B–PMGMT–03/04 Buffer Status Register Name: SIM_BSR Access: Read-only  RXPTR: Receiver buffer pointer Indicates the number of characters waiting to be read in the receiver FIFO. If RXPTR = 15 then if RXFULL is set, there are 16 characters in the FIFO, otherwise there are 15.  TXPTR: Transmitter buffer pointer Indicates the number of characters waiting to be transmitted from the transmitter FIFO. If TXPTR = 15 then if TXRDY is set, there are 15 characters in the FIFO, otherwise 16. Miscellaneous Status Register Name: SIM_MSR Access: Read-only  TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command.  ITERATION: Max number of Repetitions Reached Note: This bit will operate only in Protocol T: 0. 0: Max number of repetitions has not been reached. 1: Max number of repetitions has been reached. A repetition consists of transmitted characters or successive NACK.  PRES: SIM card presence 0: The SIM card is not present. 1: The SIM card is present. 7654 3 2 1 0 TXPTR RXPTR 7654 3 2 1 0 ---- - P R E S I T E R A T I O N T I M E O U T

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2742B–PMGMT–03/04 Interrupt Mask Register 1 Name: SIM_IMR1 (0x37) Access: Read/Write  RXRDY: Enable RXRDY Interrupt 0: Disables RXRDY Interrupt. 1: Enables RXRDY Interrupt.  RXFULL: Enable RXFULL Interrupt 0: Disables RXFULL Interrupt. 1: Enables RXFULL Interrupt.  OVRE: Enable Overrun Error Interrupt 0: Disables Overrun Error Interrupt. 1: Enables Overrun Error Interrupt.  PARE: Enable Parity Error Interrupt 0: Disables Parity Error Interrupt. 1: Enables Parity Error Interrupt.  TXRDY: Enable TXRDY Interrupt 0: Disables TXRDY Interrupt. 1: Enables TXRDY Interrupt.  TXEMPTY: Enable TXEMPTY Interrupt 0: Disables TXEMPTY Interrupt. 1: Enables TXEMPTY Interrupt.  TXNACK: Enable Non Acknowledge Interrupt 0: Disables Non Acknowledge Interrupt. 1: Enables Non Acknowledge Interrupt 7654 3 2 1 0 - TXNACK TXEMPTY TXRDY PARE OVRE RXFULL RXRDY

2742B–PMGMT–03/04 Interrupt Mask Register 2 Name: SIM_IMR2 (0x39) Access: Read/Write  TIMEOUT: Enable Time-out Interrupt 0: Disables reception time-out interrupt. 1: Enables reception time-out interrupt.  ITERATION: Enable Iteration Interrupt Note: This will operate only in Protocol T: 0. 0: Disables ITERATION interrupt. 1: Enables ITERATION interrupt.  PRES: Enable Presence Interrupt 0: Disables card presence interrupt. 1: Enables card presence interrupt.  RXHALF: Enable Reception Buffer Half Full Interrupt 0: Disables reception buffer half full interrupt. 1: Enables reception buffer half full interrupt.  TXHALF: Enable Transmission Buffer Half Full Interrupt 0: Disables transmission buffer half full interrupt. 1: Enables transmission buffer half full interrupt. 7654 3 2 1 0 - - - TXHALF RXHALF PRES ITERATION TIMEOUT

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2742B–PMGMT–03/04 Mode Register Name: SIM_MR (0x35) Access: Read/Write  TMODE: Protocol Mode 0: Protocol T: 0 1: Protocol T: 1  IRXNACK: Inhibit Reception Non Acknowledge 0: The NACK is generated 1: The NACK is not generated Note: This bit will be used only in protocol T: 0 receiver.  DSRXNACK: Disable Successive Reception NACK 0: NACK is sent on the IO line as soon as a parity error occurs in the received character (unless IRXNACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener- ate a NACK on the IO line. As soon as this value is reached, no additional NACK is sent on the IO line. The flag ITERATION is asserted.  MAX_ITERATION: Number of Repetitions 0 - 7 This will operate in Protocol T: 0 only  BIT_ORDER 0: LSB first (direct convention) 1: MSB first (inverse convention)  POLARITY: Polarity 0: Odd parity (odd number of 1 on character + parity bit) (inverse convention) 1: Even parity (even number of 1 on character + parity bit) (direct convention) 7654 3 2 1 0 POLARITY BIT_ORDER MAX_ITERATION DSRNACK IRXNACK TMODE

2742B–PMGMT–03/04 Control Register Name: SIM_CR Access: Write-only  RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE AND OVRE in the SIM_CSR.  STTO: Start Time-out 0: No effect 1: Start. waiting for a character before clocking the time-out counter.  RSTIT: Reset Iterations 0: No effect. 1: Resets the status bit Iteration.  RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets the status bit TXNACK.  RETTO: Rearm Time-out 0: No effect 1: Restart. Time-out  RSTPRES: Reset Presence Interrupt 0: No effect 1: Reset. SIM card presence interrupt.  RSTRX: Reset Receiver 0: No effect 1: The receiver logic is reset and the receiver FIFO is emptied.  RSTTX: Reset Transmitter 0: No effect 1: The transmitter logic is reset and the transmitter FIFO is emptied. 7654 3 2 1 0 RSTTX RSTRX RSTPRES RETT RSTNACK RSTIT STTO RSTSTA

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2742B–PMGMT–03/04 Activation Register Name: SIM_AR (0x3F) Access: Read/Write S R E S E T : S I M R e s e t P i n 0: SIM Reset pin: 0. 1: SIM Reset pin: 1.  CLKEN: SIM Clock Enable 0: SIM clock disabled (grounded). 1: SIM clock enabled.  ACTIVE: IO Line Activation 0: IO line at ground. 1: IO line enabled.  VSEL: SIM Voltage Selection 00: Disabled 01: Disabled 10: Regulator output equals 1.8V 11: Regulator output equals 2.8V 7654 3 2 1 0 - - - VSEL ACTIVE CLKEN SRESET

2742B–PMGMT–03/04 Receiver Holding Register Name: SIM_RHR (0x38) Access: Read-only First character received if RXRDY is set. Transmitter Holding Register Name: SIM_THR (0x31) Access: Write-only Next character to be transmitted. If transmitter FIFO is full, the last character is overwritten. Baud Divisor Register Name: SIM_BDR (0x3A) Access: Read/Write The baud rate = f/(div1 x div2) where f is the SIM clock frequency. div1 is coded on BDR[6]. div2 is coded on BDR[5:0]. BDR reset value = b0001100. Initial baud rate = 372. 7654 3 2 1 0 RHR 7654 3 2 1 0 THR 7654 3 2 1 0 -B D R BDR[6] 0 1 div1 31 32 BDR[5:0] 0 1 - 63 div2 64 BDR[5:0]

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2742B–PMGMT–03/04 Clock Divisor Register Name: SIM_CDR (0x3E) Access: Read/Write The SIM clock is generated through a programmable divider. The division factor can be modified in this register. CDR reset value = 0000. 7654 3 2 1 0 ---- C D R CDR[3:0] 0000 0001 to 1111 Clock division factor No clock CDR[3:0]

2742B–PMGMT–03/04 Receiver Time-out Register Name: SIM_RTOR (0x3B and 0x3C) Access: Read/Write 0: Disables the RX Time-out function. 1 - 65535: The Time-out counter is loaded with RTOR (16 bits) when the Start Time-out command is given or when each new data character is received (after reception has started). Transmitter Time Guard Register Name: SIM_TTGR (0x3D) Access: Read/Write Time-guard duration = TG x Bit Period 0: Disables the TX Time-guard function. 1 - 255: IO line is inactive high after the transmission of each character for the time-guard duration. Number of Errors Register Name: SIM_NER (0x30) Access: Read-only NB_ERRORS: Error number during transfers This 8-bit register presents the total amount of errors that occurred during a transfer. It is a read-only register and it is reset by reading the register. 15 14 13 12 11 10 9 8 RTOR 7654 3 2 1 0 RTOR 7654 3 2 1 0 TTGR 7654 3 2 1 0 NER

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2742B–PMGMT–03/04 Voltage and Temperature Monitoring Registers Control Register Name: MON_CR (0x29) Access: Read/Write  MON_ON: Enable bit of the monitoring function 0: Monitoring function disabled 1: Monitoring function enabled  IT_RESET: Reset of the status register 0: No action 1: Reset the status registers MON_SR1 and MON_SR2 7654 3 2 1 0 ---- - - I T _ R E S E T M O N _ O N

2742B–PMGMT–03/04 VBAT1 Measure Register Name: MON_VBAT1_MEAS (0x00) Access: Read-only VBAT2 Measure Register Name: MON_VBAT2_MEAS (0x01) Access: Read-only USB Measure Register Name: MON_USB_MEAS (0x02) Access: Read-only VDDPSU Measure Register Name: MON_VDDPSU_MEAS (0x03) Access: Read-only 7654 3 2 1 0 MON_VBAT1_MEAS 7654 3 2 1 0 MON_VBAT2_MEAS 7654 3 2 1 0 MON_USB_MEAS 7654 3 2 1 0 MON_VDDPSU_MEAS

44 AT73C203

2742B–PMGMT–03/04 VOUT1 Measure Register Name: MON_VOUT1_MEAS (0x04) Access: Read-only VOUT2 Measure Register Name: MON_VOUT2_MEAS (0x05) Access: Read-only VOUT3 Measure Register Name: MON_VOUT3_MEAS (0x06) Access: Read-only VOUT4 Measure Register Name: MON_VOUT4_MEAS (0x07) Access: Read-only 7654 3 2 1 0 MON_VOUT1_MEAS 7654 3 2 1 0 MON_VOUT2_MEAS 7654 3 2 1 0 MON_VOUT3_MEAS 7654 3 2 1 0 MON_VOUT4_MEAS

2742B–PMGMT–03/04 VTE1 Measure Register Name: MON_VTE1_MEAS (0x08) Access: Read-only VTE2 Measure Register Name: MON_VTE2_MEAS (0x09) Access: Read-only VTS Measure Register Name: MON_VTS_MEAS (0x0A) Access: Read-only 7654 3 2 1 0 MON_VTE1_MEAS 7654 3 2 1 0 MON_VTE2_MEAS 7654 3 2 1 0 MON_VTS_MEAS

46 AT73C203

2742B–PMGMT–03/04 VBAT1 Under Limit Register Name: MON_VBAT1_UNDL (0x16) Access: Read/write VBAT1 Over Limit Register Name: MON_VBAT1_OVL (0x1B) Access: Read/write VBAT2 Under Limit Register Name: MON_VBAT2_UNDL (0x17) Access: Read/write VBAT2 Over Limit Register Name: MON_VBAT2_OVL (0x0C) Access: Read/write 7654 3 2 1 0 MON_VBAT1_UNDL 7654 3 2 1 0 MON_VBAT1_OVL 7654 3 2 1 0 MON_VBAT2_UNDL 7654 3 2 1 0 MON_VBAT2_OVL

2742B–PMGMT–03/04 USB Under Limit Register Name: MON_USB_UNDL (0x18) Access: Read/write USB Over Limit Register Name: MON_USB_OVL (0x1D) Access: Read/write VDDPSU Under Limit Register Name: MON_VDDPSU_UNDL (0x19) Access: Read/write VDDPSU Over Limit Register Name: MON_VDDPSU_OVL (0x0E) Access: Read/write 7654 3 2 1 0 MON_USB_UNDL 7654 3 2 1 0 MON_USB_OVL 7654 3 2 1 0 MON_VDDPSU_UNDL 7654 3 2 1 0 MON_VDDPSU_OVL

48 AT73C203

2742B–PMGMT–03/04 VOUT1 Under Limit Register Name: MON_VOUT1_UNDL (0x1A) Access: Read/write VOUT1 Over Limit Register Name: MON_VOUT1_OVL (0x1F) Access: Read/write VOUT2 Under Limit Register Name: MON_VOUT2_UNDL (0x1B) Access: Read/write VOUT2 Over Limit Register Name: MON_VOUT2_OVL (0x10) Access: Read/write 7654 3 2 1 0 MON_VOUT1_UNDL 7654 3 2 1 0 MON_VOUT1_OVL 7654 3 2 1 0 MON_VOUT2_UNDL 7654 3 2 1 0 MON_VOUT2_OVL

2742B–PMGMT–03/04 VOUT3 Under Limit Register Name: MON_VOUT3_UNDL (0x1C) Access: Read/write VOUT3 Over Limit Register Name: MON_VOUT3_OVL (0x11) Access: Read/write VOUT4 Under Limit Register Name: MON_VOUT4_UNDL (0x1D) Access: Read/write VOUT4 Over Limit Register Name: MON_VOUT4_OVL (0x12) Access: Read/write 7654 3 2 1 0 MON_VOUT3_UNDL 7654 3 2 1 0 MON_VOUT3_OVL 7654 3 2 1 0 MON_VOUT4_UNDL 7654 3 2 1 0 MON_VOUT4_OVL

50 AT73C203

2742B–PMGMT–03/04 VTE1 Under Limit Register Name: MON_VTE1_UNDL (0x1E) Access: Read/write VTE1 Over Limit Register Name: MON_VTE1_OVL (0x13) Access: Read/write VTE2 Under Limit Register Name: MON_VTE2_UNDL (0x1F) Access: Read/write VTE2 Over Limit Register Name: MON_VTE2_OVL (0x14) Access: Read/write VTS Under Limit Register Name: MON_VTS_UNDL (0x20 Access: Read/write VTS Over Limit Register Name: MON_VTS_OVL (0x15) Access: Read/write 7654 3 2 1 0 MON_VTE1_UNDL 7654 3 2 1 0 MON_VTE1_OVL 7654 3 2 1 0 MON_VTE2_UNDL 7654 3 2 1 0 MON_VTE2_OVL 7654 3 2 1 0 MON_VTS_UNDL 7654 3 2 1 0 MON_VTS_OVL

2742B–PMGMT–03/04 Interrupt/ Reset Mask Register 1 Name: MON_MR1 (0x21) Access: Read/Write  VBAT1: Enable VBAT1 Interrupt or Reset 0: Disables VBAT1 interrupt or global reset. 1: Enables VBAT1 interrupt or global reset.  VBAT2: Enable VBAT2 Interrupt 0: Disables VBAT2 interrupt or global reset. 1: Enables VBAT2 interrupt or global reset.  USB: Enable USB Interrupt 0: Disables USB interrupt or global reset. 1: Enables USB interrupt or global reset.  VDDPSU: Enable VDDPSU Interrupt 0: Disables VDDPSU interrupt or global reset. 1: Enables VDDPSU interrupt or global reset.  VOUT1: Enable VOUT1 Interrupt 0: Disables VOUT1 interrupt or global reset. 1: Enables VOUT1 interrupt or global reset.  VOUT2: Enable VOUT2 Interrupt 0: Disables VOUT2 interrupt or global reset. 1: Enables VOUT2 interrupt or global reset.  VOUT3: Enable VOUT3 Interrupt 0: Disables VOUT3 interrupt or global reset. 1: Enables VOUT3 interrupt or global reset.  VOUT4: Enable VOUT4 Interrupt 0: Disables VOUT4 interrupt or global reset. 1: Enables VOUT4 interrupt or global reset. 7654 3 2 1 0 VOUT4 VOUT3 VOUT2 VOUT1 VDDPSU USB VBAT2 VBA T1

52 AT73C203

2742B–PMGMT–03/04 Interrupt/ Reset Mask Register 2 Name: MON_MR2 (0x22) Access: Read/Write  VTE1: Enable VTE1 Interrupt or Reset 0: Disables VTE1 interrupt or global reset. 1: Enables VTE1 interrupt or global reset.  VTE2: Enable VTE2 Interrupt 0: Disables VTE2 interrupt or global reset. 1: Enables VTE2 interrupt or global reset.  VTS: Enable VTS Interrupt 0: Disables VTS interrupt or global reset. 1: Enables VTS interrupt or global reset.  VOUT1COMP: Enable VOUT1COMP Interrupt or Reset 0: Disables VOUT1COMP interrupt or global reset. 1: Enables VOUT1COMP interrupt or global reset.  VOUT2COMP: Enable VOUT2COMP Interrupt or Reset 0: Disables VOUT2COMP interrupt or global reset. 1: Enables VOUT2COMP interrupt or global reset.  VOUT3COMP: Enable VOUT3COMP Interrupt or Reset 0: Disables VOUT3COMP interrupt or global reset. 1: Enables VOUT3COMP interrupt or global reset.  VOUT4COMP: Enable VOUT4COMP Interrupt or Reset 0: Disables VOUT4COMP interrupt or global reset. 1: Enables VOUT4COMP interrupt or global reset. 7 654 3 2 1 0 - VOUT4COMP VOUT3COMP VOUT2COMP VOUT1COMP VTS VTE2 VTE1

2742B–PMGMT–03/04 Interrupt/ Reset Selection Register 1 Name: MON_IR1 (0x23) Access: Read/Write  VBAT1: Select for VBAT1 Interrupt or Reset 0: Interrupt selected for VBAT1 1: Global reset selected for VBAT1.  VBAT2: Select for VBAT2 Interrupt or Reset 0: Interrupt selected for VBAT2 1: Global reset selected for VBAT2.  USB: Select for USB Interrupt or Reset 0: Interrupt selected for USB 1: Global reset selected for USB.  VDDPSU: Select for VDDPSU Interrupt or Reset 0: Interrupt selected for VDDPSU 1: Global reset selected for VDDPSU.  VOUT1: Select for VOUT1 Interrupt or Reset 0: Interrupt selected for VOUT1 1: Global reset selected for VOUT1.  VOUT2: Select for VOUT2 Interrupt or Reset 0: Interrupt selected for VOUT2 1: Global reset selected for VOUT2.  VOUT3: Select for VOUT3 Interrupt or Reset 0: Interrupt selected for VOUT3 1: Global reset selected for VOUT3.  VOUT4: Select for VOUT4 Interrupt or Reset 0: Interrupt selected for VOUT4 1: Global reset selected for VOUT4. 7 654 3 2 1 0 VOUT4 VOUT3 VOUT2 VOUT1 VDDPSU USB VBAT2 VBAT1

54 AT73C203

2742B–PMGMT–03/04 Interrupt/ Reset Selection Register 2 Name: MON_IR2 (0x24) Access: Read/Write  VTE1: Select for VTE1 Interrupt or Reset 0: Interrupt selected for VTE1 1: Global reset selected for VTE1.  VTE2: Select for VTE2 Interrupt or Reset 0: Interrupt selected for VTE2 1: Global reset selected for VTE2.  VTS: Select for VTS Interrupt or Reset 0: Interrupt selected for VTS 1: Global reset selected for VTS.  VOUT1COMP: Select for VOUT1COMP Interrupt or Reset 0: Interrupt selected for VOUT1COMP 1: Global reset selected for VOUT1COMP .  VOUT2COMP: Select for VOUT2COMP Interrupt or Reset 0: Interrupt selected for VOUT2COMP 1: Global reset selected for VOUT2COMP .  VOUT3COMP: Select for VOUT3COMP Interrupt or Reset 0: Interrupt selected for VOUT3COMP 1: Global reset selected for VOUT3COMP .  VOUT4COMP: Select for VOUT4COMP Interrupt or Reset 0: Interrupt selected for VOUT4COMP 1: Global reset selected for VOUT4COMP . 7 654 3 2 1 0 - VOUT4COMP VOUT3COMP VOUT2COMP VOUT1COMP VTS VTE2 VTE1

2742B–PMGMT–03/04 Status Register 1 Name: MON_SR1 (0x25) Access: Read-only  VBAT1: VBAT1 Error 0 = No out-of-limit event on VBAT1 since the last reset. 1 = An out-of-limit event on VBAT1 has occurred since the last reset.  VBAT2: VBAT2 Error 0: No out-of-limit event on VBAT2 since the last reset. 1: An out-of-limit event on VBAT2 has occurred since the last reset.  USB: US Error 0: No out-of-limit event on USB since the last reset. 1: An out-of-limit event on USB has occurred since the last reset.  VDDPSU: VDDPSU Error 0: No out-of-limit event on VDDPSU since the last reset. 1: An out-of-limit event on VDDPSU has occurred since the last reset. V O U T 1 : V O U T 1 E r r o r 0: No out-of-limit event on VOUT1 since the last reset. 1: An out-of-limit event on VOUT1 has occurred since the last reset. V O U T 2 : V O U T 2 E r r o r 0: No out-of-limit event on VOUT2 since the last reset. 1: An out-of-limit event on VOUT2 has occurred since the last reset. V O U T 3 : V O U T 3 E r r o r 0: No out-of-limit event on VOUT3 since the last reset. 1: An out-of-limit event on VOUT3 has occurred since the last reset. V O U T 4 : V O U T 4 E r r o r 0: No out-of-limit event on VOUT4 since the last reset. 1: An out-of-limit event on VOUT4 has occurred since the last reset. 7 654 3 2 1 0 VOUT4 VOUT3 VOUT2 VOUT1 VDDPSU USB VBAT2 VBAT1

56 AT73C203

2742B–PMGMT–03/04 Status Register 2 Name: MON_SR2 (0x26) Access: Read-only  VTE1: VTE1 Error 0: No out-of-limit event on VTE1 since the last reset. 1: An out-of-limit event on VTE1 has occurred since the last reset  VTE2: VTE2 Error 0: No out-of-limit event on VTE2 since the last reset. 1: An out-of-limit event on VTE2 has occurred since the last reset V T S : V T S E r r o r 0: No out-of-limit event on VTS since the last reset. 1: An out-of-limit event on VTS has occurred since the last reset  VOUT1COMP: VOUT1COMP Error 0: No out-of-limit event on VOUT1COMP since the last reset. 1: An out-of-limit event on VOUT1COMP has occurred since the last reset  VOUT2COMP: VOUT2COMP Error 0: No out-of-limit event on VOUT2COMP since the last reset. 1: An out-of-limit event on VOUT2COMP has occurred since the last reset  VOUT3COMP: VOUT3COMP Error 0: No out-of-limit event on VOUT3COMP since the last reset. 1: An out-of-limit event on VOUT3COMP has occurred since the last reset  VOUT4COMP: VOUT4COMP Error 0: No out-of-limit event on VOUT4COMP since the last reset. 1: An out-of-limit event on VOUT4COMP has occurred since the last reset 7 654 3 2 1 0 - VOUT4COMP VOUT3COMP VOUT2COMP VOUT1COMP VTS VTE2 VTE1

Table 5. Current Source Control (VTExON = 1, x = 1 or 2)

58 AT73C203

Table 5. Current Source Control (VTExON = 1, x = 1 or 2) (Continued)

2742B–PMGMT–03/04 Charge Control Registers Charger Mode Register Name: CHA_MR (0x47) Access: Write-only  CHA_PH: Charger phase control 0: Sets the Charger control off. 1: Sets Battery1 to pre-conditioning charge phase. 2: Sets Battery2 to pre-conditioning charge phase. 3: Sets Battery1 and Battery2 to pre-conditioning charge phase. 4: Sets Battery1 to fast charge phase. 5: Sets Battery2 to fast charge phase. 6: Sets Battery1 to “pulsed” charge phase. 7: Sets Battery2 to “pulsed” charge phase. 8: Sets Battery1 to fast charge phase and Battery 2 to pre-conditioning charge phase. 9: Sets Battery2 to fast charge phase and Battery 1 to pre-conditioning charge phase. A: Sets Battery1 to “pulsed” charge phase and Battery 2 to pre-conditioning charge phase. B: Sets Battery2 to “pulsed” charge phase and Battery 1 to pre-conditioning charge phase. C: Not used D: Not used E: Not used F: Not used  CHA_USB_PSU: Charger USB/PSU selection 0: PSU is selected. 1: USB is selected.  CHA_CURR: Charger current control 0: Sets the current to 100mA. 1: Sets the current to 200mA. 2: Sets the current to 300mA. 3: Sets the current to 500mA. 7 6 54 32 1 0 CHA_CURR CHA_USB_PSU CHA_PH

60 AT73C203

2742B–PMGMT–03/04 Charger Status Register Name: CHA_SR (0x41) Access: Read-only  CHA_PH: Charger phase control 0: The Charger control is off. 1: Battery1 in pre-conditioning charge phase. 2: Battery2 in pre-conditioning charge phase. 3: Battery1 and Battery2 in pre-conditioning charge phase. 4: Battery1 in fast charge phase. 5: Battery2 in fast charge phase. 6: Battery1 in “pulsed” charge phase. 7: Battery2 in “pulsed” charge phase. 8: Battery1 in fast charge phase and Battery 2 in pre-conditioning charge phase. 9: Battery2 in fast charge phase and Battery 1 in pre-conditioning charge phase. A: Battery1 in “pulsed” charge phase and Battery 2 in pre-conditioning charge phase. B: Battery2 in “pulsed” charge phase and Battery 1 in pre-conditioning charge phase. C: Not used D: Not used E: Not used F: Not used  CHA_USB_PSU: Charger USB/PSU selection 0: PSU selected. 1: USB selected.  CHA_CURR: Charger current control 0: Current selected: 100mA. 1: Current selected: 200mA. 2: Current selected: 300mA. 3: Current selected: 500mA.  CHA_ST_TIMER: Charger safety timer status 0: No interrupt or timer disabled. 1: An interrupt (end of timer) has occurred. 76 5 4 3 2 1 0 CH_ST_TIMER CHA_CURR CHA_USB_PSU CHA_PH

2742B–PMGMT–03/04 Charger Control Register Name: CHA_CR (0x40) Access: Write-only  REA_WDOG: Rearm the watchdog 0: No action 1: Rearms the watchdog  STA_TIM: Start the safety timer 0: No action 1: Starts the safety timer  RES_TIM_IT: Reset the safety timer interrupt 0: No action 1: Resets the safety timer interrupt  RES_CHA_IT: Reset the charger interrupt 0: No action 1: Resets the charger interrupt 7654 3 2 1 0 ---- R E S _ C H A _ I T R E S _ T I M _ I T S T A _ T I M R E A _ W D O G

62 AT73C203

2742B–PMGMT–03/04 Charger Safety Timer Control Register Name: CHA_STR_CR (0x42) Access: Write-only  CHA_STR_CR: Charger safety timer control register Safety timer = CHA_STR_PR x 210 sec. Writing 0x00 in this register disables the safety timer. Thus the safety timer can be programmed from 0 to 53477 sec. (14h 51min). Charger Safety Timer Status Register Name: CHA_STR_SR (0x43) Access: Read-only  CHA_STR_SR: Charger safety timer register Safety timer = CHA_STR_SR x 210 sec. It gives the status of the internal counter from 0 to 53477 sec. (14h 51min). Charger Minimum On Time Register Name: CHA_TMINON (0x44) Access: Read/Write  CHA_TMINON: Minimum on time for pulsed charge phase Minimum on-time = CHA_TMINON *2 ms Thus the minimum on-time can be tuned from 0 to 510 ms. 7654 3 2 1 0 CHA_STR 7654 3 2 1 0 CHA_STR_SR 7654 3 2 1 0 CHA_TMINON

2742B–PMGMT–03/04 Charger Minimum Off Time Register Name: CHA_TMINOFF (0x45) Access: Read/Write  CHA_TMINOFF: Minimum on time for pulsed charge phase Minimum on-time = CHA_TMINOFF *2 ms Thus the minimum off-time can be tuned from 0 to 510 ms. Charger Trim Register Name: CHA_TR (0x46) Access: Read/Write  CHA_VOLT_TRIM: Charger voltage trimming 0: Set the regulation voltage to 4.20V (typical). 1: Set the regulation voltage to 4.17V (typical). 2: Set the regulation voltage to 4.13V (typical). 3: Set the regulation voltage to 4.10V (typical). 4: Set the regulation voltage to 4.23V (typical). 5: Set the regulation voltage to 4.26V (typical). 6: Set the regulation voltage to 4.30V (typical). 7: Set the regulation voltage to 4.07V (typical).  CHA_DUTY: Charger duty cycle for pulsed charge phase Duty ratio threshold of “on” cycles to “off” cycles 0: Duty cycle threshold: 1/4 1: Duty cycle threshold: 1/8 2: Duty cycle threshold: 1/16 3: Duty cycle threshold: 1/32 4: Duty cycle threshold: 1/64 5: Duty cycle threshold: 1/128 6: Duty cycle threshold: 1/256 7: Duty cycle threshold: 1/512 7654 3 2 1 0 CHA_TMINOFF 7654 3 2 1 0 - - CHA_DUTY CHA_VOLT_TRIM

64 AT73C203

Table 6. Digital Pin Description List CHG_INHIBIT Input gnddig - vout3 Inhibit charger input.

gnddig - vout3 Clock input from the microprocessor.

66 AT73C203

gnddig - vsauv Pin for test. gnddig - vsauv Pin for test. Table 7. For Digital Pins Referred to VOUT3

Table 8. For Digital Pins Referred to VSAUV

68 AT73C203

2742B–PMGMT–03/04

Electrical Characteristics

Power Switch The power switch control block drives external dual PMOS devices to multiplex VDDPSU from battery 1 (BAT1), battery 2 (BAT2) and an AC/DC Power supply unit (PSUIN). The purpose of this cell is to guarantee a sufficient supply for VDDPSU and to limit drops even during switchover. Inrush current from source to VDDPSU must be avoided. Back powering from a selected power source to all other power sources must be avoided. Figure 13. Power Switch Controller Note: 1. Print is internal to the AT73C203.

2742B–PMGMT–03/04 Automatic Selection When the power switch digital control block is off, VDDPSU is set to the high impedance state. The supply of this cell comes from an analog OR done with four external Schottky diodes connected to BAT_1PIO, BAT2_PIO, PSU_PIO and USB_IN. The system should respect the “Universal Serial Bus Specification”, especially section 7.2.4.1, which specifies that the maximum equivalent load seen by the USB is 10 µF in parallel with 44 ohms. When the cell is on, the power switch must automatically select the correct power source. PSU is a non current-limited 5V supply output. BAT2 is a Lithium Ion battery and can be removed. BAT1 is a Lithium Ion battery and is always soldered to the PCB. A selection priority rule is used: PSU > BAT2 > BAT1 When the PSU is plugged in, it is selected by default. If the PSU is not plugged in, BAT2 is used if it is present and has enough voltage. If PSU is not plugged in, and BAT2 is unplugged or below the flat threshold, BAT1 is used if BAT1’s voltage is high enough. For a critical situation on any of the power sources, the automatic switching shall ensure that V DDPSU stays within specifications. This means that the automatic supply selection FETs must be switched as quickly as possible, ideally with a maximum switchover of 1 µs (max: 5 µs) and guarantee that the already enabled FETs are switched off before the newly selected FETs are switched on. The faster the switching, the smaller the capacitance required to hold up V DDPSU (target: 100 µF max). To handle all cases, fast analog comparators on each input with appropriate hysteresis (in voltage and in time) must be used within the AT73C203. To meet the 5 µs requirement, the comparator must be fast enough to detect when a source is disconnected (or a low voltage threshold is reached) but slow enough when detecting that a new source is plugged in (depending on contact bounce during the insertion/removal of a power source). The slow delay is done with the 10 kHz internal oscillator. At start-up, the cell is off and is turned on by the internal digital block. With PWS_CR register (bits accessible via SPI), the application processor can force an input source to be selected. This may be used for testing the AT73C203 or by the appli- cation processor to force use of one of the batteries. Using PWS_SR register, the application processor can read which supply is currently selected by the AT73C203. If one input is not used (PSU, BAT1 or BAT2), it can be grounded. The corresponding unused output (GAPSU, GABAT1 or GABAT2) can be left unconnected in this case.

70 AT73C203

Table 9. Power Switch Controller Electrical Specifications

The SPI interface between the system and the AT73C203 is detailed in Figure 14. Figure 14. SPI Architecture

72 AT73C203

Figure 15. SPI Protocol In case of a read operation, SDO first provides the contents of the read register, MSB. idle state, even if the transfer does not succeed. rising edge shifts SDO output bits.

Timing for SPI Interface SPI interface timings are shown in Figure 16. Figure 16. SPI Interface Timing Diagram Note: 1. t SYSCLK = system clock period. The frequency of SYS_CLK must be at least two times superior to that of SCLK. before the first SPI access. The minimum time for the USIM is one system clock period (tSYSCLK ). access will be taken into account. The same approach is used for the charger registers but with 10 kHz. Table 10. SPI Timing Parameters

74 AT73C203

and 1.65V. The entire cell is optimized for 1.20V. When the cell is off, the output is pulled to ground. Figure 17. Rail1 Schematic Table 11. Rail1 External Components

Rail1 can operate up to a load of 1.5 A if the R1 resistor is replaced by 80 mΩ ± 2%. Rail 1 can also operate at VIN = 2.85V. Table 12. Rail1 Electrical Specifications

76 AT73C203

When the cell is off, the output is in high impedance state. Figure 18. Rail2 Schematic Table 13. Rail2 External Components

Rail 2 can also operate at VIN = 2.85V. Table 14. Rail2 Electrical Specifications

78 AT73C203

Rail3 is a programmable buck DC/DC converter followed by a linear drop out regulator. When the cell is off, the output is pulled to ground. Figure 19. Rail3 Schematic Table 15. Rail3 External Components

Rail 3 can also operate at VIN = 2.85V. Table 16. Rail3 Electrical Specifications

80 AT73C203

When the cell is off, the output is in high impedance state. Figure 20. Rail4 Schematic Table 17. Rail4 External Components

Rail 4 can also operate at VIN = 2.85V. Table 18. Rail4 Electrical Specifications

82 AT73C203

Figure 21. 900 kHz Oscillator Distribution

All the controls are performed via registers accessed via the SPI. Figure 22. Voltage and Temperature Monitoring Architecture

8 Bits ADC

84 AT73C203

2742B–PMGMT–03/04 Analog to Digital Converter and Multiplexer An internal 8-bit analog to digital converter is used to measure the different voltages. The analog to digital converter has eleven internal inputs listed as follows: V BAT1 (internal battery) V BAT2 (external battery)  USB (USB supply) V DDPSU (output of the power switch) V OUT1 (output of Rail1) V OUT2 (output of Rail2) V OUT3 (output of Rail3) V OUT4 (output of Rail4) V TE1 (voltage on thermistor 1) V TE2 (voltage on thermistor 2) V TS (output of the internal temperature sensor) An external capacitor (C21) on VMES pin enables filtering of the ADC input and provides immunity to high frequency noise. These inputs are multiplexed into the analog to digital converter. This has a resolution of eight bits. The basic input range is 0.6V to 2.25V (typical) but the inputs have built-in attenuators to allow measurements without external components. Take note that no attenuator is present for V OUT1 , VOUT4 , VTE1 , VTE2 and VTS .

ues of less than 1%. All ratios will be confirmed during the design process. Table 19. Bridge Monitoring (Attenuators) Electrical Specifications Table 20. Temperature Sensor Electrical Specifications

86 AT73C203

Figure 23. Typical Sensor Characteristics these eight values to reduce noise before moving to the next input. Average values from these inputs are stored in value registers. See Table 21. stored in an external flash memory, the software can remove the internal offset. Table 21. Value Registers

ital core compares the measurement with programmed limits stored in the limit registers. on page 87), which can be read over the SPI to flag an out-of-limit condition. mask and interrupt/reset registers. See Table 24. resistance of the NTC is proportional to the temperature. integrated into the AT73C203. can then be estimated by the microprocessor. Table 22. Limit Registers Table 23. Status Registers Table 24. Mask and Interrupt /Reset Registers

88 AT73C203

The 6-bit DAC parameters are shown in Table 25 below. and VOUT4 ) is used as a real time supply rail brownout detector for a drop. When the cell is off, the output is pulled to ground. Figure 24. USIM Regulator Table 25. Current DAC Electrical Specifications Table 26. Comparator Electrical Specifications

The USIM 1.8V regulator complies with ETS TS 102 221, sections 5 and 6. The USIM 2.8V regulator complies with ETS TS 102 221, sections 5 and 6. Table 27. USIM 1.8V Regulator Electrical Specifications Table 28. USIM 2.8V Regulator Electrical Specifications

90 AT73C203

All these registers are detailed in Table 4, “AT73C203 User Interface,” on page 22. Figure 25 shows the major blocks required in the interface. Figure 25. USIM Interface Digital Architecture

2742B–PMGMT–03/04 Operating Conditions Clock The clock applied to the SIM card is generated by the terminal from the system clock sys_clock (see “SIM Clock Generation” on page 92). The clock signal can be enabled or disabled by register CLKEN. Voltage Both class B and C are supported (ETSI 102.221 section 5.2, 5.3). They correspond to 3V and 1.8V nominal voltage, respectively. The operating class is selected by register VSEL. The first operating condition applied to the card by the terminal should be class C (1.8V). If the card does not provide an Answer-To-Reset (ATR), class B (3V) should be applied to the card (ETSI 102.221 section 6.2). This should be managed by software. Presence The presence of card status is written in the register PRES. An interrupt is generated if the bit PRES is changing. This interrupt can be masked in the interrupt mask register. This interrupt is reset with the RSTPRES bit in control regis- ter SIM_CR. Initial Communication Establishment Procedures Reset The reset register SRESET is directly connected to output pin sim_reset. Cold Reset and Activation In order to activate the SIM card, electrical circuits should be activated in the following order: 1. SIM card voltage should be chosen with VSEL (SIM_MR). 2. SIM clock should be started by writing 1 to CLKEN (SIM_CR). 3. I/O line should be activated by setting ACTIVE in Control Register SIM_CR. 4. After a minimum of 400 sim_clock cycles, the application should rise SRESET. The application should be able to detect an absence of ATR after 40000 sim_clock cycles. This can be done by using the timer with an initial value of 108 (108 x 372 = 40176 where 372 is the default baud rate divisor). Warm Reset A warm reset is done by writing to register SRESET (SIM_CR). The application has to respect a minimum of 400 sim_clock cycles between falling and rising edges of the pin sim_reset. As for a cold reset, the absence of ATR should be managed by the application. CLKEN 0 1 SIM Clock Disabled Enabled VSEL 00 01 10 11 Selected Voltage Disabled Disabled 1.8V 2.8V PRES 0 1 Presence of the SIM Card Not present Present

92 AT73C203

done by using the time-out counter.

1. SIM clock should be stopped by writing 0 to CLKEN.
2. I/O line should be deactivated by resetting ACTIVE in Control Register SIM_CR.
3. SIM card voltage should be disabled with register VSEL.

quency. This value can be changed afterwards (see below). grammed in the timer by the application. The required value is 9600 ETUs. The ATR must be checked by software. programmed in 4 bits register SIM_CDR. Figure 26. USIM Clock Generation

2742B–PMGMT–03/04 Speed Enhancement The baud rate can be programmed in the 7-bit register BDR. The etu is one bit rate clock cycle. The baud rate = f/(div1 x div2) where f is the SIM clock frequency. div1 is coded on BDR[6]. div2 is coded on BDR[5:0]. Before changing the baud rate division factor, the values supported by the SIM card have to be checked by doing a PPS operation as defined in ISO 7816-3 section 7. Extra Guardtime An extra guardtime can be programmed when sending characters to the card. The 8-bit register SIM_TTGR (see “Transmitter Time Guard Register” on page 41) allows an extra time guard from 0 to 255 ETU. Transmission Protocol The SIM interface handles all specific requirements defined in ISO7816 T = 0 and T = 1 protocol types. It has also some specific features such as maximum character repetition. Two 16-byte FIFOs are provided in order to free CPU resources, one for reception and one for transmission. Two 4-bit pointers in the Buffer Status Register (SIM_BSR) indi- cate how many characters are present in the FIFOs, RXPTR for receiver FIFO, TXPTR for transmitter FIFO. Reception The receiver can be reset by using the RSTRX command in SIM_CR. This empties the Rx FIFO and the receiver is waiting for a new valid character. When a complete character is received, it is transferred to the receiver FIFO and the RXRDY status bit in SIM_CSR is set. If the FIFO is full, the RXFULL status bit in SIM_CSR is set and if a new character is received, the last character in the FIFO is overwritten and the OVRE status bit in SIM_CSR is set. The receiver FIFO is accessible through Receiver Holding Register (SIM_RHR). In the following, an access to SIM_RHR means an access to the receiver FIFO. T = 0 Upon detection of a start bit, the following data byte is shifted in the Receiver Holding Register (SIM_RHR) when the shift is completed and the parity is checked. If a parity error is detected, the PARE bit is set in SIM_CSR and a low error signal is sent for one Elementary Time Unit (ETU), 10.5 ETUs after the start bit. This error signal is sent from the receiver to the transmitter but can be inhibited by setting the bit IRXNACK in the reg- ister SIM_MR. 1 bit 6 bits BDR[6] BDR[5:0] BDR[6] 0 1 div1 31 32 BDR[5:0] 0 1 - 63 div2 64 BDR[5:0]

94 AT73C203

2742B–PMGMT–03/04 T = 1 Upon detection of a start bit, the following data byte is shifted in the Receiver Holding Register (SIM_RHR) when the shift is completed and the parity is checked. If a parity error is detected, the PARE bit is set in status register SIM_CSR. In this protocol there is only one stop bit.  Time-out This function allows an idle condition on reception to be detected. The maximum delay for which the terminal should wait for a new character to arrive is programmed in SIM_RTOR (Receiver Time-out). When this register is set to 0, no time-out is detected. Otherwise, the receiver waits for a first character and then initializes a counter, which is decremented at each bit period and reloaded at each byte reception. When the counter reaches 0, the TIMEOUT bit in SIM_MSR is set. The user can restart the wait for a first character with the STTO (Start Time-out) bit in SIM_CR. Transmission The transmitter can be reset by using the RSTTX command in SIM_CR. This will empty the Tx FIFO and the transmitter will be inactive until a new character has to be sent. The transmitter FIFO is accessible through the Transmit Holding Register (SIM_THR). When a character is written to SIM_THR (Transmit Holding), it is transferred to the Shift Register as soon as it is empty. Whenever the FIFO is not full, the TXRDY status bit in SIM_CSR is set. If the Transmit Shift Register and the transmitter FIFO are both empty, the TXEMPTY bit in SR is set. If the FIFO is full and a new character is written to SIM_THR, the last character in the FIFO will be overwritten. In protocol T=0, if the SIM card sends back a Non-Acknowledgment signal, the status bit TXNACK in register SIM_CSR is set. It can be reset by using the RSTTXNACK com- mand in SIM_CR.  Time-guard The time-guard function allows the transmitter to insert an idle state on the IO line between two characters. The duration of the idle state is programmed in SIM_TTGR (Transmitter Time-guard). When this register is set to zero, no time-guard is generated. Otherwise, the transmitter holds a high level on SIM_IO after each transmitted byte for the number of bit periods programmed in SIM_TTGR. Timings T = 0 The minimum interval between two consecutive characters is at least 12 ETUs. If two consecutive characters are sent in opposite directions, the minimum interval of time should be 16 ETUs. This is automatically managed by the hardware. WWT (Work waiting time) overflow can be managed by the 16-bit time-out counter. If 65536 cycles are not enough, the timer can be rearmed by using the RETTO command in register in SIM_CR. T = 1 The minimum interval between the leading edge of the start bits of two consecutive characters is at least 11 etus. The Block Guard Time (22 etus) is automatically managed by hardware. CWT (Character waiting time) and BWT (Block waiting time) can be managed by the time-out counter as for WWT in protocol T=0.

2742B–PMGMT–03/04 Character Repetition for T = 0Protocol T = 0 allows character repetition.  Reception When IRXNACK is set and a parity error is detected, an error signal is not sent. The received byte is available in the SIM_RHR register and the RXRDY bit is set. If IRXNACK = 0, the number of character repetitions depends on Disable Successive Non-Acknowledgment (DSRXNACK) bit and MAX_ITERATION bits, both in SIM_MR. MAX_ITERATION is a 3-bit field configurable with a value between 0 and 7. This implies that a character can be repeated up to eight times. If DSRXNACK = 0, an error signal is sent on the I/O line as soon as a parity error occurs in the received character. If DSRXNACK = 1, successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a error signal on the SIM_IO line. As soon as this value is reached, no additional error signal is sent on the I/O line. The flag ITERATION is asserted. To reset the ITERATION (SIM_MSR) flag, the RSIT bit must be set in the Control Regis- ter (SIM_CR).  Transmission A character repetition can be executed if the MAX_ITERATION field in SIM_MR is differ- ent from 0. If MAX_ITERATION = 0, no repetition is done. If MAX_ITERATION is different from zero and no parity error has been detected, no rep- etition is done. If MAX_ITERATION is different from zero and a parity error has been detected, the transmitter re-sends the corrupted value. If a parity error is still detected, the corrupted value is sent as many times as the value loaded in the MAX_ITERATION field. If the number of repetitions of the corrupted value reaches the value loaded in the MAX_ITERATION field, the ITERATION (SIM_MSR) flag is set. The transmitter is dis- abled until the ITERATION flag is reset. If at some stage during the repetition sequence, no error parity is detected, repetition is stopped. To reset the ITERATION (SIM_MSR) flag, the RSIT command can be used, but in that case the transfer will continue if the FIFO is not empty and not all characters would have been correctly sent. That's why it is recommended to reset the transmitter with the RSTTX command in the Control Register (SIM_CR). Error Counter If errors occurred during a transfer, it is possible to obtain the total number of errors by reading the register in SIM_NER. This is a read-only register reset by a read action. Up to 255 errors can be recorded. Interrupts All interrupts can be masked in registers SIM_IMR1 and SIM_IMR2 RXRDY A character has been received. An interrupt occurs when status bit RXRDY in SIM_CSR is set. Reset of status bit causes reset of interrupt.

96 AT73C203

2742B–PMGMT–03/04 RXFULL The receiver FIFO is full. An interrupt occurs when status bit RXFULL in SIM_CSR is set. Reset of status bit causes reset of interrupt. OVRE The last character in the receiver FIFO has been overwritten. An interrupt occurs when status bit OVRE in SIM_CSR is set. Reset of status bit causes reset of interrupt. PA RE A parity error occurred. An interrupt occurs when status bit PARE in SIM_CSR is set. Reset of status bit causes reset of interrupt. TXRDY The transmitter FIFO has one byte space left. An interrupt occurs when status bit TXRDY in SIM_CSR is set. Reset of status bit causes reset of interrupt. TXEMPTY All characters have been transmitted. An interrupt occurs when status bit TXEMPTY in SIM_CSR is set. Reset of status bit causes reset of interrupt. TXNACK An error bit has been received. An interrupt occurs when status bit TXNACK in SIM_CSR is set. Reset of status bit causes reset of interrupt. TIMEOUT The timer has expired. An interrupt occurs when status bit TIMEOUT in SIM_MSR is set. Reset of status bit causes reset of interrupt. ITERATION The maximum iteration number has been reached. An interrupt occurs when status bit ITERATION in SIM_MSR is set. Reset of status bit causes reset of interrupt. PRES The SIM card has been removed or inserted. An interrupt occurs when status bit PRES in SIM_MSR is changing. RSTPRES command in register SIM_CR causes reset of interrupt. RXHALF The receiver FIFO is half full. An interrupt occurs when receiver FIFO pointer RXPTR goes from 7 to 8. Reading SIM_BSR causes reset of interrupt. TXHALF The transmitter FIFO is half full. An interrupt occurs when transmitter FIFO pointer TXPTR goes from 9 to 8. Reading SIM_BSR causes reset of interrupt.

application processor (the application processor is not powered up). registers accessed via the SPI. Figure 27. Charger Control Schematic

98 AT73C203

terminated if the charge timer expires or if the voltage of battery 1 goes above 3.8V. the digital core is off and battery 1 is charged (25 mA) through the USB up to 4.1V. Figure 28. Stand-alone Mode Table 29. Charger Components

default the charge phase is stopped when the application processor wakes up. function that the operating temperature is within allowable limits for battery charging. Figure 29. Controlled Mode the PSU or USB source. Precondition current is set to 25 mA. registers included in the monitoring function. cessor should put the charger into the fast charge phase. charge phase at the same time.

100 AT73C203

2742B–PMGMT–03/04 The fast charge is automatically stopped when the battery voltage reaches the regula- tion voltage. The regulation voltage can be trimmed. By default, the voltage is 4.2V. When this voltage is reached an interrupt is sent to warn the microprocessor. A safety timer (CHA_STR_CR) can be launched during this phase. Pulsed Charge Phase To enable the pulsed charge phase, the application processor must use the charger control register. Note that battery 1 and battery 2 can not be in pulsed charge phase at the same time. The charger control uses a hysteretic algorithm with minimum on-times and minimum off-times of the external PMOS. These minimum on-times and off-times can be pro- grammed via registers CHA_TMINON and CHA_TMINOFF. The battery voltage is sampled every 0.3 millisecond (typical). If the battery voltage is less than the battery regulation voltage, the external PMOS FET either turns on or, if already on, remains on. If the battery voltage is greater than, or equal to, the regulation voltage threshold, the FET either turns off or, if already off, remains off until the next sample. At the beginning of the pulsed charge phase, the current stays on for many consecutive cycles between single off periods. As the battery continues to charge, the percentage of time spent in the “current-on” mode decreases. At the end of the pulsed phase, the cur- rent stays off for many cycles between single “on” pulses. This phase is automatically stopped when the duty ratio of “on” cycles to “off” cycles falls below a threshold which must be programmed trough register CHA_TR. Additionally, an interrupt is sent to warn the microprocessor. For safety, a timer (CHA_STR_CR) can be launched during this phase. If this timer expires, an interrupt is launched and the pulsed charge phase is automati- cally stopped. The “Start-up State Machine Pulsed Charge Phase” shown in Figure 30 on page 101 presents a summary of the pulsed charge phase. Refer also to the “State Machine Description” on page 15 for more information on the pulsed charge phase. The parameters (CHA_TMINON, CHA_TMINOFF and CHA_TR) can be trimmed in order to be adapted to the battery. To properly choose the parameters, a test must been done with the real battery. At the end of top-off mode, it is preferable to use a small cur- rent (100 mA). A good default value seems to be 200 ms for CHA_TMINON and CHA_TMINOFF and a duty cycle threshold of 1/64.

Figure 30. Start-up State Machine Pulsed Charge Phase been rearmed, the charge is stopped.

102 AT73C203

Table 30. Charger Control Electrical Specifications

Table 31 gives power dissipation values (estimated). Quiescent Current The AT73C203 has two modes: off and active mode. maximum current of the AT73C203 in this mode must be below 220 µA. Typical measure on Rev C: 70 µA. Table 31. Power Dissipation (Estimated)

104 AT73C203

Figure 31. 10 x 10 balls, 0.8mm Pitch BGA Package on 9 x 9mm Body Size for AT73C203

Figure 32. AT73C203 Package Specification

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