Download PDFAT49SV163D ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 30
Technical content
Features
- Single Voltage Read/Write Operation: 1.65V to 1.95V Access Time – 80 ns Sector Erase Architecture – Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout – Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout Fast Word Program Time – 10 µs Fast Sector Erase Time – 100 ms Suspend/Resume Feature for Erase and Program – Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Word in the Non-suspending Sectors by Suspending Programming of Any Other Word Low-power Operation – 10 mA Active – 15 µA Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Write Protection and Accelerated Program Operation RESET Input for Device Initialization Sector Lockdown Support TSOP and CBGA Package Options Top or Bottom Boot Block Configuration Available 128-bit Protection Register Minimum 100,000 Erase Cycles Common Flash Interface (CFI) 1. Description The AT49SV163D(T) is a 1.8-volt 16-megabi t Flash memory organized as 1,048,576 words of 16 bits each. The memory is di vided into 39 sectors for erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see “Sector Lockdown” on page 6). To increase the flexibility of the device, it contains an Erase Suspe nd and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. The VPP pin provides data protection. When the VPP input is below 0.4V, the program and erase functions are inhibited. When V PP is at 1.65V or above, normal program and erase operations can be performed. With V PP at 10.0V, the program (Dual-word Program command) operation is accelerated. 16-megabit (1M x 16) 1.8-volt Only Flash Memory AT49SV163D AT49SV163DT 3656A–FLASH–2/07
3656A–FLASH–2/07 AT49SV163D(T)
2.1 TSOP Top View (Type 1)
2.2 CBGA Top View (Ball Down)
A B C D E F G H 1 23456 RDY/BUSY VPP A18 NC I/O2 I/O10 I/O11 I/O3 CE OE VSS A17 I/O0 I/O8 I/O9 I/O1 WE RST NC A19 I/O5 I/O12 VCC I/O4 A10 A11 I/O7 I/O14 I/O13 I/O6 A13 A12 A14 A15 A16 NC I/015 VSS A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pu lse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase, Erase Suspend/Re sume and Program Suspend/ Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. 2. Pin Configurations Pin Name Function A0 - A19 Addresses CE Chip Enable OE Output Enable WE Write Enable RESET Reset RDY/BUSY READY/BUSY Output VPP Write Protection I/O0 - I/O15 Data Inputs/Outputs NC No Connect
3656A–FLASH–2/07 AT49SV163D(T) 3. Block Diagram 4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the “Command Definition Table” on page 12 (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE , whichever occurs last. The data is latched by the first rising edge of CE or WE . Standard microprocessor write timings are us ed. The address locations used in the command sequences are not affected by entering the command sequences. IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR OUTPUT MULTIPLEXER OUTPUT BUFFER INPUT BUFFER COMMAND REGISTER DATA REGISTER Y -GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH CE WE OE RESET RDY/BUSY VCC GND Y -DECODER X-DECODER INPUT BUFFER ADDRESS LATCH I/O0 - I/O15 A0 - A19 MAIN MEMORY VPP
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4.2 Read
The AT49SV163D(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
4.3 Reset
A RESET input pin is provided to ease so me system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs.
4.4 Erase
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
4.4.1 Chip Erase
The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the dev ice will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t EC. If the sector lockdown ha s been enabled, the chip erase w ill not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode.
4.4.2 Sector Erase
As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sec- tor address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE . The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is inter nally controlled; it will automatically time to completion. The maximum time to erase a sector is t SEC. When the sector programming lock- down feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating immediately.
4.5 Word Programming
Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Progr amming is completed after the specified t BP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or program operation was performed successfully.
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4.6 VPP Pin
The circuitry of the AT49SV163D(T) is designed so that the device cannot be programmed or erased if the V PP voltage is less that 0.4V. When V PP is at 1.65V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating.
4.7 Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49SV163D(T) contains a programmable configur ation register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the part will auto- matically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit command must be given after a suc- cessful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register command as shown in the “Command Definition Table” on page 12, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configura- tion register will affect the operation of the I/O7 status bit as described below.
4.7.1 Data Polling
The AT49SV163D(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a “00”, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase oper ation, an attempt to re ad the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page 11 for more details. If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the device is actively programming or erasing dat a. I/O7 will go high when the device has com- pleted a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 4-1 and 4-2 on page 9.
4.7.2 Toggle Bit
In addition to Data Polling the AT49SV163D(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the pro- gram cycle has comple ted, I/O6 will stop togg ling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on page 11 for more details. The toggle bit status bit should be used in conjunction with the erase/program and V PP status bit as shown in the algorithm in Figures 4-3 and 4-3 on page 10.
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4.7.3 Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to verify that an erase or a word program operation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or program operation is still in progress. Please see “Status Bit Table” on page 11 for more details.
4.7.4 VPP Status Bit
The AT49SV163D(T) provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase oper ation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”. Once the V PP status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the V PP status bit will output a “0”. Please see “Status Bit Table” on page 11 for more details.
4.8 Sector Lockdown
Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in t he rest of the device is updated. This feature does not have to be activated; any sector’s usage as a write-protected region is optional to the user. At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed.
4.8.1 Sector Lockdown Detection
A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see “Software Product Identification Entry/Exit” sections on page 23 ), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.
4.8.2 Sector Lockdown Override
The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.
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4.9 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Sus- pend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same.
4.10 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 20 µs to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other word that is not contained in the sector in which the programming operation was sus- pended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same.
4.11 Product Identification
The product identification mode identifies the device and manufacturer as Atmel ®. It is accessed using a software operation. For details, see “Operating Modes” on page 16 or “Software Product Identification Entry/Exit” sections on page 23. 4.12 128-bit Protection Register The AT49SV163D(T) contains a 128-bit register that can be used for security purposes in sys- tem design. The protection register is divide d into two 64-bit blo cks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the “Command Definition Table” . Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protec- tion Register Addressing Table” on page 13 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the prot ection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation.
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4.13 RDY/BUSY
An open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see “Status Bit Table” on page 11 for more details.
4.14 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed dev ice to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary bene- fits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the sys- tem can read CFI data at the addresses given in “Common Flash Interface Definition Table” on page 24. To exit the CFI Query mode, the product ID exit command must be given.
4.15 Hardware Data Protection
The Hardware Data Protection feature pr otects against inadvertent programs to the AT49SV163D(T) in the following ways: (a) V CC sense: if VCC is below 1.65V (typical), the pro- gram function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (t ypical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: VPP is less than VILPP .
4.16 Input Levels
While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
3656A–FLASH–2/07 AT49SV163D(T) Notes: 1. I/O5 switches to a “1” when a program or an erase o peration has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a “1” when the V PP level is not high enough to successfully perform program and erase operations. 5. Status Bit Table Status Bit I/O7 I/O7 I/O6 I/O5 (1) I/O3(2) I/O2 RDY/BUSY Configuration Register 00 01 00/01 00/01 00/01 00/01 00/01 Programming I/O7
0 TOGGLE 0 0 1 0
Erasing 0 0 TOGGLE 0 0 TOGGLE 0 Erase Suspended & Read Erasing Sector 11100 T O G G L E 1 Erase Suspended & Read Non-erasing Sector DATA DATA DATA DATA DATA DATA 1 Erase Suspended & Program Non-erasing Sector I/O7 0 TOGGLE 0 0 TOGGLE 0 Erase Suspended & Program Suspended and Reading from Non- suspended Sectors DATA DATA DATA DATA DATA DATA 1 Program Suspended & Read Programming Sector I / O 7 1100 T O G G L E 1 Program Suspended & Read Non-programming Sector DATA DATA DATA DATA DATA DATA 1
3656A–FLASH–2/07 AT49SV163D(T) Notes: 1. The DATA FORMAT shown for each bus cycle is as follow s; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don’t care. 2. Since A11 is a Don’t Care, AAA can be replaced with 2AA. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 15 for details). 4. This fast programming option enables the user to program two words in parallel only when V PP = 9.5V. The Addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only. 5. Once a sector is in the lockdown mode, data in the prot ected sector cannot be changed unless the chip is reset or power cycled. 6. Either one of the Product ID Exit commands can be used. 7. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used. 8. Any addresses within the user programmable protection register region. Address locations are shown on “Protection Regis- ter Addressing Table” on page 13. 9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. 10. The default state (after power-up) of the configuration register is “00”. 11. When accessing the data in the CFI table, the address format is A15 - A0 (Hex). 6. Command Definition Table Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 555 AA AAA (2) 55 555 80 555 AA AAA 55 555 10 Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA (3) 30 Word Program 4 555 AA AAA 55 555 A0 Addr D IN Dual Word Program(4) 5 555 AA AAA 55 555 E0 Addr0 D IN0 Addr1 D IN1 Enter Single Pulse Program Mode 6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0 Single Pulse Word Program 1A d d r D IN Sector Lockdown 6 555 AA AAA (2) 55 555 80 555 AA AAA 55 SA (3)(5) 60 Erase/Program Suspend 1 XXX B0 Erase/Program Resume 1 XXX 30 Product ID Entry 3 555 AA AAA 55 555 90 Product ID Exit(6) 3 555 AA AAA 55 555 F0 (7) Product ID Exit(6) 1 XXX F0 (7) Program Protection Register 4 555 AA AAA 55 555 C0 Addr (8) DIN Lock Protection Register - Block B 4 555 AA AAA 55 555 C0 080 X0 Status of Block B Protection 4 555 AA AAA 55 555 90 80 D OUT (9) Set Configuration Register 4 555 AA AAA 55 555 D0 XXX 00/01 (10) CFI Query(11) 1 X55 98
3656A–FLASH–2/07 AT49SV163D(T) Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0. 7. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on VPP 8. Protection Register Addressing Table A d d r e s s U s e B l o c k A 7A 6A 5A 4A 3A 2A 1A 0 8 1 F a c t o r y A10000001 8 2 F a c t o r y A10000010 8 3 F a c t o r y A10000011 8 4 F a c t o r y A10000100 8 5 U s e r B10000101 8 6 U s e r B10000110 8 7 U s e r B10000111 8 8 U s e r B10001000
3656A–FLASH–2/07 AT49SV163D(T) 9. AT49SV163D – Sector Address Table Sector Size (Bytes/Words) Address Range (A19 - A0) SA0 8K/4K 00000 - 00FFF SA1 8K/4K 01000 - 01FFF SA2 8K/4K 02000 - 02FFF SA3 8K/4K 03000 - 03FFF SA4 8K/4K 04000 - 04FFF SA5 8K/4K 05000 - 05FFF SA6 8K/4K 06000 - 06FFF SA7 8K/4K 07000 - 07FFF SA8 64K/32K 08000 - 0FFFF SA9 64K/32K 10000 - 17FFF SA10 64K/32K 18000 - 1FFFF SA11 64K/32K 20000 - 27FFF SA12 64K/32K 28000 - 2FFFF SA13 64K/32K 30000 - 37FFF SA14 64K/32K 38000 - 3FFFF SA15 64K/32K 40000 - 47FFF SA16 64K/32K 48000 - 4FFFF SA17 64K/32K 50000 - 57FFF SA18 64K/32K 58000 - 5FFFF SA19 64K/32K 60000 - 67FFF SA20 64K/32K 68000 - 6FFFF SA21 64K/32K 70000 - 77FFF SA22 64K/32K 78000 - 7FFFF SA23 64K/32K 80000 - 87FFF SA24 64K/32K 88000 - 8FFFF SA25 64K/32K 90000 - 97FFF SA26 64K/32K 98000 - 9FFFF SA27 64K/32K A0000 - A7FFF SA28 64K/32K A8000 - AFFFF SA29 64K/32K B0000 - B7FFF SA30 64K/32K B8000 - BFFFF SA31 64K/32K C0000 - C7FFF SA32 64K/32K C8000 - CFFFF SA33 64K/32K D0000 - D7FFF SA34 64K/32K D8000 - DFFFF SA35 64K/32K E0000 - E7FFF SA36 64K/32K E8000 - EFFFF SA37 64K/32K F0000 - F7FFF SA38 64K/32K F8000 - FFFFF
3656A–FLASH–2/07 AT49SV163D(T) 10. AT49SV163DT – Se ctor Address Table Sector Size (Bytes/Words) Address Range (A19 - A0) SA0 64K/32K 00000 - 07FFF SA1 64K/32K 08000 - 0FFFF SA2 64K/32K 10000 - 17FFF SA3 64K/32K 18000 - 1FFFF SA4 64K/32K 20000 - 27FFF SA5 64K/32K 28000 - 2FFFF SA6 64K/32K 30000 - 37FFF SA7 64K/32K 38000 - 3FFFF SA8 64K/32K 40000 - 47FFF SA9 64K/32K 48000 - 4FFFF SA10 64K/32K 50000 - 57FFF SA11 64K/32K 58000 - 5FFFF SA12 64K/32K 60000 - 67FFF SA13 64K/32K 68000 - 6FFFF SA14 64K/32K 70000 - 77FFF SA15 64K/32K 78000 - 7FFFF SA16 64K/32K 80000 - 87FFF SA17 64K/32K 88000 - 8FFFF SA18 64K/32K 90000 - 97FFF SA19 64K/32K 98000 - 9FFFF SA20 64K/32K A0000 - A7FFF SA21 64K/32K A8000 - AFFFF SA22 64K/32K B0000 - B7FFF SA23 64K/32K B8000 - BFFFF SA24 64K/32K C0000 - C7FFF SA25 64K/32K C8000 - CFFFF SA26 64K/32K D0000 - D7FFF SA27 64K/32K D8000 - DFFFF SA28 64K/32K E0000 - E7FFF SA29 64K/32K E8000 - EFFFF SA30 64K/32K F0000 - F7FFF SA31 8K/4K F8000 - F8FFF SA32 8K/4K F9000 - F9FFF SA33 8K/4K FA000 - FAFFF SA34 8K/4K FB000 - FBFFF SA35 8K/4K FC000 - FCFFF SA36 8K/4K FD000 - FDFFF SA37 8K/4K FE000 - FEFFF SA38 8K/4K FF000 - FFFFF
3656A–FLASH–2/07 AT49SV163D(T) 2. X can be V IL or VIH. 3. Refer to “Program Cycle Waveforms” on page 21. 4. V IHPP (min) = 1.65V 5. V ILPP (max) = 0.4V. 6. See details under “Software Product Identification Entry/Exit” on page 23. 7. Manufacturer Code: 001FH, Device Code: 02C0H - AT49SV163D; 02C2H (x16) - AT49SV163DT. 11. DC and AC Operating Range AT49SV163D(T)-80 Operating Temperature (Case) Ind. -40°C - 85°C VCC Power Supply 1.65V to 1.95V 12. Operating Modes Mode CE OE WE RESET VPP (1) Ai I/O Read V IL VIL VIH VIH X(2) Ai D OUT Program/Erase(3) VIL VIH VIL VIH VIHPP (4) Ai D IN Standby/Program Inhibit V IH X(2) XV IH X X High-Z Program Inhibit XX V IH VIH X XV IL XV IH X XXX V IH VILPP (5) Output Disable X V IH XV IH X High-Z R e s e t XXX V IL X X High-Z Product Identification Software(6) VIH A0 = VIL, A1 - A19 = VIL Manufacturer Code(7) A0 = VIH, A1 - A19 = VIL Device Code(7)
3656A–FLASH–2/07 AT49SV163D(T) Note: 1. In the erase mode, I CC is 15 mA. 13. DC Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current V IN = 0V to VCC 2µ A ILO Output Leakage Current V I/O = 0V to VCC 2µ A ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC 15 25 µA ICC (1) VCC Active Read Current f = 5 MHz; I OUT = 0 mA 10 15 mA ICC1 VCC Programming Current 15 mA IPP1 VPP Input Load Current 10 µA VIL Input Low Voltage 0.4 V VIH Input High Voltage V CC - 0.2 V VOL1 Output Low Voltage I OL = 2.1 mA 0.25 V VOL2 Output Low Voltage I OL = 1.0 mA 0.1 V VOH1 Output High Voltage I OH = -400 µA 1.4 V VOH2 Output High Voltage I OH = -100 µA V CC - 0.1 V
3656A–FLASH–2/07 AT49SV163D(T) 14. Input Test Waveforms and Measurement Level tR, tF < 5 ns 15. Output Test Load Note: 1. This parameter is characterized and is not 100% tested. 0.9V 16. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V
3656A–FLASH–2/07 AT49SV163D(T) 18. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 17. AC Read Characteristics Symbol Parameter AT49SV163D(T)-80 UnitsMin Max tRC Read Cycle Time 80 ns tACC Address to Output Delay 80 ns tCE (1) CE to Output Delay 80 ns tOE (2) OE to Output Delay 0 35 ns tDF (3)(4) CE or OE to Output Float 0 25 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0n s tRO RESET to Output Delay 100 ns OUTPUT VALID OUTPUT HIGH Z RESET OE tOE tCE ADDRESS VALID tDF tOH tACC tRO CE ADDRESS tRC
3656A–FLASH–2/07 AT49SV163D(T) 20. AC Word Load Waveforms
20.1 WE Controlled
20.2 CE Controlled
- AC Word Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time 0 ns tAH Address Hold Time 25 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)3 5 n s tWPH Write Pulse Width High 15 ns tDS Data Setup Time 25 ns tDH, tOEH Data, OE Hold Time 0 ns
3656A–FLASH–2/07 AT49SV163D(T) 22. Program Cycle Waveforms 23. Sector or Chip Erase Cycle Waveforms Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector eras e, the address depends on what sector is to be erased. (See note 3 under “Command Definition Table” on page 12.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 21. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Word Programming Time 10 120 µs tBPD Word Programming Time in Dual Programming Mode 5 60 µs tAS Address Setup Time 0 ns tAH Address Hold Time 25 ns tDS Data Setup Time 25 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 35 ns tWPH Write Pulse Width High 15 ns tWC Write Cycle Time 70 ns tRP Reset Pulse Width 500 ns tEC Chip Erase Cycle Time 16 seconds tSEC1 Sector Erase Cycle Time (4K Word Sectors) 0.1 2.0 seconds tSEC2 Sector Erase Cycle Time (32K Word Sectors) 0.5 6.0 seconds tES Erase Suspend Time 15 µs tPS Program Suspend Time 10 µs OE PROGRAM CYCLE INPUT DATA ADDRESS A055 555 555 AA AAA tBPtWPHtWP CE WE A0 - A19 DATA tAS tAH tDH tDS 555 AA tWC OE (1) AA80 Note 355 55 555 555 Note 2 AA WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 AAA AAA tWPHtWP CE WE A0-A19 DATA tAS tAH tEC tDH tDS 555 tWC
3656A–FLASH–2/07 AT49SV163D(T) Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in “AC Read Characteristics” on page 19. 25. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in “AC Read Characteristics” on page 19. 27. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 24. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns A0-A19 WE CE OE I/O7 tDH tOEH tOE HIGH Z An An An An An tWR 26. Toggle Bit Characteristics (1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 50 ns tWR Write Recovery Time 0 ns
3656A–FLASH–2/07 AT49SV163D(T) 28. Software Product Identification Entry(1) 29. Software Product Identification Exit(1)(6) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t Care). 2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. Additional Device Code is read from address 0003H. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH Device Code: 02C0H – AT49SV163D; 02C2H – AT49SV163DT. Additional Device Code: 0001H – AT49SV163D(T) 6. Either one of the Product ID Exit commands can be used. LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 90 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE(4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) 30. Sector Lockdown Enable Algorithm(1) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t Care). 2. Sector Lockdown feature enabled. LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 60 TO SECTOR ADDRESS PAUSE 200 µs(2)
3656A–FLASH–2/07 AT49SV163D(T) 31. Common Flash Interface Definition Table Address Data Comments 10h 0051h “Q” 11h 0052h “R” 12h 0059h “Y” 13h 0002h 14h 0000h 15h 0041h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h 1Bh 0017h VCC min write/erase 1Ch 0019h VCC max write/erase 1Dh 0090h VPP min voltage 1Eh 00A0h VPP max voltage 1Fh 0004h Typ word write – 10 µs 20h 0002h Typ dual word program time – 5 µs 21h 0009h Typ sector erase, 500 ms 22h 000Eh Typ chip erase, 16,000 ms 23h 0004h Max word write/typ time 24h 0004h Max dual word program time/typ time 25h 0004h Max sector erase/typ sector erase 26h 0004h Max chip erase/ typ chip erase 27h 0015h Device size 28h 0001h x16 device 29h 0000h x16 device 2Ah 0002h Max number of bytes in multiple byte write = 4 2Bh 0000h Max number of bytes in multiple byte write = 4 2Ch 0002h 2 regions, x = 2 2Dh 0007h 8K bytes, Y = 7 2Eh 0000h 8K bytes, Y = 7 2Fh 0020h 8K bytes, Z = 32 30h 0000h 8K bytes, Z = 32 31h 001Eh 64K bytes, Y = 30 32h 0000h 64K bytes, Y = 30 33h 0000h 64K bytes, Z = 256 34h 0001h 64K bytes, Z = 256
3656A–FLASH–2/07 AT49SV163D(T) VENDOR SPECIFIC EXTENDED QUERY 41h 0050h “P” 42h 0052h “R” 43h 0049h “I” 44h 0031h Major version number, ASCII 45h 0030h Minor version number, ASCII 46h 0087h Bit 0 – chip erase supported, 0 – no, 1 – yes Bit 1 – erase suspend supported, 0 – no, 1 – yes Bit 2 – program suspend supported, 0 – no, 1 – yes Bit 3 – simultaneous operations supported, 0 – no, 1 – yes Bit 4 – burst mode read supported, 0 – no, 1 – yes Bit 5 – page mode read supported, 0 – no, 1 – yes Bit 6 – queued erase supported, 0 – no, 1 – yes Bit 7 – protection bits supported, 0 – no, 1 – yes 47h 0000h (top) or 0001h (bottom) Bit 0 – top (“0”) or bottom (“1”) boot block device undefined bits are “0” 48h 0000h Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes Bit 2 – continuos burst, 0 - no, 1 - yes Undefined bits are “0” 49h 0000h Bit 0 – 4 word page, 0 – no, 1 – yes Bit 1 – 8 word page, 0 – no, 1 – yes Undefined bits are “0” 4Ah 0080h Location of protection register lock byte, the section’s first byte 4Bh 0003h # of bytes in the factory prog section of prot register – 2*n 4Ch 0003h # of bytes in the user prog section of prot register – 2*n 31. Common Flash Interface Definition Table (Continued) Address Data Comments
3656A–FLASH–2/07 AT49SV163D(T) 32. Ordering Information
32.1 Green Package (Pb/Halide-free)
(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 80 25 0.025 AT49SV163D-80CU AT49SV163D-80TU 48C17 48T Industrial (-40° to 85° C) 80 25 0.025 AT49SV163DT -80CU AT49SV163DT -80TU 48C17 48T Industrial (-40° to 85° C) Package Type 48C17 48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 48T 48-lead, Plastic Thin Small Outline Package (TSOP)
3656A–FLASH–2/07 AT49SV163D(T) 33. Packaging Information 33.1 48C17 – CBGA
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 48C17, 48-ball (6 x 8 Array), 0.80 mm Pitch, 7.0 x 10.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA) B48C17 10/26/05 Top View Bottom View Side View A B C D E F G H
1.50 REF
2.20 REF
E D A1 Ball ID 6 54321 A e e A1 Ball Corner Øb COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE E 6.9 7.0 7.1 E1 4.0 TYP D 9.9 10.0 10.1 D1 5.6 TYP A – – 1.0 A1 0.20 – – e 0.80 BSC Øb 0.35 TYP
3656A–FLASH–2/07 AT49SV163D(T) 33.2 48T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) B48T 10/18/01 PIN 1 0º ~ 8º D1 D Pin 1 Identifier be E AA2 c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 11.90 12.00 12.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC
3656A–FLASH–2/07 AT49SV163D(T) 34. Revision History Revision No. History Revision A – February 2007 • Initial Web Release
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