AT49SN12804

AT49SN12804 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 41

Technical content

Features

• 1.65V - 1.95V Read/Write  High Performance – Random Access Time – 70 ns – Page Mode Read Time – 20 ns – Synchronous Burst Frequency – 66 MHz – Configurable Burst Operation  Sector Erase Architecture – Sixteen 4K Word Sectors with Individual Write Lockout – Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout  Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms  Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one Planes not Being Programmed/Erased  Suspend/Resume Feature for Erase and Program – Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Word by Suspending Programming of Any Other Word  Low-power Operation –3 0 m A A c t i v e – 10 µA Standby  VPP Pin for Write Protection and Accelerated Program/Erase Operations  RESET Input for Device Initialization  CBGA and TSOP Packages  Seventeen 128-bit Protection Registers (2,176 Bits)  Common Flash Interface (CFI)

Description

The AT49SN/SV12804 is a 1.8-volt 128-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The AT49SN/SV12804 is organized as 8,388,608 x 16 bits. The device can be read or reprogrammed off a single 1.8V power supply, making it ideally suited for In-System programming. The device can be configured to operate in the asynchronous/page read (default mode) or burst read mode (not available for the AT49SV12804). The burst read mode is used to achieve a faster data rate than is possible in the asynchronous/page read mode. If the AVD and the CLK signals are both tied to GND and the burst configuration register is configured to perform asynchronous reads, the device will behave like a standard asynchronous Flash memory. In the page mode, the AVD signal can be tied to GND or can be pulsed low to latch the page address. In both cases the CLK can be tied to GND. The AT49SN/SV12804 is divided into thirty-two memory planes. A read operation can occur in any of the thirty-one planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the sys- tem to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Pro- gram Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remain- ing sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The VPP pin provides data protection and faster programming and erase times. When the V PP input is below 0.4V, the program and erase functions are inhibited. When V PP is at 0.9V or above, normal program and erase operations can be performed. With VPP at 12.0V, the program (Dual-word Program command) and erase operations are accelerated. 128-megabit (8M x 16) Burst/Page Mode 1.8-volt Flash Memory AT49SN12804 AT49SV12804 Preliminary Rev. 3314A–FLASH–4/04

2 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 AT49SN/SV12804: Pin Configurations Note: 1. These signals are not available for use with the AT49SV12804. The A T49SV12804 can only be used in the asynchro- nous/page mode. Pin Name Pin Function I/O0 - I/O15 Data Inputs/Outputs A0 - A22 Addresses CE Chip Enable OE Output Enable WE Write Enable AVD(1) Address Latch Enable CLK(1) Clock RESET Reset WP(1) Write Protect VPP Write Protection and Power Supply for Accelerated Program Operations WAIT(1) WAIT VCCQ Output Power Supply AT49SN12804: CBGA – Top View A B C D E F G 1 2345678 A11 A12 A13 A15 VCCQ VSS I/O7 A10 A14 I/O15 I/O14 VSS VSS A20 A21 WAIT I/O6 I/013 I/O5 VCC CLK AVD A16 I/O4 I/O11 VCC VPP RESET WE I/O12 I/O2 I/O10 I/O3 A18 A17 A19 WP I/O1 I/O9 VCCQ A22 CE I/O0 I/O8 OE VSS AT49SV12804: TSOP – Top View Type 1 A21 NC A20 A19 A18 A17 A16 A15 VCC A14 A13 A12 A11 CE VPP RST A10 VSS NC WE OE NC I/O15 I/O7 I/O14 I/O6 VSS I/O13 I/O5 I/O12 I/O4 VCCQ VSS I/O11 I/O3 I/O10 I/O2 VCC I/O9 I/O1 I/O8 I/O0 NC NC A22 NC

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Device Operation COMMAND SEQUENCES: When the device is first power ed on, it will be in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. BURST CONFIGURATION COMMAND: The Program Burst Configuration Register command is used to program the burst configuration register. The burst configuration register determines several parameters that control the read operation of the device. Bit B15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. Since the page read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to enable the page read feature. Bit B14 determines whether a four-word page or an eight-word page will be used. The rest of the bits in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock latency versus input clock frequency table is shown on page 20. The “Burst Read Waveform” as shown on page 31 illustrates a clock latency of four; the data is output from the device four clock cycles after the first valid clock edge following the high-to-low AVD edge. The B10 bit of the configuration register determines the polarit y of the WAIT signal. The B9 bit of the burst configuration register determines the number of clocks that data will be held valid (see Figure 4). The Hold Data for 2 Clock Cycles Read Waveform is shown on page 31. The clock latency is not affected by the value of the B9 bit. The B8 bit of the burst configuration register deter- mines when the WAIT signal will be asserted. When synchronous burst reads are enabled, a linear burst sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four-, eight - or sixteen-word length will be used in the fixed-length mode. When a four-, eight- or sixteen-word burst length is selected, Bit B3 can be used to select whether burst accesses wrap within the burst length boundary or whether they cross word length boundaries to perform linear accesses (see Table 5). All other bits in the burst configuration register should be programmed as shown on page 20. The default state (after power-up or reset) of the burst configuration register is also shown on page 20. ASYNCHRONOUS READ: There are two types of asynchronous reads – AVD pulsed and standard asynchronous reads. The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. The data at the address location defined by A0 - A22 and captured by the AVD signal will be read when CE and OE are low. The address location passes into the device when CE and AVD are low; the address is latched on the low-to-high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of the devic e. The access time is measured from stable address, falling edge of AVD or falling edge of CE , whichever occurs last. During the AVD pulsed read, the CLK signal may be static high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are shown on page 28. PAGE READ: The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input is ignored during a page read operation and should be tied to GND. The page size can be four words (default value) or eight words depending on what value bit B14 of the burst configuration register is programmed to. During a page read, the AVD signal can transi- tion low and then transition high, transition low and remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the

4 AT49SN/SV12804 [Preliminary]

word page and A22 - A2 for a four-word page) cannot change during a page read operation. read diagrams are shown on page 22. for the AVD pulsed asynchronous read operation; it can be any memory location in the device. data at the next burst address location is read for each following clock cycle. Figure 1. Word Boundary In the “Burst Read Waveform” as shown on page 31, the valid address is latched at point A. like at point G, will continue to result in burst reads.

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 FIXED-LENGTH BURST READS: During a fixed-length burst mode read, four, eight or six- teen words of data may be burst from the device, depending upon the configuration. The device supports a linear burst mode. The burst sequence is shown on page 21. When operat- ing in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory. If the starting is D0 - D12, there is no delay. If the starting address is D13 - D15, an output delay equal to the initial clock latency is incurred. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or OE signal is high. The “Four-word Burst Read Waveform” on page 32 illustrates a fixed-length burst cycle. The valid address is latched at point A. For the specified clock latency of four, data D0 is valid within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read. Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the read cycle. There is no output delay in the burst access wrap mode (B3 = 0). BURST SUSPEND: The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the Flash address and data bus for other purposes. Burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. Burst Suspend occurs when CE is asserted, the current address has been latched (either ris- ing edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted when it is at V IH or VIL. To resume the burst access, OE is reasserted and the CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT sig- nal reverts to a high-impedance state when OE is deasserted. See “Burst Suspend Waveform” on page 32. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read mode. ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase com- mand or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command.

6 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 CHIP ERASE : Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state. PLANE ERASE: As an alternative to a full Chip Erase, the device is organized into thirty-two planes that can be individually erased. The Plane Erase command is a two-bus cycle opera- tion. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors. SECTOR ERASE: The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. WORD PROGRAMMING: The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automati- cally generate the required internal programmi ng pulses. Please note that a “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. FLEXIBLE SECTOR PROTECTION: The AT49SN/SV12804 offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a two- bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector. HARDLOCK AND WRITE PROTECT (WP ): The Hardlock sector protection mode operates in conjunction with the Write Protection (WP ) pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden.  When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only.  When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command.

To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. Figure 2. Sector Locking State Diagram sector is defined by the state of WP and the two bits of the sector-lock status D[1:0]. Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP VCC 1 0 0 Yes No sector is locked.

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sector will show if the sector is unlocked, softlocked, or hardlocked. reading from the memory, issue a Read command. when a Read Status Register command is issued. read, or the status register will not indicate completion of a Program or Erase operation. the preferred operation (see Table 3). Table 2. Sector Protection Status

after the chosen clock latency during an erase operation. Figure 3. Read Status Register in the Burst Mode Note: 1. The WAIT signal is for a burst configuration setting of B10 and B8 = 0.

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Note: 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set. Table 3. Status Register Bit Definition an Erase Resume command is issued. before the operation is verified by the WSM. until a Program Resume command is issued. 1 = Prog/Erase attempted on a locked sector; Operation aborted. aborted and the device is returned to read status mode. SR0 = Plane Status (PLS) Indicates program or erase status of the addressed plane. Table 4. Status Register Device WSMS and Write Status Definition 0 0 The addressed plane is performing a program/erase operation. 0 1 A plane other than the one currently addressed is performing a program/erase operation. indicate whether other planes are suspended.

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase or plane erase operation. The erase suspend command does not work with the Chip Erase feature. Using the erase suspend command to suspend a sector erase operation, the system can program or read data from a different sector within the same plane. Since this device is organized into thirty-two planes, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to sus- pend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Pro- gram, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock are valid commands during an erase suspend. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation a nd then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 µs to suspend the programming operati on. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program sus- pend are the same, and the command sequence for the erase resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid com- mands during a Program Suspend. 128-BIT PROTECTION REGISTERS: The AT49SN/SV12804 contains seventeen (PR0 - PR16) 128-bit registers that can be used for security purposes in system design. Please see the Protection Register Addressing Table on page 19 for the address locations within each protection register. The first protection register (PR0) is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. The other 16 registers (PR1 - PR16) have 128 bits (16 words) each that are all user programmable. To pro- gram block B in PR0 or to program PR1 - PR16 register, a two-bus cycle command must be used as shown in the Command Definition table on page 18. To lock out block B in PRO or to lock out PR1 - PR16, a two-bus cycle command must also be used as shown in the Command Definition table. To lock out block B in PRO, the address used in the second bus cycle is 080h and data bit D1 must be zero during the second bus cycle. All other data bits during the sec- ond bus cycle are don’t cares. To lock out PR1 - PR16, the address used in the second bus cycle is 089h and sixteen bits of data are programmed. If any of these bits is programmed to a zero, the appropriate register is locked. After being locked, the protection register cannot be unlocked. To determine whether block B in PRO or PR1 - PR16 is locked out, the Product ID Entry command is given followed by a read operation from address 80H or address 89H, respectively. (This command is shown as status of protection in the Command Definition table). For block B in PRO, if data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. For PR1 - PR16, sixteen bits of data are read out. Each bit represents the protection status of a particular register. If the bit is a zero, the register is locked. If the bit is a one, the register can be reprogrammed. To read a protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether a register is protected or not or reading the protection reg- ister, the Read command must be given to return to the read mode.

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3314A–FLASH–4/04 CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to deter- mine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to any address. The CFI Query command can be written when the device is ready to read data or can also be wr itten when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in Table on page 31. To return to the read mode, the read command should be issued. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49SN/SV12804 in the following ways: (a) V CC sense: if V CC is below 1.2V (typical), the device is reset and the program and erase functions are inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typi- cal) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP. INPUT LEVELS: While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 2.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V. OUTPUT LEVELS: For the AT49SN/SV12804, output high levels are equal to V CCQ - 0.1V (not VCC). VCCQ must be regulated between 1.8V - 2.25V.

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Word Program Flowchart Full Status Check Flowchart Program Suspend Loop Start Write 40, Word Address Write Data, Word Address Read Status Register SR7 = Full Status Check (If Desired) Program Complete Suspend? No Yes (Setup) (Confirm) Read Status Register Program Successful SR3 = SR1 = SR4 =

1 VPP Range

Full Status Check Procedure Bus Operation Command Comments Write Program Setup Data = 40 Addr = Location to program Write Data Data = Data to program Addr = Location to program Read None Status register data: Toggle CE or OE to update status register Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to set to the Read state. Bus Operation Command Comments Idle None Check SR3: 1 = VPP Error Idle None Check SR4: 1 = Data Program Error Idle None Check SR1: 1 = Sector locked; operation aborted SR3 MUST be cleared before the Write State Machine allows further program attempts. If an error is detected, clear the status register before continuing operations – only the Clear Status Register command clears the status register error bits.

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3314A–FLASH–4/04 Program Suspend/Resume Flowchart Read Status Register SR7 = SR2 = Read Data Program Completed Done Reading Program Resumed Read Data No Yes Write FF (Read Array) Write D0 Any Address (Program Resume) Write FF (Read Array) Start Write B0 Any Address (Program Suspend) Write 70 Any Address (Read Status) the Same Plane within Suspend Plane Write 70H Any Address within the Same Plane (Read Status) Program Suspend/Re sume Procedure Bus Operation Command Comments Write Program Suspend Data = B0 Addr = Sector address to Suspend (SA) Write Read Status Data = 70 Addr = Any address within the Same Plane Read None Status register data: Toggle CE or OE to update status register Addr = Any address Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Idle None Check SR2 1 = Program suspended 0 = Program completed Write Read Array Data = FF Addr = Any address within the Suspended Plane Read None Read data from any sector in the memory other than the one being programmed Write Program Resume Data = D0 Addr = Any address If the Suspend Plane was placed in Read mode: Write Read Status Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Erase Suspend/Resume Flowchart Erase Completed Read Array Data Start Read Status Register SR7 = SR6 = Erase Resumed Done? Read Read or Program? Write 70, Any Address (Read Status) Write B0, Any Address (Erase Suspend) Write D0, Any Address(Erase Resume) Write FF (Read Array) No Yes Program Loop Write 70H Any Address within the Same Plane (Read Status) Erase Suspend/Resume Procedure Bus Operation Command Comments Write Erase Suspend Data = B0 Addr = Any address within the Same Plane Write Read Status Data = 70 Addr = Any address Read None Status register data: Toggle CE or OE to update status register Addr = Any address within the Same Plane Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Idle None Check SR6 1 = Erase suspended 0 = Erase completed Write Read or Program Data = FF or 40 Addr = Any address Read or Write None Read or program data from/to sector other than the one being erased Write Program Resume Data = D0 Addr = Any address If the Suspended Plane was placed in Read mode or a Program loop: Write Read Status Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane

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3314A–FLASH–4/04 Sector Erase Flowchart Full Erase Status Check Flowchart Start No Suspend Erase

0 Yes

Write 20, Address Write D0, Address Read Status Register SR7 = Full Erase Status Check (If Desired) Erase Complete (E r a s e ) (Erase Confirm) Sector SectorSector Sector 1,1 Read Status Register Erase Successful SR1 = Sector Sector Locked Error SR3 = VPP Range Error SR4, SR5= Command Sequence Error SR5 = Erase Error Sector Sector Erase Procedure Full Erase Status Check Procedure Bus Operation Command Comments Write Sector Erase Setup Data = 20 Addr = Sector to be erased (SA) Write Erase Confirm Data = D0 Addr = Sector to be erased (SA) Read None Status register data: Toggle CE or OE to update status register data Idle None Check SR7 1 = WSMS Ready 0 = WSMS Busy Repeat for subsequent sector erasures. Full status register check can be done after each sector erase, or after a sequence of sector erasures. Write FF after the last operation to enter read mode. Bus Operation Command Comments Idle None Check SR3: 1 = VPP Range Error Idle None Check SR4, SR5: Both 1 = Command Sequence Error Idle None Check SR5: 1 = Sector Erase Error Idle None Check SR1: 1 = Attempted erase of locked sector; erase aborted. SR1, SR3 must be cleared before the Write State Machine allows further erase attempts. Only the Clear Status Register command clears SR1, SR3, SR4, SR5. If an error is detected, clear the status register before attempting an erase retry or other error recovery.

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Protection Register Programming Flowchart Full Status Check Flowchart Start Write C0, PR Address Write PR Address & Data Read Status Register SR7 = Full Status Check (If Desired) Program Complete (Program Setup) (Confirm Data) 0, 1 1, 1 Read Status Register Data Program Successful = VPP Range Error Program Error Register Locked; Program Aborted SR1, SR4 SR1, SR4 SR3, SR4 1, 1 Protection Register Programming Procedure Full Status Check Procedure Bus Operation Command Comments Write Program PR Setup Data = C0 Addr = First Location to Program Write Protection Program Data = Data to Program Addr = Location to Program Read None Status register data: Toggle CE or OE to update status register data Idle None Check SR7 1 = WSMS Ready 0 = WSMS Busy Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to return to the Read mode. Bus Operation Command Comments Idle None Check SR1, SR3, SR4: 0,1,1 = VPP Range Error Idle None Check SR1, SR3, SR4: 0,0,1 = Programming Error Idle None Check SR1, SR3, SR4: 1, 0,1 = Sector locked; operation aborted SR3 must be cleared before the Write State Machine allows further program attempts. Only the Clear Status Register command clears SR1, SR3, SR4. If an error is detected, clear the status register before attempting a program retry or other error recovery.

18 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS FOR MA T shown for each bus cycle is as follows: A7 - A0 (Hex). Address A22 through A8 are don’t care. 2. PA is the plane address (A22 - A18). Any address within a plane can be used. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 22 - 25 for deta ils). 4. The status register bits are output on I/O7 - I/O0. 5. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. 6. See “Burst Configuration Register” on page 20. Bits B15 - B0 of the burst configuration register determine A15 - A0. Addresse s A16 - A22 can select any plane. 7. The plane address has to be the same as the plane address in the second bus cycle. 8. Any address within the user programmable protection register region. 9. This fast programming option enables the user to program two words in parallel only when V PP = 12V. The addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only. 10. Address locations are shown on next page. 11. D IN represents 16 bits of data. If any bit is programmed to a “0”, the appropriate protection register is locked. 12. D OUT represents 16 bits of data. Each bit corresponds to the protec tion status of a given register. The most significant bit read o ut corre- sponds to PR16, and the last significant bit corresponds to PR0. If the data bit is a “0”, the register is locked. If the data bits is a “1”, the register can be programmed. 13. The manufacturer code is read from address 0000H , and the device code is read from address 0001H. 14. The first bus cycle address should be the same as the word address to be programmed. Command Definition in Hex(1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Addr Data Addr Data Addr Data Read 1 PA (2) FF Chip Erase 2 XX 21 Addr D0 Plane Erase 2 XX 22 Addr D0 Sector Erase 2 SA 20 SA (3) D0 Word Program 2 Addr (14) 40/10 Addr (14) DIN Dual Word Program(9) 3 Addr0 E0 Addr0 D IN0 Addr1 D IN1 Erase/Program Suspend 1 XX B0 Erase/Program Resume 1 PA D0 Product ID Entry (13) 1P A 9 0 Sector Softlock 2 SA 60 SA (3) 01 Sector Hardlock 2 SA 60 SA (3) 2F Sector Unlock 2 SA 60 SA (3) D0 Read Status Register 2 PA 70 XX D OUT (4) Clear Status Register 1 XX 50 Program PR0 (Block B) or PR1-PR16 2 XX (8) C0 Addr (10) DIN Lock Protection PR0 – Block B 2 80 C0 80 FFFD Lock Protection PR1-PR16 2 XX C0 89 D IN (11) Status of Protection PR0 (Block B) 2 PA 90 80 D OUT (5) Status of Protection PR1-PR16 2 PA 90 89 D OUT (12) Program Burst Configuration Register 2 Addr (6) 60 Addr (6) 03 Read Burst Configuration Register 2 PA 90 PAX005 (7) DOUT CFI Query 1 XX 98

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Note: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A22 - A9 = 0. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages Except V PP (including NC Pins) VPP Input Voltage All Output Voltages Protection Register Addressing Table A d d r e s s U s e B l o c k A 8A 7A 6A 5A 4A 3A 2A 1 A 0 8 1 F a c t o r y A 01000000 1 8 2 F a c t o r y A 01000001 0 8 3 F a c t o r y A 01000001 1 PRO 8 4 F a c t o r y A 01000010 0 8 5 U s e r B 01000010 1 8 6 U s e r B 01000011 0 8 7 U s e r B 01000011 1 8 8 U s e r B 01000100 0

8 A U s e r 01000101 0

20 AT49SN/SV12804 [Preliminary]

1. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1 (WAIT asserted one

clock cycle before data is valid) is not supported.

1. Data is not ready when WAIT is asserted.

Figure 4. Output Configuration

1 CLK

2 CLK

Table 5. Sequence and Burst Length

22 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 Memory Organization – AT49SN/SV12804 Plane Plane Size (Bits) Sector Size Words x16 Address Range (A22 - A0) SA0 4K 00000 - 00FFF SA1 4K 01000 - 01FFF SA2 4K 02000 - 02FFF SA3 4K 03000 - 03FFF SA4 4K 04000 - 04FFF SA5 4K 05000 - 05FFF SA6 4K 06000 - 06FFF SA7 4K 07000 - 07FFF SA8 32K 08000 - 0FFFF SA9 32K 10000 - 17FFF SA13 32K 30000 - 37FFF SA14 32K 38000 -3FFFF SA15 32K 40000 - 47FFF

2 SA22 32K 78000 - 7FFFF

3 SA30 32K B8000 - BFFFF

4 SA38 32K F8000 - FFFFF

5 SA46 32K 138000 - 13FFFF

6 SA54 32K 178000 - 17FFFF

7 SA62 32K 1B8000 - 1BFFFF

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 SA63 32K 1C0000 - 1C7FFF

8 SA70 32K 1F8000 - 1FFFFF

9 SA78 32K 238000 - 23FFFF

10 SA86 32K 278000 - 27FFFF

11 SA94 32K 2B8000 - 2BFFFF

12 SA102 32K 2F8000 - 2FFFFF

13 SA110 32K 338000 - 33FFFF

14 SA118 32K 378000 - 37FFFF

15 SA126 32K 3B8000 - 3BFFFF

16 SA134 32K 3F8000 - 3FFFFF

Memory Organization – AT49SN/SV12804 (Continued) Plane Plane Size (Bits) Sector Size Words x16 Address Range (A22 - A0)

24 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 SA135 32K 400000 - 407FFF

17 SA142 32K 438000 - 43FFFF

18 SA150 32K 478000 - 47FFFF

19 SA158 32K 4B8000 - 4BFFFF

20 SA166 32K 4F8000 - 4FFFFF

21 SA174 32K 538000 - 53FFFF

22 SA182 32K 578000 - 57FFFF

23 SA190 32K 5B8000 - 5BFFFF

24 SA198 32K 5F8000 - 5FFFFF

25 SA206 32K 638000 - 63FFFF

Memory Organization – AT49SN/SV12804 (Continued) Plane Plane Size (Bits) Sector Size Words x16 Address Range (A22 - A0)

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 SA207 32K 640000 - 647FFF

26 SA214 32K 678000 - 67FFFF

27 SA222 32K 6B8000 - 6BFFFF

28 SA230 32K 6F8000 - 6FFFFF

29 SA238 32K 738000 - 73FFFF

30 SA246 32K 778000 - 77FFFF

31 SA254 32K 7B8000 - 7BFFFF

Memory Organization – AT49SN/SV12804 (Continued) Plane Plane Size (Bits) Sector Size Words x16 Address Range (A22 - A0)

26 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 Notes: 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. Manufacturer Code: 001FH; Device Code: 00BBH 4. The VPP pin can be tied to V CC. For faster program/erase operations, VPP can be set to 12.0V ± 0.5V. 5. V IHPP (min) = 0.9V. 6. V ILPP (max) = 0.4V. DC and AC Operating Range AT49SN/SV12804-70 Operating Temperature (Case) Industrial -40°C - 85°C VCC Power Supply 1.65V - 1.95V Operating Modes Mode CE OE WE RESET VPP (4) Ai I/O Read V IL VIL VIH VIH XA i D OUT Burst Read V IL VIL VIH VIH XA i D OUT Program/Erase(3) VIL VIH VIL VIH VIHPP (5) Ai D IN Standby/Program Inhibit VIH X(1) XV IH X X High Z Program Inhibit XX V IH VIH X XV IL XV IH X XXX X V ILPP (6) Output Disable X V IH XV IH X High Z Reset X X X V IL X X High Z Product Identification Software V IH A0 = VIL, A1 - A22 = VIL Manufacturer Code(3) A0 = VIH, A1 - A22 = VIL Device Code(3)

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Note: 1. In the erase mode, I CC is 30 mA. Input Test Waveforms and Measurement Level tR, tF < 5 ns Output Test Load Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 1µ A ILO Output Leakage Current V I/O = 0V to VCC 1µ A ISB1 VCC Standby Current CMOS CE = VCCQ - 0.3V to VCC 20 µA ICC (1) VCC Active Current f = 66 MHz; I OUT = 0 mA 30 mA ICCRE VCC Read While Erase Current f = 66 MHz; I OUT = 0 mA 50 mA ICCRW VCC Read While Write Current f = 66 MHz; I OUT = 0 mA 50 mA VIL Input Low Voltage 0.4 V VIH Input High Voltage V CCQ - 0.2 V VOL Output Low Voltage IOL = 100 µA IOL = 2.1 mA 0.1 0.25 V VOH Output High Voltage IOH = -100 µA V CCQ - 0.1 V IOH = -400 µA 1.4 AC DRIVING LEVELS 1.4V 0.4V 0.9V AC MEASUREMENT LEVEL V 1.8K OUTPUT PIN 30 pF1.3K CCQ Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V

28 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 AVD Pulsed Asynchronous Read Cycle Waveform(1)(2) Notes: 1. After the high-to-low transition on AVD , AVD may remain low as long as the address is stable. 2. CLK may be static high or static low. Asynchronous Read Cycle Waveform(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. AVD and CLK should be tied low. AC Asynchronous Read Timing Characteristics Symbol Parameter Min Max Units tACC1 Access, AVD To Data Valid 70 ns tACC2 Access, Address to Data Valid 70 ns tCE Access, CE to Data Valid 70 ns tOE OE to Data Valid 20 ns tAHAV Address Hold from AVD 9n s tAVLP AVD Low Pulse Width 10 ns tAVHP AVD High Pulse Width 10 ns tAAV Address Valid to AVD 7n s tDF CE, OE High to Data Float 25 ns tOH Output Hold from OE, CE or Address, Whichever Occurred First ns tRO RESET to Output Delay 150 ns tCE tACC2 tDF tDF tAHAV DATA VALID CE I/O0-I/O15 A2 -A22 tAAV tAVLP tACC1 AVD OE tOE tAVHP RESET tRO (1) tACC2 tAHAV A0 -A1 tAAV OUTPUT VALID I/O0 - I/O15 HIGH Z RESET OE tOE tCE ADDRESS VALID tDF tOHtACC2 tRO CE A0 - A22 tRC

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Page Read Cycle Waveform 1(1) Note: 1. After the high-to-low transition on AVD , AVD may remain low as long as the page address is stable. Page Read Cycle Waveform 2(1) Note: 1. AVD may remain low as long as the page address is stable. AC Asynchronous Read Timing Characteristics Symbol Parameter Min Max Units tACC1 Access, AVD To Data Valid 70 ns tACC2 Access, Address to Data Valid 70 ns tCE Access, CE to Data Valid 70 ns tOE OE to Data Valid 20 ns tAHAV Address Hold from AVD 9n s tAVLP AVD Low Pulse Width 10 ns tAVHP AVD High Pulse Width 10 ns tAAV Address Valid to AVD 7n s tDF CE, OE High to Data Float 25 ns tRO RESET to Output Delay 150 ns tPA A Page Address Access Time 20 ns tCE tACC2 tDF tDF tAHAV DATA VALID CE I/O0-I/O15 A2 -A22 tAAV tAVLP tACC1 AVD OE tOE tAVHP RESET tRO (1) tACC2 tAHAV A0 -A1 tAAV tPAA tCE tACC2 tDF tDF DATA VALID CE I/O0-I/O15 A2 -A22 AVD OE tOE RESET tRO (1) tACC2 A0 -A1 tPAA VIL

30 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 Burst Read Cycle Waveform Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (s olid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. After the high-to-low transition on AVD , AVD may remain low. AC Burst Read Timing Characteristics Symbol Parameter Min Max Units tCLK CLK Period 15 ns tCKH CLK High Time 4 ns tCKL CLK Low Time 4 ns tCKRT CLK Rise Time 3.5 ns tCKFT CLK Fall Time 3.5 ns tACK Address Valid to Clock 7 ns tAVCK AVD Low to Clock 7 ns tCECK CE Low to Clock 7 ns tCKAV Clock to AVD High 3 ns tQHCK Output Hold from Clock 3 ns tAHCK Address Hold from Clock 8 ns tCKRY Clock to WAIT Delay 13 ns tCESAV CE Setup to AVD 10 ns tAAV Address Valid to AVD 10 ns tAHAV Address Hold From AVD 9n s tCKQV CLK to Data Delay 13 ns tCEQZ CE High to Output High-Z 10 ns D15D13 D16 CE I/O0-I/O15 A0-A21 AVD CLK OE ... WAIT tCESAV tCE tAHAV tAAV D17... D14 ... tCECK tAHCK tAVCK tACK ... tCKAV tCKRY tCKRY tCLK tCKH tCKL tCKQV tCEQZ tQHCK (1) (2)

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Burst Read Waveform (Clock Latency of 3) Note: 1. Dashed line reflects a B10 and B8 setting of 0 in the configuration register. Solid line reflects a B10 setting of 0 and B8 setting of 1 in the configuration register. Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 3) Note: 1. Dashed line reflects a burst configuration register setting of B10 and B8 = 0, B9 = 1. Solid line reflects a burst configuration register setting of B10 = 0, B9 and B8 = 1 VALID D13 D14 D15 CE A0-A21 I/O0-I/O15 AVD CLK OE WAIT(1) A C D E F GB HIGH ZHIGH Z D16 D18D17 A0-A21 I/O0-I/O15 AVD CLK WAIT(1) OE CE D13 D14 D15 D16

32 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 Four-word Burst Read Waveform (Clock Latency of 4) Note: 1. The WAIT signal shown is for a burst configuration register of B10 and B8 = 1. Burst Suspend Waveform Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (s olid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. During Burst Suspend, CLK signal can be held low or high. CE A0-A21 I/O0-I/O15 AVD CLK OE VALID A CB WAIT(1) HIGH ZHIGH Z D0 D2 D3D1 D0 D1 D2D1 CE I/O0-I/O15 A0-A21 AVD CLK OE tCLK tCKH tCKL ... WAIT tCEAV tCE tAHAV tAAV tCECK tAHCK tAVCK tACK tCKAV tCKQV tCEQZ tQHCK tDF (2) (2) tOE

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 AC Word Load Waveforms 1 WE Controlled(1) Note: 1. After the high-to-low transition on AVD , AVD may remain low as long as the CLK input does not toggle. CE Controlled(1) Note: 1. After the high-to-low transition on AVD , AVD may remain low as long as the CLK input does not toggle. AC Word Load Characteristics 1 Symbol Parameter Min Max Units tAAV Address Valid to AVD High 10 ns tAHAV Address Hold Time from AVD High 9 ns tAVLP AVD Low Pulse Width 10 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tCESAV CE Setup to AVD 10 ns tWP CE or WE Low Pulse Width 35 ns tWPH CE or WE High Pulse Width 25 ns tWEAV WE High Time to AVD Low 25 ns tCEAV CE High Time to AVD Low 25 ns tDS tWEAV tDH tAAV tAHAV tAVLP tWP DATA VALID CE I/O0-I/O15 A0 -A22 AVD WE tDS tDH tAHAV tAVLP tWP DATA VALID CE I/O0-I/O15 A0 -A22 AVD WE tCESAV tCEAV tAAV

34 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 AC Word Load Waveforms 2 WE Controlled(1) Note: 1. The CLK input should not toggle. CE Controlled(1) Note: 1. The CLK input should not toggle. AC Word Load Characteristics 2 Symbol Parameter Min Max Units tAS Address Setup Time to WE and CE High 50 ns tAH Address Hold Time 0 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tWP CE or WE Low Pulse Width 35 ns tWPH CE or WE High Pulse Width 25 ns I/O0 - I/O15 A0 - A22 WE CE AVD VIL DATA VALID I/O0 - I/O15 A0 - A22 CE AVD VIL DATA VALID WE

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Program Cycle Waveforms Sector, Plane or Chip Erase Cycle Waveforms Notes: 1. Any address can be used to load data. 2. OE must be high only when WE and CE are both low. 3. The data can be 40H or 10H. 4. For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector is to be erased. 5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should be 20H. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Word Programming Time 22 µs tSEC1 Sector Erase Cycle Time (4K word sectors) 200 ms tSEC2 Sector Erase Cycle Time (32K word sectors) 700 ms tES Erase Suspend Time 15 µs tPS Program Suspend Time 10 µs tERES Delay between Erase Resume and Erase Suspend 500 µs OE PROGRAM CYCLE INPUT DATANote 3 ADDRESS tBPtWP CE WE AVD A0 - A22 I/O0 - I/O15 tWPH tAS tAH tDH tDS tWC XX (1) VIL OE (2) XX (1) WORD 0 WORD 1 Note 4 tWPH tWP CE WE A0 - A22 tAS tAH tSEC1/2 tDH tDStWC AVD I/O0 - I/O15 VIL Note 5

36 AT49SN/SV12804 [Preliminary]

Table 6. Common Flash Interface Definition for AT49SN/SV12804

Table 6. Common Flash Interface Definition for AT49SN/SV12804 (Continued)

38 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 AT49SN/SV12804 Ordering Information tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 70 30 0.01 AT49SN12804-70CI 56C3 Industrial (-40° to 85°C) 70 30 0.01 AT49SV12804-70TI 56T Industrial (-40° to 85°C) Package Type 56C3 56-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 56T 56-lead, Plastic Thin Small Outline Package (TSOP)

AT49SN/SV12804 [Preliminary] 3314A–FLASH–4/04 Packaging Information 56C3 – CBGA

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 56C3, 56-ball (8 x 7 Array), 8 x 10 x 1.0 mm Body, 0.75 mm Ball Pitch Ceramic Ball Grid Array Package (CBGA) A56C3 1/9/04 0.12 C Seating PlaneC 1.375 mm Ref D E Top View Side View A 87 6 5 4 3 21 Øb 2.75 mm Ref Bottom View A e e B C D E F G COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.00 A1 0.21 – – D 7.90 8.00 8.10 D1 5.25 TYP E 9.90 10.00 10.10 E1 4.50 TYP e 0.75 TYP Øb 0.35 TYP

40 AT49SN/SV12804 [Preliminary]

3314A–FLASH–4/04 56T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 56T, 56-lead (14 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) C56T 10/23/03 PIN 1 D1 D Pin 1 Identifier be E A 0º ~ 8º c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-142, Variation EC. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.20 18.40 18.60 Note 2 E 13.80 14.00 14.20 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.10 0.15 0.20 c 0.10 – 0.21 e 0.50 BASIC

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