AT49LH00B4-33JC

AT49LH00B4 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 36

Technical content

Features

 Complies with Intel® Low-Pin Count (LPC) Interface Specification Revision 1.1 – Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles  Auto-detection of FWH and LPC Memory Cycles – Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets – Can Be Used as LPC Flash for Non-Intel Chipsets  Top Boot with Bottom Partitioned Memory Array for Efficient Vital Data Storage – 64-Kbyte Top Boot Sector, Six 64-Kbyte Sectors, One 32-Kbyte Sector, One 16-Kbyte Sector, Two 8-Kbyte Sectors – Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing  Two Configurable Interfaces – FWH/LPC Interface for In-System Operation – Address/Address Multiplexed (A/A Mux) Interface for Programming during Manufacturing  FWH/LPC Interface – Operates with the 33 MHz PCI Bus Clock – 5-signal Communication Interface Supporting Byte Reads and Writes – Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All Other Sectors – Five General-purpose Input (GPI) Pins for System Design Flexibility – Identification (ID) Pins for Multiple Device Selection – Sector Locking Registers for Individual Sector Read and Write Protection  A/A Mux Interface – 11-pin Multiplexed Address and 8-pin Data Interface – Facilitates Fast In-System or Out-of-System Programming  Single Voltage Operation – 3.0V to 3.6V Supply Voltage for Read and Write Operations  Industry-Standard Package Options – 32-lead PLCC – 40-lead TSOP

Description

The AT49LH00B4 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec- ification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH00B4 to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets. 4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory AT49LH00B4 Pin Configurations PLCC Note: [ ] Designates A/A Mux Interface. [A7] GPI1 [A6] GPI0 [A5] WP [A4] TBL [A3] ID3 [A2] ID2 [A1] ID1 [A0] ID0 [I/O0] FWH0/LAD0 IC [IC] GND NC NC VCC INIT [OE] FWH4/LFRAME [WE] RES [RDY/BSY] RES [I/O7] [I/O1] FWH1/LAD1 [I/O2] FWH2/LAD2 GND [I/O3] FWH3/LAD3 [I/O4] RES [I/O5] RES [I/O6] RES GPI2 [A8] GPI3 [A9] RST [RST] NC VCC CLK [R/C] GPI4 [A10] TSOP NC [IC] IC NC NC NC NC [A10] GPI4 NC [R/C] CLK VCC NC [RST] RST NC NC [A9] GPI3 [A8] GPI2 [A7] GPI1 [A6] GPI0 [A5] WP [A4] TBL GND VCC FWH4/LFRAME [WE] INIT [OE] RES [RDY/BSY] RES [I/O7] RES [I/O6] RES [I/O5] RES [I/O4] VCC GND GND FWH3/LAD3 [I/O3] FWH2/LAD2 [I/O2] FWH1/LAD1 [I/O1] FWH0/LAD0 [I/O0] ID0 [A0] ID1 [A1] ID2 [A2] ID3 [A3]

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3379B–FLASH–9/03 The sectoring of the AT49LH00B4’s memory array has been optimized to meet the needs of today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space can be used more efficiently. Because certain BIOS code modules must reside in their own sectors by themselves, the wasted and unused memory space that occurred with previous generation BIOS Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional BIOS routines to be developed and added while still main- taining the same overall device density. The memory array of the AT49LH00B4 can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16- Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top (upper- most) of the device’s memory address space and can be hardware write protected by using the TBL pin. Alternatively, by using a different erase command, the memory array can be arranged into eight even erase sectors of 64-Kbyte each. The AT49LH00B4 supports two hardware interfaces: The FWH/LPC interface for In-System operations and the A/A Mux interface for programming during manufacturing. The Interface Configuration (IC) pin of the device provides the control between these two interfaces. An internal Command User Interface (CUI) serves as the control center between the device inter- faces and the internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation. Specifically designed for use in 3-volt systems, the AT49LH00B4 supports read, program, and erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required for programming and erasing. The AT49LH00B4 utilizes fixed program and erase times, independent of the number of pro- gram and erase cycles that have occurred. Therefore, the system does not need to be calibrated or correlated to the cumulative number of program and erase cycles. Block Diagram FLASH MEMORY ARRAY Y -GATING CONTROL LOGIC CLK FWH4/LFRAME FWH/LAD[3:0] R/C A[10:0] I/O[7:0] OE WE RDY/BSY ID[3:0] GPI[4:0] IC RST FWH/LPC INTERFACE A/A MUX INTERFACE Y -DECODER ADDRESS LATCH X-DECODER I/O BUFFERS AND LATCHES TBL WP INTERFACE CONTROL AND LOGIC INIT

both the FWH/LPC interface as well as the A/A Mux interface.

10 Main Sector 64K 070000H - 07FFFFH

9 Main Sector 64K 060000H - 06FFFFH

8 Main Sector 64K 050000H - 05FFFFH

7 Main Sector 64K 040000H - 04FFFFH

6 Main Sector 64K 030000H - 03FFFFH

5 Main Sector 64K 020000H - 02FFFFH

4 Main Sector 64K 010000H - 01FFFFH

3 Sub-sector 32K 008000H - 00FFFFH

2 Sub-sector 16K 004000H - 007FFFH

1 Sub-sector 8K 002000H - 003FFFH

0 Sub-sector 8K 000000H - 001FFFH

Table 1. Signal Descriptions interface, then the pin will exhibit some leakage current. usually connected to the 33 MHz PCI clock and adheres to the PCI specification. pin in the A/A Mux interface. This pin is used as the WE pin in the A/A Mux interface. information such as addresses, data, and command inputs/outputs. These pins are used as the I/O[3:0] pins in the A/A Mux interface. state, it will default to the read array mode.

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designed to be connected to the chipset’s INIT signal. specifications regarding the INIT pin voltage. This pin is used as the OE pin in the A/A Mux interface. the TBL pin does not affect the state of the Sector Locking Registers. This pin is used as the A4 pin in the A/A Mux interface. This pin is used as the A5 pin in the A/A Mux interface. low may be left floating. Any ID pin driven high will exhibit some leakage current. These pins are used as the A[3:0] pins in the A/A Mux interface. should remain at the same level until the end of the read cycle. requirements. Any unused GPI pins must not be left floating. These pins are used as the A[10:6] pins in the A/A Mux interface. and falling edge of R/C pin. Table 1. Signal Descriptions (Continued)

The I/O pins will be in a high-impedance state when the outputs are disabled. (A18 - A11) are latched on the rising edge of R/C. device’s output buffers during a read cycle. pin is optional, and the pin does not need to be connected. the voltage levels should comply with VIH and VIL requirements. These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface.

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when the IC pin is held high, the device will operate using the A/A Mux interface. tures, the FWH/LPC interface is the only way to get access to the full feature set of the device. fields. The field sequences and contents are strictly defined for FWH and LPC memory cycles. details the three valid START fields that the device will recognize. will also be placed in a high-impedance state. peripherals to know when to monitor the bus for a cycle. FWH/LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. Table 2. FWH/LPC Start Fields memory cycles are supported by the device.

(read/write), address, data, wait states, DMA channel, and bus master grant. MSIZE (Memory Size) field must be sent to indicate the number of bytes to transfer. Figure 1. FWH Memory Cycle Initiation and Addressing memory cycle. It may be a valid LPC memory cycle that the device will attempt to decode. the device will be directed to the memory array (A22 = 1) or to the register space (A22 = 0). Addresses are transferred to the device with the most significant nibble first. transfers, so 0000b must be sent in this field to indicate a single-byte transfer.

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FWH Read Cycle and FWH Write Cycle sections detail the order of the various fields. FWH/LAD[3:0] lines into a high-impedance state. to indicate that it is turning control of the LPC bus back over to the master. Table 3. Valid SYNC Values 0000b RSYNC (Ready SYNC) – Synchronization has been achieved with no error.

Figure 2. FWH Read Cycle Note: 1. Field contents are valid on the rising edge of the present clock cycle. Table 4. FWH Read Cycle

1 START 1101b IN FWH4/LFRAME must be active (low) for the device to

contents indicate a FWH memory read cycle. particular device will respond to subsequent commands. are transferred with the most significant nibble first.

10 MSIZE 0000b

IN The MSIZE field indicates how many bytes will be transferred.

11 TAR0 1111b IN then float In this clock cycle, the master has driven the bus to all 1s and

part of the bus “turn-around cycle”. 12 TAR1 1111b (float) Float then OUT The device takes control of the bus during this clock cycle. function of the device’s memory access time.

15 RSYNC 0000b (ready) OUT During this clock cycle, the device will generate a “ready”

byte will be available during the next clock cycle. 16 DAT A YYYY OUT YYYY is the least significant nibble of the data byte. 17 DAT A YYYY OUT YYYY is the most significant nibble of the data byte.

18 TAR0 1111b OUT then float The FWH memory device drives the bus to 1111b to indicate a

19 TAR1 1111b (float) Float then IN The FWH memory device floats its outputs, and the master

regains control of the bus during this clock cycle.

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the bus back over to the master. Figure 3. FWH Write Cycle Note: 1. Field contents are valid on the rising edge of the present clock cycle. Table 5. FWH Write Cycle respond to subsequent commands. most significant nibble first. device only supports single-byte operations, so MSIZE must be 0000b. 12 DATA YYYY IN YYYY is the most significant nibble of the data byte.

13 TAR0 1111b IN then float In this clock cycle, the master has driven the bus to all 1s and then

14 TAR1 1111b (float) Float then OUT The device takes control of the bus during this clock cycle.

15 RSYNC 0000b (ready) OUT During this clock cycle, the device will generate a “ready” SYNC

indicating that the data byte has been received.

16 TAR0 1111b OUT then float The FWH memory device drives the bus to 1111b to indicate a turn-

17 TAR1 1111b (float) Float then IN The FWH memory device floats its outputs, and the master regains

control of the bus during this clock cycle.

Figure 4. LPC Memory Cycle Initiation and Addressing start field that is sampled is not 0000b, then the cycle attempted is not an LPC memory cycle. It may be a valid FWH memory cycle that the device will attempt to decode. FWH/LAD[3:0] pins will also be placed in a high-impedance state. valid CYCTYPE + DIR fields that the device will respond to. be directed to the memory array (A23 = 1) or to the register space (A23 = 0). (see LPC Multiple Device Selection for mode details). Addresses are transferred to the device with the most significant nibble first. Table 6. Valid CYCTYPE + DIR Values

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LPC Read Cycle and LPC Write Cycle sections detail the order of the various fields. the FWH/LAD[3:0] lines into a high-impedance state. several clocks in length. On target cycles, this field is driven by the LPC memory device. Table 7. Valid SYNC Values 0000b RSYNC (Ready SYNC) – Synchronization has been achieved with no error.

Figure 5. LPC Read Cycle Note: 1. Field contents are valid on the rising edge of the present clock cycle. Table 8. LPC Read Cycle

1 START 0000b IN FWH4/LFRAME must be active (low) for the device to

contents indicate an LPC cycle.

2 CYCTYPE +

direction of the transfer is a read. 3 - 10 MADDR YYYY IN These eight clock cycles make up the 32-bit memory address. transferred with the most significant nibble first. part of the bus “turn-around cycle”. 12 TAR1 1111b (float) Float then OUT The device takes control of the bus during this clock cycle. function of the device’s memory access time. byte will be available during the next clock cycle. 16 DAT A YYYY OUT YYYY is the least significant nibble of the data byte. 17 DAT A YYYY OUT YYYY is the most significant nibble of the data byte.

18 TAR0 1111b OUT then float The LPC memory device drives the bus to 1111b to indicate a

19 TAR1 1111b (float) Float then IN The LPC memory device floats its outputs, and the master

regains control of the bus during this clock cycle.

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ing control of the bus back over to the master. Figure 6. LPC Write Cycle Note: 1. Field contents are valid on the rising edge of the present clock cycle. Table 9. LPC Write Cycle contents indicate an LPC cycle. direction of the transfer is a write. 3 - 10 MADDR YYYY IN These eight clock cycles make up the 32-bit memory address. transferred with the most significant nibble first. programmed into the memory array. 12 DAT A YYYY IN YYYY is the most significant nibble of the data byte.

13 TAR0 1111b IN then float In this clock cycle, the master has driven the bus to all 1s and

part of the bus “turn-around cycle”. 14 TAR1 1111b (float) Float then OUT The device takes control of the bus during this clock cycle. SYNC indicating that the data byte has been received.

16 TAR0 1111b OUT then float The LPC memory device drives the bus to 1111b to indicate a

17 TAR1 1111b (float) Float then IN The LPC memory device floats its outputs, and the master

regains control of the bus during this clock cycle.

3379B–FLASH–9/03 Response to Invalid FWH/LPC Fields During FWH/LPC operations, the device will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: FWH Cycles  ID mismatch: If the IDSEL field does not match ID[3:0], then the device will ignore the FWH cycle. The device will then enter standby mode when the FWH4/LFRAME pin is brought high and no internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high-impedance state.  Address out of range: The FWH address sequences is seven fields long (28 bits), but only the last six address fields (A23 - A0) will be decoded. Therefore, address bits A27 - A24 will be ignored. In addition, because of the device density, address bits A23 and A21 - A19 will be ignored. Address bit A22 is used to determine whether reads or writes to the device will be directed to the memory array (A22 = 1) or to the register space (A22 = 0).  Invalid MSIZE field: If the device receives an invalid size field during a read or write operation, the internal state machine will reset and no operation will be attempted. The device will generate no response of any kind in this situation. Invalid size fields for a read or write cycle are anything but 0000b. In addition, when accessing register space, invalid field sizes are anything but 0000b. Once valid START, IDSEL, and MSIZE fields are received, the device will always respond to subsequent inputs as if they were valid. As long as the states of FWH/LAD[3:0] and FWH4/LFRAME are known, the response of the device to signals received during the FWH cycle should be predictable. The device will make no attempt to check the validity of incoming Flash operation commands. LPC Cycles  Address out of range: The LPC address sequences is eight fields long (32 bits), but only the last six address fields (A23 - A0) will be decoded. Therefore, address bits A31 - A24 will be ignored. Address bits A22 - A19 will be decoded based on the strapping values on the ID[3:0] pins. Address bit A23 is used to determine whether reads or writes to the device will be directed to the memory array (A23 = 1) or to the register space (A23 = 0). Once valid START and CYCTYPE + DIR fields are received, the device will always respond to subsequent inputs as if they were valid. As long as the states of FWH/LAD[3:0] and FWH4/LFRAME are known, the response of the device to signals received during the LPC cycle should be predictable. The device will make no attempt to check the validity of incoming Flash operation commands. Bus Abort The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4/LFRAME is driven low for one or more clock cycles after the start of a bus cycle. The memory will place the FWH/LAD[3:0] pins in a high-impedance state, and the internal state machine will reset. During a write cycle, there is the possibility that an internal Flash write or erase operation may be in progress (or has just been initiated). If the FWH4/LFRAME pin is asserted during this time frame, the internal operation will not abort. However, the internal state machine will not initiate a Flash write or erase operation until it has received the last nibble from the host. This means that FWH4/LFRAME can be asserted as late as clock cycle 12 (see Table 5 and Table 9) and no internal Flash operation will be attempted. When the FWH4/LFRAME pin has been driven low to abort a cycle, the host may issue a START field of 1111b (stop/abort) to return the interface to the ready mode.

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3379B–FLASH–9/03 Device Reset Asserting RST or INIT initiates a device reset. In read mode, RST or INIT low deselects the memory, places the output drivers in a high-impedance state, and turns off all internal circuits. RST or INIT must be held low for the minimum specified tPLPH time (FWH/LPC and A/A Mux operations). The device resets to read array mode upon return from reset, and all Sector Lock- ing Registers are reset to their default (write-locked) state. Since all Sector Locking Registers are reset, all sectors in the memory array are set to the write-locked status regardless of their locked state prior to reset. A reset recovery time (t PHFV using the FWH/LPC interface and tPHAV using the A/A Mux inter- face) is required from RST or INIT switching back high until writes to the CUI are recognized. A reset latency will occur if a reset procedure is performed during a programming or erase operation. During sector erase or program, driving RST or INIT low will abort the operation underway in addition to causing a reset latency. Memory contents being altered are no longer valid since the data may be partially erased or programmed. It is important to assert RST or INIT during system reset. When the system comes out of reset, it will expect to read from the memory array of the device. If a system reset occurs with no FWH/LPC device reset (this will be hardware dependent), it is possible that proper CPU initial- ization will not occur (the FWH/LPC memory may be providing status information instead of memory array data). Sector Protection Sectors in the memory array can be protected from program and erase operations using a hardware controlled method and/or a software (register-based) controlled method. Hardware Write Protection Two pins are available to provide hardware write protection capabilities. The Top Boot Sector Lock (TBL) pin, when held low, prevents program and sector erase operations to the top sec- tor of the device (sector 10) where critical code can be stored. When the TBL pin is high, hardware write protection for program and erase operations to the top sector is disabled. Provided that the Write-Lock bits in the Sector Locking Registers are not set (detailed later), sector erase or program commands can then be issued to the device to erase the top 64-Kbyte sector (sector 10). The Write Protect (WP ) pin, which operates independently from the TBL pin, serves the same basic function as the TBL pin for the remaining sectors except the top boot sector. When the WP pin is held low, program and sector erase operations to sectors 9 through 0 will not be allowed.

new lock status will take place after the program or erase operation completes. longer locked. However, the register may still be set to Read-Lock the sector if desired. effect on the values or status of the Sector Locking Registers. for FWH and A23 for LPC), the register memory address will also differ. always default to a state of 01H. Table 10. Hardware Write Protection Options

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of a particular sector can be determined by reading the corresponding Read-Lock bit. WRITE LOCK : The default write status of all sectors upon power-up is write-locked (1 state). unlocked (0 state) by clearing the Write-Lock bit, provided that the Lock-Down bit is not set. new lock status will take place after the program or erase operation completes. tor Locking Registers will not read the state of the TBL or WP pins. reading the corresponding Lock-Down bit. Table 11. Sector Locking Registers

A General-purpose Input Register is provided to read the status of the GPI[4:0] pins when using the FWH/LPC interface. Table 12. Function of Sector Locking Bits 7:3 Reserved Reserved for future use. 2 Read-Lock 0 Sector is not read-locked. Normal read operations in the sector can occur. This is the default state. Read operations within the sector are prevented. Data read will be 00H. 1 Lock-Down 0 Sector is not locked down. The Read-Lock and Write-Lock bits may be changed. This is the default state. remain locked down until the device is reset (using the RST or INIT signals) or power-cycled. 0W r i t e - L o c k 0 Sector is not write-locked. Normal program and erase operations to the sector can occur. Program and erase operations to the sector are prevented. This is the default state. Table 13. Valid Sector Locking Register Values 07H Sector is read and write locked down. 06H Sector is read locked down. 05H Sector is read and write locked but not locked down. 04H Sector is read locked but not locked down. 03H Sector is write locked down. 02H Sector is locked open (full access locked down). 01H Sector is write locked but not locked down. This is the default state. 00H Sector is open for full access. Table 14. GPI Register Memory Address

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sequential up-count strapping. progress. The FWH/LAD[3:0] pins will also be placed in a high-impedance state. Table 15. General-purpose Input Register 7:5 Reserved Reserved for future use. 4 GPI_REG4 0 GPI4 input pin is at V IL. 3 GPI_REG3 0 GPI3 input pin is at V IL. 2 GPI_REG2 0 GPI2 input pin is at V IL. 1 GPI_REG1 0 GPI1 input pin is at V IL. 0 GPI_REG0 0 GPI0 input pin is at V IL. Table 16. FWH Multiple Device Selection

FWH/LAD[3:0] pins will also be placed in a high-impedance state. devices while still allowing the device to fit into low lead-count packages. purpose Input Register, are not available. Table 17. LPC Multiple Device Selection

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be drawn (see DC Specifications) when the pin is driven high. into the device on the rising edge of WE. The RST pin is used to reset the device. test equipment and PROM programmers. Notes: 1. X can be VIL or VIH for control and address input pins.

1. VIH and VIL refer to the DC characteristics associated with the Flash memory output buffers:
2. Refer to Table 21 for Product ID addresses and data.

row addresses on the falling edge and column addresses on the rising edge. program and erase cycles and is released at the completion of the cycle. Table 18. A/A Mux Interface Bus Operations

in Table 19 can be issued using either interface. the FWH/LPC interface, 19 FWH/LPC bus cycles are required. Notes: 1. The sector must not be hardware write protected or write-locked when attempting sector erase or program operations. Attempts to issue a sector erase or byte program command to a hardware write protected or write-locked sector will fail.

1. Sub-sectors are sectors 3, 2, 1, and 0; the main sectors are sectors 10 through 4. Refer to the Device Memory Map and

ing a single erase command to be used to erase any sector in the memory array.

1. Either 40H or 10H is recognized by the device as the byte program command.
2. Following the Product ID Read command, read operations will access manufacturer and device ID information. Refer to

Table 21 for Product ID addresses and data. Table 19. Command Definitions

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3379B–FLASH–9/03 READ ARRAY : Upon initial device power-up and after exit from reset, the device defaults to the read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written to the device. Once the internal write state machine (WSM) has started a sector erase or program operation, the device will not recognize the Read Array command until the operation is completed. SECTOR ERASE : Before a byte can be programmed into a sector, the sector must first be erased. The memory array is organized into multiple sectors that can be individually erased using two different sector erase commands, Sector Erase and Uniform Sector Erase. The Uni- form Sector Erase command can be used to erase the main sectors, and it can also be used to erase all of the sub-sectors to allow the memory array to be erased in uniform 64-Kbyte regions. The Sector Erase command is used to erase the individual sub-sectors to provide a more efficient and finer erase granularity. In addition, the Sector Erase command can be used to erase the main sectors as well to allow a single erase command to be used to erase any sector in the memory array. Both sector erase commands require two command cycles to ini- tiate the internally self-timed erase operation. After issuing a sector erase command, the device’s Status Register may be checked to deter- mine the status of the WSM and the erase operation. If the device detects a sector erase error, the Status Register should be cleared before the system software attempts any corrective actions. After a sector erase, the CUI remains in the Read Status Register mode until a new command is issued. Successful sector erase requires that the corresponding sector’s Write-Lock bit be cleared and the corresponding hardware write protect pin (TBL or WP) be inactive. If using the Uniform Sector Erase command to erase all of the sub-sectors, then all of the sub-sectors must have their Write-Lock bits cleared and the WP pin must be inactive. If a sector erase is attempted when the sector is locked, the sector erase will fail, and the reason for the failure will be indi- cated in the Status Register. The erased state of the memory bits is a logical “1” (erased state of a byte is FFH). BYTE PROGRAM : The device is programmed on a byte-by-byte basis. The Byte Program command requires two command cycles with the programming address and data being input on the second command cycle. The device will automatically generate the required internal programming pulses, and all programming operations are completely self-timed. Please note that the byte location being programmed must have already been erased to FFH. A “0” cannot be programmed back to a “1”; only an erase operation can convert “0”s to “1”s. After the Byte Program command is written, the device’s Status Register may be checked to determine the WSM status and the result of the program operation. If a program error is detected, the Status Register should be cleared before any corrective action is taken by the system software. After a byte program operation, the CUI remains in the Read Status Register mode until a new command is issued. A successful program operation also requires that the corresponding sector’s Write-Lock bit be cleared, and the corresponding hardware write protect pin (TBL or WP) be inactive. If a pro- gram operation is attempted when the sector is locked, the operation will fail, and the reason for the failure will be indicated in the Status Register. READ STATUS REGISTER : The Status Register (SR) may be read to determine when a sec- tor erase or program operation completes and whether the operation completed successfully. The Status Register may be read at any time by writing the Read Status Register command. After writing the Read Status Register command, all subsequent read operations will return data from the Status Register until another valid command is written to the device. CLEAR STATUS REGISTER : Error flags (SR[5,4,1]) in the Status Register can only be set to “1”s by the WSM and can only be reset by the Clear Status Register command. Therefore, if an error is detected, the Status Register must be cleared before beginning another operation to avoid ambiguity.

informs the system whether or not the selected sector is locked. device ID code. To exit the Product ID Read mode, any valid command can be written to the device. Table 20. Status Register (SR)

7 Write State Machine

A program or erase cycle is in progress. SR[6-1] values are invalid when SR[7] is 0. The device is ready for any operation. 6 Reserved Reserved for future use. 5E r a s e S t a t u s 0 Erase successful. The sector erase operation completed successfully. 4 Program Status 0 Program successful. The byte program operation competed successfully. The program operation failed. If SR[5,4] are 1, then there was a command sequence error. 3:2 Reserved Reserved for future use.

1 Device Protect

The sector being erased or programmed is unlocked (not protected). 1 Sector is hardware write protected or write-locked. WP pin, or it is write-locked. 0 Reserved Reserved for future use. Table 21. Product ID Address and Data

26 AT49LH00B4

3379B–FLASH–9/03 Notes: 1. All specified voltages are with respect to GND. During transitions, this level may undershoot to -2.0V for periods of <20 ns. During transitions, this level may overshoot to VCC + 2.0V for periods <20 ns. 2. Do not violate processor or chipset limitations on the INIT pin. Note: 1. The device is designed to operate at temperatures beyond the normal commercial temperature range of 0° C to +70° C. Notes: 1. All currents are in RMS unless otherwise noted. These currents are valid for all packages. 2. VIH = 0.9 VCC , VIL = 0.1 VCC per the PCI output VOH and VOL spec. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Conditions Temperature and VCC Symbol Parameter Test Condition Min Max Unit TC Operating Temperature(1) Case Temperature 0 +85 ° C VCC VCC Supply Voltage 3.0 3.6 V Power Supply Specifications – All Interfaces Symbol Parameter Conditions Min Max Units V LKO VCC Lockout Voltage 1.5 V ICCSL1 VCC Standby Current (FWH/LPC Interface) Voltage range of all inputs is VIH to VIL, FWH4/ LFRAME = VIH,(2) VCC = 3.6V, fCLK = 33 MHz No internal operations in progress 35 µA ICCSL2 VCC Standby Current (FWH/LPC Interface) FWH4/ LFRAME = VIL (2) VCC = 3.6V, fCLK = 33 MHz No internal operations in progress 2m A ICCA VCC Active Read Current (FWH/LPC Interface) VCC = VCC Max, FWH4/ LFRAME = VIL (2) fCLK = 33 MHz IOUT = 0 mA 20 mA IPP Program or Erase Current V CC = VCC Max 60 mA

3379B–FLASH–9/03 Notes: 1. Inputs are not “5-volt safe.” 2. Do not violate processor or chipset specifications regarding the INIT pin voltage. 3. Input leakage currents include high-Z output leakage for all bi-directional buffers with high-Z outputs. 4. I IL may be higher on the IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions 5. Refer to PCI spec. Notes: 1. PCI specification output load is used. 2. IOH = (98.0/VCC ) * (VOUT - VCC ) * (VOUT + 0.4 VCC ). 3. IOL = (256/VCC ) * VOUT (VCC - VOUT ). FWH/LPC Interface DC Input/Output Specifications Symbol Parameter Conditions Min Max Units VIH (1) Input High Voltage 0.5 V CC VCC + 0.5 V VIH (INIT)(1)(2) INIT Input High Voltage 1.35 V CC + 0.5 V VIL Input Low Voltage -0.5 0.3 V CC V VIL (INIT)(2) INIT Input Low Voltage 0.85 V IIL (3)(4) Input Leakage Current 0 < V IN < VCC ±10 µA VOH Output High Voltage I OUT = -500 µA 0.9 V CC V VOL Output Low Voltage I OUT = 1.5 mA 0.1 V CC V C IN Input Pin Capacitance 13 pF C CLK CLK Pin Capacitance 3 12 pF LPIN (5) Recommended Pin Inductance 20 nH FWH/LPC Interface AC Input/Output Specifications Symbol Parameter Condition Min Max Units IOH (AC) Switching Current High 0 < V OUT ≤ 0.3 VCC -12 VCC mA 0.3 VCC < VOUT < 0.9 VCC -17.1 (VCC - VOUT )m A

0.7 VCC < VOUT < VCC Note 2

(T est Point) V OUT = 0.7 VCC -32 VCC mA IOL (AC) Switching Current Low V CC > VOUT ≥ 0.6 VCC 16 VCC mA 0.6 VCC > VOUT > 0.1 VCC -17.1 (VCC - VOUT )m A

0.18 VCC > VOUT > 0 Note 3

(T est Point) V OUT = 0.18 VCC 38 VCC mA ICL Low Clamp Current -3 < V IN ≤ -1 -25 + (V IN + 1)/0.015 mA ICH High Clamp Current V CC + 4 > VIN ≥ VCC + 1 25 + (V IN - VCC - 1)/0.015 mA slewr Output Rise Slew Rate 0.2 V CC - 0.6 VCC load(1) 14 V / n s slewf Output Fall Slew Rate 0.6 V CC - 0.2 VCC load(1) 14 V / n s

28 AT49LH00B4

3379B–FLASH–9/03 FWH/LPC Interface AC Timing Specifications Notes: 1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than16 MHz may be guaranteed by design rather than testing. 2. Applies only to rising edge of signal. Clock Waveform Clock Specification Symbol Parameter Condition Min Max Units tCYC CLK Cycle Time(1) 30 ∞ ns tHIGH CLK High Time 11 ns tLOW CLK Low Time 11 ns – CLK Slew Rate peak-to-peak 1 4 V/ns –R S T or INIT Slew Rate(2) 50 mV/ns tCYC tHIGH tLOW0.6 VCC

0.5 VCC

0.4 VCC

0.3 VCC

0.4 VCC, p-to-p

(minimum)

0.2 VCC

3379B–FLASH–9/03 Notes: 1. Minimum and maximum times have different loads. See PCI spec. 2. For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. This parameter applies to any input type (excluding CLK). Output Timing Parameters Input Timing Parameters Signal Timing Parameters Symbol PCI Symbol Parameter Min Max Units tCHQX tVAL CLK to Data Out(1) 21 1 n s tCHQX tON CLK to Active (Float to Active Delay)(2) 2n s tCHQZ tOFF CLK to Inactive (Active to Float Delay)(2) 28 ns tAVCH tDVCH tSU Input Set-up Time(3) 7 n s tCHAX tCHDX tH Input Hold Time(3) 0 n s tVSPL tRST Reset Active Time after Power Stable 1 ms tCSPL tRST -CLK Reset Active Time after CLK Stable 100 µs tPLQZ tRST -OFF Reset Active to Output Float Delay(2) 48 ns tOFF tON tVAL VTH VTLVTESTCLK FWH/LAD[3:0] (Valid Output Data) FWH/LDA[3:0] (Float Output Data) tH VTH VTL VMAX VTESTCLK FWH/LAD[3:0] (Valid Input Data) tSU Inputs Valid

30 AT49LH00B4

3379B–FLASH–9/03 Note: 1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production testing may use different voltage values, but must correlate results back to these parameters. Note: 1. A reset latency of 20 µs will occur if a reset procedure is performed during a programming or erase operation. AC Waveform for Reset Operation Notes: 1. Typical values measured at TA = +25° C and nominal voltages. 2. Excludes system-level overhead. Interface Measurement Condition Parameters Symbol Value Units VTH (1) 0.6 VCC V VTL (1) 0.2 VCC V VTEST 0.4 VCC V VMAX (1) 0.4 VCC V Input Signal Edge Rate 1 V/ns Reset Operations Symbol Parameter Min Max Unit tPLPH (1) RST or INIT Pulse Low Time (If RST or INIT is tied to VCC , this specification is not applicable) 100 ns tPHFV RST or INIT High to FWH4/FRAME Low 1 µs Programming and Erase Times Parameter Typ (1) Max Unit Byte Program Time(2) 30 50 µs Sector Erase Time(2) 150 500 ms VIH VIL RST tPLPH tPHFV VIH VIL FWH4/LFRAME

3379B–FLASH–9/03 ELECTRICAL CHARACTERISTICS FOR A/A MUX INTERFACE: Certain specifications differ from the previous sections when programming using the A/A Mux interface. The following subsections provide this data. Any information that is not shown here is not specific to the A/A Mux interface and uses the FWH/LPC interface specifications. Notes: 1. Inputs are not “5-volt safe.” 2. Input leakage currents include high-Z output leakage for all bi-directional buffers with high-Z outputs. 3. IIL may be higher on the IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions. 4. Refer to PCI spec. Notes: 1. If RST is asserted when the WSM is not busy (RDY/BSY = 1), the reset will complete within 100 ns. 2. A reset recovery time, tPHAV , is required from the latter of RDY/BSY or RST going high until addresses are valid. AC Waveforms for Reset Operations A/A Mux Interface DC Input/Output Specifications Symbol Parameter Conditions Min Max Unit VIH (1) Input High Voltage 0.5 V CC VCC + 0.5 V VIL Input Low Voltage -0.5 0.8 V IIL (2)(3) Input Leakage Current V CC = VCC max, VOUT = VCC or GND +10 µA VOH Output High Voltage V CC = VCC min, IOH = -2.5 mA VCC = VCC min, IOH = -100 µA

0.85 VCC min

VCC = 0.4 V V VOL Output Low Voltage V CC = VCC min, IOL = 2 mA 0.4 V C IN Input Pin Capacitance 13 pF C CLK CLK Pin Capacitance 3 12 pF LPIN (4) Recommended Pin Inductance 20 nH Reset Operations Symbol Parameter Min Max Unit tPLPH RST Pulse Low Time (If RST is tied to VCC , this specification is not applicable.) 100 ns tPLRH RST Low to Reset during Sector Erase or Program(1)(2) 20 µs tPHAV RST High to Row Address Setup(2) 1µ s VIH VIL VIH VIL tPLPH tPHAV tPLRH tPHAV RDY/BSY RST VIH VIL ADDRESS

32 AT49LH00B4

3379B–FLASH–9/03 Note: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE may be delayed up to tCHQV - tGLQV after the rising edge of R/C without impact on tCHQV . 3. T C = 0° C to +85° C , VCC = 3.0V to 3.6V. A/A Mux Read Timing Diagram A/A Mux Interface Read-only Operations(1)(3) Symbol Parameter Min Max Units tAVAV Read Cycle Time 250 ns tAVCL Row Address Setup to R/C Low 50 ns tCLAX Row Address Hold from R/C Low 50 ns tAVCH Column Address Setup to R/C High 50 ns tCHAX Column Address Hold from R/C High 50 ns tCHQV R/C High to Output Delay(2) 150 ns tGLQV OE Low to Output Delay(2) 50 ns tPHAV RST High to Row Address Setup 1 µs tGLQX OE Low to Output in Low-Z 0 ns tGHQZ OE High to Output in High-Z 50 ns tQXGH Output Hold from OE High 0 ns VIH VIL R/C VIH VIL OE VIH VIL WE VIH VIL RST VOH VOL I/O VIH VIL ADDRESSES tGLQX tCHAX tAVCHtCLAX tAVCL tQXGH tGHQZ tGLQV tCHQV tPHAV tAVAV Row Address Stable Next Address Stable Data Valid High-ZHigh-Z Column Address Stable

3379B–FLASH–9/03 Note: 1. T C = 0° C to +85° C, VCC = 3.0V to 3.6V . A/A Mux Write Timing Diagram A/A Mux Interface Write Operations(1) Symbol Parameter Min Max Units tPHWL RST High Recovery to WE Low 1 µs tWLWH Write Pulse Width Low 100 ns tDVWH Data Setup to WE High 50 ns tWHDX Data Hold from WE High 5 ns tAVCL Row Address Setup to R/C Low 50 ns tCLAX Row Address Hold from R/C Low 50 ns tAVCH Column Address Setup to R/C High 50 ns tCHAX Column Address Hold from R/C High 50 ns tWHWL Write Pulse Width High 100 ns tCHWH R/C High Setup to WE High 50 ns tWHGL Write Recovery before Read 150 ns tWHSV Write Recovery before a Valid SRD (Status Register Data) Read 150 ns tWHRL WE High to RDY/BSY Going Low 0 ns VIH VIL R/C VIH VIL WE VOH VOL I/O VIH VIL RDY/BSY VIH VIL RST VIH VIL OE VIH VIL ADDRESSES tWHRL tWHDX tCHWH tCHAXtCLAX tAVCHtAVCL tWHWL tWLWH tDVWH tWHSV tWHGL tPHWL R1 C1 R2 C2 Valid SRDDINDIN AB C D E F NOTES A=V CC power-up and standby B = Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command

34 AT49LH00B4

3379B–FLASH–9/03

Ordering Information

ICC (mA) Ordering Code Package Operation RangeActive Standby 20 0.03 AT49LH00B4-33JC AT49LH00B4-33TC 32J 40T Extended Commercial (0° to 85° C) Package Type 32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP)

3379B–FLASH–9/03 Packaging Information 32J – PLCC DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131R TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B32J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 Note 2 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 Note 2 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP

Printed on recycled paper. 3379B–FLASH–9/03 xM Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza

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