AT49F1024 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 13

Technical content

Features

  • Single Voltage Operation – 5V Read – 5V Reprogramming
  • Fast Read Access Time - 45 ns
  • Internal Program Control and Timer
  • 8K word Boot Block With Lockout
  • Fast Erase Cycle Time - 10 seconds
  • Word By Word Programming - 10 µµµµs/Word Typical
  • Hardware Data Protection
  • DATA Polling For End Of Program Detection
  • Small 10 x 14 mm VSOP Package
  • Typical 10,000 Write Cycles

Description

The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash Memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The only difference between the AT49F1024 and the AT49F1025 is the pinout. The AT49F1024 is pin compatable with the AT27C1024, and the AT49F1025 is pin com- patable with the AT29C1024. Rev. 0765D–09/98 1-Megabit (64K x 16) 5-volt Only Flash Memory AT49F1024 AT49F1025 Pin Configurations Pin Name Function A0 - A15 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O15 Data Inputs/Outputs NC No Connect (continued) A T49F1024 VSOP T op View Type 1 10 x 14 mm A10 A11 A12 A13 A14 A15 NC WE VCC NC CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND

To allow for simple in-system reprogrammability, the AT49F1024/1025 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by erasing a block of data (entire chip or main memory block) and then programming on a word by word basis. The typi- cal word programming time is a fast 10 µs. The end of a program cycle can be optionally detected by the DATA poll- ing feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K words boot block section includes a repro- gramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is perma- nently protected from being erased or reprogrammed. Block Diagram Device Operation READ: The AT49F1024/1025 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in pre- venting bus contention. CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same chip erase com- mand (See command definitions table). If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory sec- tion will be erased. After a chip erase, the device will return to the read mode. MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block erase can be performed which will erase all bytes not located in the boot block region to an FFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six bus cycle operation. The address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE . The main memory erase starts after the rising edge of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The Main Memory Erase operation is internally controlled; it will automatically time to completion. WORD PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a word-by-word basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can con- vert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indi- cate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The OE, CE, AND WE LOGIC Y DECODER X DECODER INPUT/OUTPUT BUFFERS DATA LATCH Y-GATING OPTIONAL BOOT BLOCK (8K WORDS) MAIN MEMORY (56K WORDS) OE WE CE ADDRESS INPUTS VCC GND DATA INPUTS/OUTPUTS I/O15 - I/O0 1FFFH 0000H

size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti- vated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular pro- gramming method and can be erased using either the chip erase or the main memory block erase command. To acti- vate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the soft- ware product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 0002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lock- out feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F1024/1025 features DATA polling to indicate the end of a program or erase cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F1024/1025 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop tog- gling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F1024/1025 in the following ways: (a) V CC sense: if VCC is below 3.8V (typical), the program function is inhib- ited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.

Notes: 1. The DA T A FORMA T in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). 2. The 8K word boot sector has the address range 00000H to 1FFFH. 3. Either one of the Product ID Exit commands can be used. Command Definition (in Hex) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Main Memory Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 30 Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D IN Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (3) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit(3) 1x x x x F 0 Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE

Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 4. Manufacturer Code: 1FH, Device Code: 87H. 5. See details under Software Product Identification Entry/Exit. Note: 1. In the erase mode, I CC is 90 mA. DCand AC Operating Range AT49F1024/1025-45 AT49F1024/1025-55 AT49F1024/1025-70 AT49F1024/1025-90 Operating T emperature (Case) VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Operating Modes Mode CE OE WE Ai I/O Read V IL VIL VIH Ai D OUT Program(2) VIL VIH VIL Ai D IN Standby/Write Inhibit V IH X(1) X X High Z Program Inhibit X X V IH Program Inhibit X V IL X Output Disable X V IH X High Z Product Identification Hardware V IL VIL VIH A1 - A15 = VIL, A9 = VH ,(3) A0 = VIL Manufacturer Code(4) A1 - A15 = VIL, A9 = VH ,(3) A0 = VIH Device Code(4) Software(5) A0 = VIL, A1 - A15 = VIL Manufacturer Code(4) A0 = VIH, A1 - A15 = VIL Device Code(4) DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA Ind. 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3m A ICC (1) VCC Active Current f = 5 MHz; I OUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA 0.45 V VOH1 Output High Voltage I OH = -400 µA2 . 4 V VOH2 Output High Voltage CMOS I OH = -100 µA; VCC = 4.5V 4.2 V

AC Read Waveforms (1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level tR , tF < 5 ns Output Test Load Note: 1. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter AT49F1024-45 AT49F1025-45 AT49F1024-55 AT49F1025-55 AT49F1024-70 AT49F1025-70 AT49F1024-90 AT49F1025-90 UnitsMin Max Min Max Min Max Min Max tACC Address to Output Delay 45 55 70 90 ns tCE (1) CE to Output Delay 45 55 70 90 ns tOE (2) OE to Output Delay 0 30 30 35 0 40 ns tDF (3)(4) CE or OE to Output Float 0 25 0 25 0 25 0 25 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0000 n s OUTPUT PIN 5.0V 45/55/70 ns 90/120 ns 30 pF 1.8K 1.3K OUTPUT PIN 5.0V 100 pF 1.8K 1.3K Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V

AC Word Load Characteristics Symbol Parameter Min Max Units tAS , tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)9 0 n s tDS Data Set-up Time 50 ns tDH , tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 90 ns tDHtDS tAS tAH tWP CE ADDRESS DATA IN OE tOES tOEH WE tCS tCH tWPH tDHtDS tAS tAH tWP WE ADDRESS DATA IN OE tOES tOEH CE tCS tCH tWPH

Main Memory or Chip Erase Cycle Waveforms Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 10H. For a main memory erase the data should be 30H. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Word Programming Time 10 50 µs tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 90 ns tWPH Write Pulse Width High 90 ns tEC Erase Cycle Time 10 seconds A0-A15 OE AA80 NOTE 355 55 5555 5555 5555 AA WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 2AAA 2AAA tWPHtWP CE WE A0-A15 DATA tAS tAH tEC tDH tDS 5555

Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. T oggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns

Identification Entry(1) Software Product Identifcation Exit (1) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A15 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if pow- ered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 87H Boot Block Lockout Enable Algorithm(1) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. LOAD DA T A AA TO ADDRESS 5555 LOAD DA T A 55 TO ADDRESS 2AAA LOAD DA T A 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICA TION MODE (2)(3)(5) LOAD DA T A AA TO ADDRESS 5555 O R LOAD DA T A F0 TO ANY ADDRESS LOAD DA T A 55 TO ADDRESS 2AAA EXIT PRODUCT IDENTIFICA TION MODE (4) LOAD DA T A F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICA TION MODE (4) LOAD DA T A AA TO ADDRESS 5555 LOAD DA T A 55 TO ADDRESS 2AAA LOAD DA T A 80 TO ADDRESS 5555 LOAD DA T A AA TO ADDRESS 5555 LOAD DA T A 55 TO ADDRESS 2AAA LOAD DA T A 40 TO ADDRESS 5555 P AUSE 1 second(2)

Note: 1. The A T49F1024 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 45 50 0.1 A T49F1024-45VC 40V Commercial (0° to 70°C) 55 50 0.1 A T49F1024-55VC 40V Commercial (0° to 70°C) 50 0.3 A T49F1024-55VI 40V Industrial (-40° to 85°C) 70 50 0.1 A T49F1024-70VC 40V Commercial (0° to 70°C) 50 0.3 A T49F1024-70VI 40V Industrial (-40° to 85°C) 90 50 0.1 A T49F1024-90VC 40V Commercial (0° to 70°C) 50 0.3 A T49F1024-90VI 40V Industrial (-40° to 85°C) Package Type 40V 40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm)

Note: 1. The A T49F1025 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 45 50 0.1 A T49F1025-45JC A T49F1025-45VC 44J 40V Commercial (0° to 70°C) 55 50 0.1 A T49F1025-55JC A T49F1025-55VC 44J 40V Commercial (0° to 70°C) 50 0.3 A T49F1025-55JI A T49F1025-55VI 44J 40V Industrial (-40° to 85°C) 70 50 0.1 A T49F1025-70JC A T49F1025-70VC 44J 40V Commercial (0° to 70°C) 50 0.3 A T49F1025-70JI A T49F1025-70VI 44J 40V Industrial (-40° to 85°C) 90 50 0.1 A T49F1025-90JC A T49F1025-90VC 44J 40V Commercial (0° to 70°C) 50 0.3 A T49F1025-90JI A T49F1025-90VI 44J 40V Industrial (-40° to 85°C) Package Type 44J 44-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 40V 40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm)

.045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ *Controlling dimension: millimeters 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC 40V, 40-Lead, Plastic Thin Small Outline Package (VSOP) Dimensions in Millimeters and (Inches)*