AT49F020 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 10

Technical content

Features

  • Single Voltage Operation – 5V Read – 5V Reprogramming
  • Fast Read Access Time - 55 ns
  • Internal Program Control and Timer
  • 8K bytes Boot Block With Lockout
  • Fast Erase Cycle Time - 10 seconds
  • Byte By Byte Programming - 50 µs/Byte
  • Hardware Data Protection
  • DATA Polling For End Of Program Detection
  • Low Power Dissipation – 50 mA Active Current – 100 µA CMOS Standby Current
  • Typical 10,000 Write Cycles

Description

The AT49F020 is a 5-volt-only in-system Flash Memory. Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with Atmel’s advanced nonvola- tile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is dese- lected, the CMOS standby current is less than 100 µA. To allow for simple in-system reprogrammability, the AT49F020 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F020 is performed by erasing the entire 2 megabits of memory and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of pro- gram and erase cycles is in excess of 10,000 cycles. 2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT49F020 0567B-A–8/97 Pin Configurations Pin Name Function A0 - A17 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DIP Top View NC A16 A15 A12 I/O0 I/O1 I/O2 GND VCC WE A17 A14 A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Top View I/O0 A14 A13 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A12 A15 A16 NC VCC WE A17 TSOP Top View Type 1 A11 A13 A14 A17 WE VCC NC A16 A15 A12 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 (continued)

The optional 8K bytes boot block section includes a repro- gramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is perma- nently protected from being reprogrammed. Block Diagram Device Operation READ: The AT49F020 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus conten- tion. ERASURE: Before a byte can be reprogrammed, the 256K bytes memory array (or 248K bytes if the boot block fea- tured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load com- mands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is t EC . If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can con- vert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle oper- ation (please refer to the Command Definitions table). The device will automatically generate the required internal pro- gram pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti- vated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular pro- gramming method. To activate the lockout feature, a series of six program commands to specific addresses with spe- cific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the soft- ware product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lock- out feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. DATA INPUTS/OUTPUTS I/O0 - I/O7 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY (248K BYTES) OPTIONAL BOOT BLOCK (8K BYTES) OE, CE AND WE LOGIC Y DECODER X DECODER VCC GND OE WE CE ADDRESS INPUTS

PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F020 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F020 provides another method for determining the end of a pro- gram or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F020 in the following ways: (a) V CC sense: if VCC is below 3.8V (typ- ical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits pro- gram cycles. (c) Noise filter: pulses of less than 15 ns (typi- cal) on the WE or CE inputs will not initiate a program cycle. Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH. 2. Either one of the Product ID exit commands can be used. Command Definition (in Hex) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D IN Boot Block Lockout (1) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (2) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit (2) 1 XXXX F0 Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE

Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. V H = 12.0V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code 0BH. 5. See details under Software Product Identification Entry/Exit. Note: In the erase mode, ICC is 90 mA. DC and AC Operating Range AT49F020-55 AT49F020-70 AT49F020-90 Operating Temperature (Case) VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% Operating Modes Mode CE OE WE Ai I/O Read V IL VIL VIH Ai D OUT Program(2) VIL VIH VIL Ai D IN Standby/Write Inhibit V IH X(1) XX H i g h Z Program Inhibit X X V IH Program Inhibit X V IL X Output Disable X V IH XH i g h Z Product Identification Hardware V IL VIL VIH A1 - A17 = VIL, A9 = VH ,(3) A0 = VIL Manufacturer Code(4) A1 - A17 = VIL, A9 = VH ,(3) A0 = VIH Device Code(4) Software(5) A0 = VIL, A1 - A17=VIL Manufacturer Code(4) A0 = VIH, A1 - A17=VIL Device Code(4) DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA Ind. 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3m A ICC (1) VCC Active Current f = 5 MHz; I OUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA .45 V VOH1 Output High Voltage I OH = -400 µA2 . 4 V VOH2 Output High Voltage CMOS I OH = -100 µA; VCC = 4.5V 4.2 V

AC Read Waveforms (1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load Note: 1. This parameter is characterized and is not 100% tested. AC Read Characteristics AT49F020-55 AT49F020-70 AT49F020-90 Symbol Parameter Min Max Min Max Min Max Units tACC Address to Output Delay 55 70 90 ns tCE (1) CE to Output Delay 55 70 90 ns tOE (2) OE to Output Delay 0 30 0 35 0 40 ns tDF (3)(4) CE or OE t o O u t p u t F l o a t 02 502 502 5 n s tOH Output Hold from OE, CE or Address, whichever occurred first 000 n s Pin Capacitance(1) (f = 1 MHz, T = 25°C) Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V ADDRESS CE OUTPUT OE OUTPUT VALID tACC ADDRESS VALID HIGH Z tDF tCE tOH AC DRIVING LEVELS AC MEASUREMENT LEVEL0.0V 1.5V 3.0V tR , tF < 5 ns 100 pF1.3K 1.8K 5.0V OUTPUT PIN

AC Byte Load Characteristics Symbol Parameter Min Max Units tAS , tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)9 0 n s tDS Data Set-up Time 50 ns tDH , tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 90 ns ADDRESS CE DATA IN WE tWP tWPH tAH OE tOES tAS tOEH tCH tCS tDS tDH ADDRESS WE DATA IN CE tWP tWPH tAH OE tOES tAS tOEH tCH tCS tDS tDH

Chip Erase Cycle Waveforms Note: OE must be high only when WE and CE are both low. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Byte Programming Time 10 50 µs tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 90 ns tWPH Write Pulse Width High 90 ns tEC Erase Cycle Time 10 seconds CE WE DATA A0-A17 tBP tAH OE tAS tWPH tDS tDH tWP 5555 2AAA 5555 AA 55 A0 ADDRESS PROGRAM CYCLE INPUT DATA CE WE DATA A0-A17 tAH OE tAS tWPH tDS tDH tWP 5555 2AAA 5555 AA 55 80 5555 2AAA 5555 AA 55 10 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 tEC

Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics (1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay (2) ns tWR Write Recovery Time 0 ns Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns CE OE I/O7 tOE WE tDH An tOEH tWR A0-A17 An An AnAn CE OE I/O6 tOE WE tDH tOEHP HIGH Z tOEH tWR

Identification Entry(1) Software Product Identification Exit (1) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A17 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturers Code: 1FH Device Code: 0BH. Boot Block Lockout Feature Enable Algorithm(1) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE (2)(3)(5) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE (4) OR LOAD DATA AA TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE (4) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second(2)

Note: The AT49F020 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. Ordering Information (1) tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 55 50 0.1 AT49F020-55JC 32J Commercial AT49F020-55PC 32P6 (0 ° to 70°C) AT49F020-55TC 32T 50 0.3 AT49F020-55JI 32J Industrial AT49F020-55PI 32P6 (-40 ° to 85°C) AT49F020-55TI 32T 70 50 0.1 AT49F020-70JC 32J Commercial AT49F020-70PC 32P6 (0 ° to 70°C) AT49F020-70TC 32T 50 0.3 AT49F020-70JI 32J Industrial AT49F020-70PI 32P6 (-40 ° to 85°C) AT49F020-70TI 32T 90 50 0.1 AT49F020-90JC 32J Commercial AT49F020-90PC 32P6 (0 ° to 70°C) AT49F020-90TC 32T 50 0.3 AT49F020-90JI 32J Industrial AT49F020-90PI 32P6 (-40 ° to 85°C) AT49F020-90TI 32T Package Type 32J 32 Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32P6 32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32T 32 Lead, Thin Small Outline Package (TSOP)