AT49F001 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 16

Technical content

Features

  • Single Voltage Operation – 5V Read – 5V Reprogramming
  • Fast Read Access Time - 55 ns
  • Internal Program Control and Timer
  • Sector Architecture – One 16K Byte Boot Block with Programming Lockout – Two 8K Byte Parameter Blocks – Two Main Memory Blocks (32K, 64K) Bytes
  • Fast Erase Cycle Time - 10 seconds
  • Byte By Byte Programming - 10 µs/Byte Typical
  • Hardware Data Protection
  • DATA Polling for End of Program Detection
  • Low Power Dissipation – 50 mA Active Current – 100 µA CMOS Standby Current
  • Typical 10,000 Write Cycles

Description

The AT49F001(N)(T) is a 5-volt-only in-system reprogrammable Flash Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. Rev. 1008B–07/98 1-Megabit (128K x 8) 5-volt Only Flash Memory AT49F001 AT49F001N AT49F001T AT49F001NT Pin Configurations Pin Name Function A0 - A16 Addresses CE Chip Enable OE Output Enable WE Write Enable RESET RESET I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect DIP T op View * RESET A16 A15 A12 I/O0 I/O1 I/O2 GND VCC WE NC A14 A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC T op View I/O0 A14 A13 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A12 A15 A16 RESET * VCC WE NC (continued) VSOP Top View (8 x 14 mm) or TSOP T op View (8 x 20 mm) Type 1 A11 A13 A14 NC WE VCC * RESET A16 A15 A12 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 *Note: This pin is a DC on the AT49F001N(T).

AT49F001(N)(T)2 When the device is deselected, the CMOS standby current is less than 100 µA. For the AT49F001NT pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package are don’t connect pins. To allow for simple in-system reprogrammability, the AT49F001(N)(T) does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE , OE, and WE inputs to avoid bus conten- tion. Reprogramming the AT49F001(N)(T) is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or pro- gram can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The device is erased by executing the erase command sequence; the device internally controls the erase opera- tions. There are two 8K byte parameter block sections and two main memory blocks. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the fea- ture is enabled, the boot sector is protected from being reprogrammed. In the AT49F001N(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49F001(T), once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less. Block Diagram CONTROL LOGIC Y DECODER PARAMETER BLOCK 1 (8K BYTES) BOOT BLOCK (16K BYTES) OE WE CE RESET ADDRESS INPUTS VCC GND AT49F001(N)T DATA INPUTS/OUTPUTS I/O7 - I/O0 X DECODER PARAMETER BLOCK 2 (8K BYTES) MAIN MEMORY BLOCK 1 (32K BYTES) MAIN MEMORY BLOCK 2 (64K BYTES) PROGRAM DATA LATCHES Y-GATING INPUT/OUTPUT BUFFERS 1FFFF 1C000 1BFFF 1A000 19FFF 18000 17FFF 10000 0FFFF 00000 PARAMETER BLOCK 1 (8K BYTES) BOOT BLOCK (16K BYTES) AT49F001(N) DATA INPUTS/OUTPUTS I/O7 - I/O0 PARAMETER BLOCK 2 (8K BYTES) MAIN MEMORY BLOCK 1 (32K BYTES) MAIN MEMORY BLOCK 2 (64K BYTES) PROGRAM DATA LATCHES Y-GATING INPUT/OUTPUT BUFFERS 1FFFF 10000 0FFFF 08000 07FFF 06000 05FFF 04000 03FFF 00000

AT49F001(N)(T) Device Operation READ: The AT49F001(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus conten- tion. COMMAND SEQUENCES: When the device is first pow- ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respec- tively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address loca- tions used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some sys- tem applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedence state. If the RESET pin makes a high to low transition during a program or erase operation, the operation may not be sucessfully completed and the operation will have to be repeated after a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available for the AT49F001N(T). ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is t EC . If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Mem- ory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. SECTOR ERASE : As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections can be independently erased and repro- grammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the other block should be erased and reprogrammed before the first block is again erased. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can con- vert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indi- cate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti- vated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000 to 03FFF for the AT49F001(N) while the address

AT49F001(N)(T)4 range of the boot block is 1C000 to 1FFFF for the AT49F001(N)T. Once the feature is enabled, the data in the boot block can no longer be erased or programmed with input voltage lev- els of 5.5V or less. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program com- mands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the soft- ware product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out for the AT49F001(N) and a read from address 1C002H will show if programming the boot block is locked out for the AT49F001(N)T. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identi- fication exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts. By doing this, pro- tected boot block data can be altered through a chip erase, sector erase or word programming. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. This feature is not available on the AT49F001N(T). PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F001(N)(T) features DATA polling to indicate the end of a program cycle. During a pro- gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F001(N)(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop tog- gling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F001(N)(T) in the following ways: (a) V CC sense: if VCC is below 3.8V (typical), the program function is inhib- ited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.

AT49F001(N)(T) Command Definition (in Hex)(1) Notes: 1. The DA T A FORMA T in each bus cycle is as follows: I/O7 - I/O0 (Hex) 2. The 16K byte boot sector has the address range 00000H to 03FFFH for the A T49F001(N) and 1C000H to 1FFFFH for the A T49F001(N)T . 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses For the A T49F001(N): SA = 10000 to 1FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 04000 to 05FFF for P ARAMETER BLOCK 1 SA = 06000 to 07FFF for P ARAMETER BLOCK 2 SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2 For the A T49F001(N)T: SA = 1C000 to 1FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 1A000 to 1BFFF for P ARAMETER BLOCK 1 SA = 18000 to 19FFF for P ARAMETER BLOCK 2 SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2 Absolute Maximum Ratings* Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA (4) 30 Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D IN Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit(3) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit(3) 1 XXXX F0 mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE

AT49F001(N)(T)6 Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 4. Manufacturer Code: 1FH, Device Code: 05H - A T49F001(N), 04H - A T49F001(N)T 5. See details under Software Product Identification Entry/Exit. 6. This pin is not available on the A T49F001N(T). Note: 1. In the erase mode, ICC is 90 mA. DC and AC Operating Range AT49F001(N)(T)-55 AT49F001(N)(T)-70 AT49F001(N)(T)-90 AT49F001(N)(T)-12 Operating T emperature (Case) VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Operating Modes Mode CE OE WE RESET (6) Ai I/O Read V IL VIL VIH VIH Ai D OUT Program/Erase(2) VIL VIH VIL VIH Ai D IN Standby/Write Inhibit V IH X(1) XV IH X High Z Program Inhibit X X V IH VIH Program Inhibit X V IL XV IH Output Disable X V IH XV IH High Z Reset X X X V IL X High Z Product Identification Hardware VIL VIL VIH A1 - A16 = VIL, A9 = VH ,(3) A0 = VIL Manufacturer Code(4) A1 - A16 = VIL, A9 = VH ,(3) A0 = VIH Device Code(4) Software(5) A0 = VIL, A1 - A16=VIL Manufacturer Code(4) A0 = VIH, A1 - A16=VIL Device Code(4) DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA Ind. 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3m A ICC (1) VCC Active Current f = 5 MHz; I OUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA .45 V VOH1 Output High Voltage I OH = -400 µA2 . 4 V VOH2 Output High Voltage CMOS I OH = -100 µA; VCC = 4.5V 4.2 V

AT49F001(N)(T) AC Read Waveforms (1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveform and Measurement Level tR , tF < 5 ns Output Load Test Note: 1. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter AT49F001(N)(T)-50 AT49F001(N)(T)-70 AT49F001(N)(T)-90 AT49F001(N)(T)-12 UnitsMin Max Min Max Min Max Min Max tACC Address to Output Delay 50 70 90 120 ns tCE (1) CE to Output Delay 50 70 90 120 ns tOE (2) OE to Output Delay 0 30 0 35 0 40 0 50 ns tDF (3)(4) CE or OE to Output Float 0 25 0 25 0 25 0 30 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0000 n s ADDRESS OUTPUTHIGH ZOUTPUT OE CE tACC tOE tDF tOH tCE VALID ADDRESS VALID 55 ns 5.0V 1.8K 100 pF30 pF 1.3K 70/90/120 ns 5.0V 1.8K OUTPUT PIN 1.3K OUTPUT PIN Pin Capacitance (f = 1 MHz, T = 25°C)(1) Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V

AT49F001(N)(T)8 AC Byte Load Waveforms WE Controlled CE Controlled AC Byte Load Characteristics Symbol Parameter Min Max Units tAS , tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)9 0 n s tDS Data Set-up Time 50 ns tDH , tOEH Data, OE Hold Time 0n s tWPH Write Pulse Width High 90 ns tDHtDS tAS tAH tWP CE ADDRESS DATA IN OE tOES tOEH WE tCS tCH tWPH tDHtDS tAS tAH tWP WE ADDRESS DATA IN OE tOES tOEH CE tCS tCH tWPH

AT49F001(N)(T) Program Cycle Waveforms Sector or Chip Erase Cycle Waveforms Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under command definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Byte Programming Time 10 50 µs tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 90 ns tWPH Write Pulse Width High 90 ns tEC Erase Cycle Time 10 seconds OE PROGRAM CYCLE INPUT DATA ADDRESS A055 5555 5555 AA 2AAA tBPtWPHtWP CE WE A0-A16 DATA tAS tAH tDH tDS OE (1) AA80 Note 355 55 5555 5555 Note 2 AA BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 2AAA 2AAA tWPHtWP CE WE A0-A16 DATA tAS tAH tEC tDH tDS 5555

AT49F001(N)(T)10 Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. DATA Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. T oggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns HIGH Z An An An An An WE CE OE I/O7 A0-A16 tOEH tOE tDH tWR Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns WE CE OE I/O6 tOEH HIGH ZtDH tOE tWR tOEHP

AT49F001(N)(T) Software Product Identification Entry(1) Software Product Identification Exit (1) Notes for software product identification 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A16 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 05H - A T49F001(N) 04H - A T49F001(N)T Boot Block Lockout Feature Enable Algorithm(1) Notes for boot block lockout feature enable: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE (2)(3)(5) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE (4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE (4) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second(2)

AT49F001(N)(T)12 tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 55 50 0.1 A T49F001-55JC A T49F001-55PC A T49F001-55TC A T49F001-55VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001-55JI A T49F001-55PI A T49F001-55TI A T49F001-55VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 70 50 0.1 A T49F001-70JC A T49F001-70PC A T49F001-70TC A T49F001-70VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001-70JI A T49F001-70PI A T49F001-70TI A T49F001-70VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 90 50 0.1 A T49F001-90JC A T49F001-90PC A T49F001-90TC A T49F001-90VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001-90JI A T49F001-90PI A T49F001-90TI A T49F001-90VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 120 50 0.1 A T49F001-12JC A T49F001-12PC A T49F001-12TC A T49F001-12VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001-12JI A T49F001-12PI A T49F001-12TI A T49F001-12VI 32J 32P6 32T 32V Industrial (-40° to 85°C) Package Type 32J 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32P6 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32T 32-Lead, Plastic Thin Small Outline Package (TSOP) 32V 32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)

AT49F001(N)(T) tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 55 50 0.1 A T49F001N-55JC A T49F001N-55PC A T49F001N-55TC A T49F001N-55VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001N-55JI A T49F001N-55PI A T49F001N-55TI A T49F001N-55VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 70 50 0.1 A T49F001N-70JC A T49F001N-70PC A T49F001N-70TC A T49F001N-70VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001N-70JI A T49F001N-70PI A T49F001N-70TI A T49F001N-70VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 90 50 0.1 A T49F001N-90JC A T49F001N-90PC A T49F001N-90TC A T49F001N-90VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001N-90JI A T49F001N-90PI A T49F001N-90TI A T49F001N-90VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 120 50 0.1 A T49F001N-12JC A T49F001N-12PC A T49F001N-12TC A T49F001N-12VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001N-12JI A T49F001N-12PI A T49F001N-12TI A T49F001N-12VI 32J 32P6 32T 32V Industrial (-40° to 85°C) Package Type 32J 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32P6 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32T 32-Lead, Plastic Thin Small Outline Package (TSOP) 32V 32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)

AT49F001(N)(T)14 tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 55 50 0.1 A T49F001T -55JC A T49F001T -55PC A T49F001T -55TC A T49F001T -55VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001T -55JI A T49F001T -55PI A T49F001T -55TI A T49F001T -55VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 70 50 0.1 A T49F001T -70JC A T49F001T -70PC A T49F001T -70TC A T49F001T -70VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001T -70JI A T49F001T -70PI A T49F001T -70TI A T49F001T -70VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 90 50 0.1 A T49F001T -90JC A T49F001T -90PC A T49F001T -90TC A T49F001T -90VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001T -90JI A T49F001T -90PI A T49F001T -90TI A T49F001T -90VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 120 50 0.1 A T49F001T -12JC A T49F001T -12PC A T49F001T -12TC A T49F001T -12VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001T -12JI A T49F001T -12PI A T49F001T -12TI A T49F001T -12VI 32J 32P6 32T 32V Industrial (-40° to 85°C) Package Type 32J 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32P6 32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32T 32-Lead, Plastic Thin Small Outline Package (TSOP) 32V 32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)

AT49F001(N)(T) tACC (ns) I CC (mA) Ordering Code Package Operation Range 55 50 0.1 A T49F001NT -55JC A T49F001NT -55PC A T49F001NT -55TC A T49F001NT -55VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001NT -55JI A T49F001NT -55PI A T49F001NT -55TI A T49F001NT -55VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 70 50 0.1 A T49F001NT -70JC A T49F001NT -70PC A T49F001NT -70TC A T49F001NT -70VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001NT -70JI A T49F001NT -70PI A T49F001NT -70TI A T49F001NT -70VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 90 50 0.1 A T49F001NT -90JC A T49F001NT -90PC A T49F001NT -90TC A T49F001NT -90VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001NT -90JI A T49F001NT -90PI A T49F001NT -90TI A T49F001NT -90VI 32J 32P6 32T 32V Industrial (-40° to 85°C) 120 50 0.1 A T49F001NT -12JC A T49F001NT -12PC A T49F001NT -12TC A T49F001NT -12VC 32J 32P6 32T 32V Commercial (0° to 70°C) 50 0.3 A T49F001NT -12JI A T49F001NT -12PI A T49F001NT -12TI A T49F001NT -12VI 32J 32P6 32T 32V Industrial (-40° to 85°C) Package Type 32J 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32P6 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32T 32-Lead, Plastic Thin Small Outline Package (TSOP) 32V 32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)

AT49F001(N)(T) Packaging Information .045(1.14) X 45°PIN NO. 1 IDENTIFY .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(3.81) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) TYP .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS .453(11.5) .447(11.4) .495(12.6) .485(12.3) 1.67(42.4) 1.64(41.7) PIN .566(14.4) .530(13.5) .090(2.29) MAX .005(.127) MIN .065(1.65) .015(.381) .022(.559) .041(1.04) .630(16.0) .590(15.0)

15 REF

.690(17.5) .610(15.5) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) SEATING PLANE .220(5.59) MAX 1.500(38.10) REF *Controlling dimension: millimeters INDEX MARK 18.5(.728) 18.3(.720) 20.2(.795) 19.8(.780) 0.25(.010) 0.15(.006) 0.50(.020) BSC 7.50(.295) REF 8.20(.323) 0.15(.006) 0.05(.002)

5 REF

0.70(.028) 0.50(.020) 0.20(.008) 0.10(.004) *Controlling dimension: millimeters INDEX MARK 12.5(.492) 12.3(.484) 14.2(.559) 13.8(.543) 0.25(.010) 0.15(.006) 0.50(.020) BSC 7.50(.295) REF 8.10(.319) 0.15(.006) 0.05(.002) 0.70(.028) 0.50(.020) 0.20(.008) 0.10(.004) 32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE 32P6, 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) Dimensions in Inches and (Millimeters) 32T, 32-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* 32V, 32-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* JEDEC OUTLINE MO-142 BA