Download PDFAT49BV320C ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 32
Technical content
Features
- Single Voltage Read/Write Operation: 2.65V to 3.6V Access Time – 70 ns Sector Erase Architecture – Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout – Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout Fast Word Program Time – 12 µs Fast Sector Erase Time – 300 ms Suspend/Resume Feature for Erase and Program – Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation – 12 mA Active – 13 µA Standby VPP Pin for Write Protection WP Pin for Sector Protection RESET Input for Device Initialization Flexible Sector Protection TSOP and CBGA Package Options Top or Bottom Boot Block Configuration Available 128-bit Protection Register Minimum 100,000 Erase Cycles Common Flash Interface (CFI)
Description
The AT49BV320C(T) is a 2.7-volt 32-megabit Flash memory organized as 2,097,152 words of 16 bits each. The memory is divided into 71 sectors for erase operations. The device is offered in a 48-lead TSOP and a 47-ball CBGA package. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. 32-megabit (2M x 16) 3-volt Only Flash Memory AT49BV320C AT49BV320CT Pin Configurations Pin Name Function A0 - A20 Addresses CE Chip Enable OE Output Enable WE Write Enable RESET Reset VPP Write Protection I/O0 - I/O15 Data Inputs/Outputs NC No Connect VCCQ Output Power Supply WP Write Protect Rev. 3372D–FLASH–5/04
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3372D–FLASH–5/04 The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and er ase. The device has the capability to protect the data in any sector (see Flexible Sector Protection section). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or progr am on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The VPP pin provides data protection. When the V PP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 1.5V or above, normal program and erase opera- tions can be performed. CBGA Top View A B C D E F 1 234567 A13 A14 A15 A16 VCCQ GND A11 A10 A12 I/O14 I/O15 I/O7 WE I/O5 I/O6 I/O13 VPP RST I/O11 I/O12 I/O4 WP A18 A20 I/O2 I/O3 VCC A19 A17 I/O8 I/O9 I/O10 CE I/O0 I/O1 GND OE TSOP Top View Type 1 A15 A14 A13 A12 A11 A10 NC A20 WE RESET VPP WP A19 A18 A17 A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE
AT49BV320C(T) 3372D–FLASH–5/04 Block Diagram IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR OUTPUT MULTIPLEXER OUTPUT BUFFER INPUT BUFFER COMMAND REGISTER DATA REGISTER Y-GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH CE WE OE RESET WP VPP VCC GND Y-DECODER X-DECODER INPUT BUFFER ADDRESS LATCH I/O0 - I/O15 A0 - A20 MAIN MEMORY
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3372D–FLASH–5/04 Device Operation READ: When the AT49BV320C(T) is in the read mode, with CE and OE low and WE high, the data stored at the memory location determined by the address pins are asserted on the out- puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be in the read mode. In order to perform other device functions, a se ries of command sequences are entered into the device. The command sequences are shown in the “Command Definition” table on page 15 (I/O8 - I/O15 are don’t care inputs for th e command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address and data are latc hed by the first rising edge of CE or WE . Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read mode, depending upon the state of the control inputs. ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The individual sectors can be erased by using the Sector Erase command. SECTOR ERASE: The device is organized into 71 sectors (SA0 - SA70) that can be individu- ally erased. The Sector Erase command is a two-bus cycle operation. The sector address and the D0H Data Input command are latched on the rising edge of WE . The sector erase starts after the rising edge of WE of the second cycle provided t he given sector has not been pro- tected. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is tSEC. An attempt to erase a sector that has been protected will result in the operation terminating immediately. WORD PROGRAMMING: Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis. Programming is accomplished via the Internal Device command reg- ister and is a two-bus cycle operation. The dev ice will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Progr amming is completed after the specified t BP cycle time. If the program status bit is a “1”, the device was not able to verify that the program oper- ation was performed successfully. The status register indicates the programming status. While the program sequence executes, status bit I/O7 is “0”. While programming, the only valid com- mands are Read Status Register, Program Suspend and Program Resume. VPP PIN: The circuitry of the AT49BV320C(T) is des igned so that the device cannot be pro- grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 1.5V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating. READ STATUS REGISTER: The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the memory, issue a Read command. The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H when a Read Status Register command is issued.
read, or the status register will not indicate completion of a Program or Erase operation. the preferred operation (see Table 1). Note: 1. A Command Sequence Error is indica ted when SR1, SR3, SR4 and SR5 are set. Table 1. Status Register Bit Definition an Erase Resume command is issued. before the operation is verified by the WSM. until a Program Resume command is issued. 1 = Prog/Erase attempted on a locked sector; Operation aborted. aborted and the device is returned to read status mode. when polling the status register.
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3372D–FLASH–5/04 CLEAR STATUS REGISTER: The WSM can set status register bits 1 through 7 and can clear bits 2, 6 and 7; but, the WSM cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register command. By allowing the system software to control the resetting of these bits, sev- eral operations may be performed (such as cumulatively programming several addresses or erasing multiple sectors in sequence) before r eading the status register to determine if an error occurred during those operations. The status register should be cleared before beginning another operation. The Read command must be issued before data can be read from the memory array. The status register can also be cleared by resetting the device. FLEXIBLE SECTOR PROTECTION: The AT49BV320C(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently . Once either of these two modes is enabled, the contents of the selected sector is r ead-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a two- bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector. HARDLOCK AND WRITE PROTECT: The Hardlock sector protection mode operates in con- junction with the Write Protect (WP ) pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock Software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
Figure 1. Sector Locking State Diagram and the two bits of the sector-lock status D[1:0]. Table 2. Hardlock and Softlock Protection Configurations in Conjunction with WP command can unlock the sector. VCC/5V 1 0 0 Y es No sector is locked. command can unlock the sector. and the sector is not locked.
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sector will show if the sector is unlocked, softlocked, or hardlocked. Register, Product ID Entry, CFI Query and Program Resume. Table 3. Sector Protection Status
AT49BV320C(T) 3372D–FLASH–5/04 register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection regist er. After determining whether sector B is protected or not, or r eading the protection register, the Read command must be given to return to the read mode. CFI: Common Flash Interface (CFI) is a publis hed, standardized data structure that may be read from a flash device. CFI allows system so ftware to query the installed device to deter- mine the configurations, various electrical and timing parameters and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CF I Query mode is a one-bus cycle command which requires writing data 98h to any address. Th e CFI Query command can be written when the device is ready to read data or can also be wr itten when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 4 on page 27. To return to the read mode, issue the Read command. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the AT49BV320C (T) in the following ways: (a) V CC sense: if V CC is below 1.8V (typical), the program function is inhibited. (b) V CC power-on delay: once V CC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before pro- gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: V PP is less than V ILPP. (e) VPP power-on delay: once V PP has reached 0.9V, program and erase operations are inhibited for 100 ns. INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCCQ + 0.6V. OUTPUT LEVELS: For the AT49BV320C(T), output high levels (VOH) are equal to VCCQ - 0.1V els, VCCQ must be regulated to 2.0V ± 10%, while V CC must be regulated to 2.65V - 3.0V (for minimum power).
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3372D–FLASH–5/04 Word Program Flowchart Full Status Check Flowchart Program Suspend Loop Start Write 40, Word Address Write Data, Word Address Read Status Register SR7 = Full Status Check (If Desired) Program Complete Suspend? No Yes (Setup) (Confirm) Read Status Register Program Successful SR3 = SR1 = SR4 =
1 VPP Range
Full Status Check Procedure Bus Operation Command Comments Write Program Setup Data = 40 Addr = Location to program Write Data Data = Data to program Addr = Location to program Read None Status register data: Toggle CE or OE to update status register Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to set to the Read state. Bus Operation Command Comments Idle None Check SR3: 1 = VPP Error Idle None Check SR4: 1 = Data Program Error Idle None Check SR1: 1 = Sector locked; operation aborted SR3 MUST be cleared before the Write State Machine allows further program attempts. If an error is detected, clear the status register before continuing operations – only the Clear Status Register command clears the status register error bits.
AT49BV320C(T) 3372D–FLASH–5/04 Program Suspend/Resume Flowchart Read Status Register SR7 = SR2 = Read Data Program Completed Done Reading Program Resumed Read Data No Yes Write FF (Read Array) Write D0 Any Address (Program Resume) Write FF (Read Array) Start Write B0 Any Address (Program Suspend) Write 70 Any Address (Read Status) Program Suspend/Resume Procedure Bus Operation Command Comments Write Read Status Data = 70 Addr = Any address Write Program Suspend Data = B0 Addr = Any address Read None Status register data: Toggle CE or OE to update status register Addr = Any address Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Idle None Check SR2 1 = Program suspended 0 = Program completed Write Read Array Data = FF Addr = Any address Read None Read data from any word in the memory Write Program Resume Data = D0 Addr = Any address
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3372D–FLASH–5/04 Erase Suspend/Resume Flowchart Erase Completed Read Array Data Start Read Status Register SR7 = SR6 = Erase Resumed Done Reading Write 70, Any Address (Read Status) Write B0, Any Address (Erase Suspend) Write D0, Any Address(Erase Resume) Write FF (Read Array) Read Data Wr ite FF (Read Array) Erase Suspend/Resume Procedure Bus Operation Command Comments Write Read Status Data = 70 Addr = Any address Write Erase Suspend Data = B0 Addr = Any address Read None Status register data: Toggle CE or OE to update status register Addr = Any address Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Idle None Check SR6 1 = Erase suspended 0 = Erase completed Write Read or Program Data = FF or 40 Addr = Any address Read or Write None Read or program data from/to sector other than the one being erased Write Program Resume Data = D0 Addr = Any address
AT49BV320C(T) 3372D–FLASH–5/04 Sector Erase Flowchart Full Erase Status Check Flowchart Start No Suspend Erase
0 Yes
Write 20, Address Write D0, Address Read Status Register SR7 = Full Erase Status Check (If Desired) Erase Complete (E r a s e ) (Erase Confirm) Sector SectorSector Sector 1,1 Read Status Register Erase Successful SR1 = Sector Sector Locked Error SR3 = VPP Range Error SR4, SR5= Command Sequence Error SR5 = Erase Error Sector Sector Erase Procedure Full Erase Status Check Procedure Bus Operation Command Comments Write Sector Erase Setup Data = 20 Addr = Sector to be erased (SA) Write Erase Confirm Data = D0 Addr = Sector to be erased (SA) Read None Status register data: Toggle CE or OE to update status register data Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent sector erasures. Full status register check can be done after each sector erase, or after a sequence of sector erasures. Write FF after the last operation to enter read mode. Bus Operation Command Comments Idle None Check SR3: 1 = VPP Range Error Idle None Check SR4, SR5: Both 1 = Command Sequence Error Idle None Check SR5: 1 = Sector Erase Error Idle None Check SR1: 1 = Attempted erase of locked sector; erase aborted. SR1, SR3 must be cleared before the Write State Machine allows further erase attempts. Only the Clear Status Register command clears SR1, SR3, SR4, SR5. If an error is detected, clear the status register before attempting an erase retry or other error recovery.
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3372D–FLASH–5/04 Protection Register Programming Flowchart Full Status Check Flowchart Start Write C0, PR Address Write PR Address & Data Read Status Register SR7 = Full Status Check (If Desired) Program Complete (Program Setup) (Confirm Data) Read Status Register Data Program Successful = VPP Range Error Program Error Register Locked; Program Aborted SR3, SR4 SR3, SR4 SR3, SR4 Protection Register Programming Procedure Full Status Check Procedure Bus Operation Command Comments Write Program PR Setup Data = C0 Addr = First Location to Program Write Protection Program Data = Data to Program Addr = Location to Program Read None Status register data: Toggle CE or OE to update status register data Idle None Check SR7 1 = WSM Ready 0 = WSM Busy Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to return to the Read mode. Bus Operation Command Comments Idle None Check SR1, SR3, SR4: 0,1,1 = V PP Range Error Idle None Check SR1, SR3, SR4: 0,0,1 = Programming Error Idle None Check SR1, SR3, SR4: 1, 0,1 = Sector locked; operation aborted SR3 must be cleared before the Write State Machine allows further program attempts. Only the Clear Status Register command clears SR1, SR3, SR4. If an error is detected, clear the status register before attempting a program retry or other error recovery.
AT49BV320C(T) 3372D–FLASH–5/04 Notes: 1. The DATA FORMAT shown for each bus cycle is as follow s; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A20 through A8 are don’t care. 2. SA = sector address. Any word addres s within a sector can be used to designate the sector address (see pages 17 and 18 for details). 3. The status register bits are output on I/O7 - I/O0. 4. If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed. Command Definition in Hex(1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle Addr Data Addr Data Read 1 XX FF Sector Erase/Confirm 2 XX 20 SA (2) D0 Word Program 2 XX 40/10 Addr D IN Erase/Program Suspend 1 XX B0 Erase/Program Resume 1 XX D0 Product ID Entry 1 XX 90 Sector Softlock 2 XX 60 SA (2) 01 Sector Hardlock 2 XX 60 SA (2) 2F Sector Unlock 2 XX 60 SA (2) D0 Read Status Register 2 XX 70 XX D OUT (3) Clear Status Register 1 XX 50 Program Protection Register 2 XX C0 Addr D IN Lock Protection Register – Sector B 2 XX C0 80 FFFD Status of Sector B Protection 2 XX 90 80 D OUT (4) CFI Query 1 XX 98 Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on VPP
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3372D–FLASH–5/04 Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A20 - A8 = 0. Protection Register Addressing Table W o r d U s e S e c t o r A 7A 6A 5A 4A 3A 2A 1A 0
0 F a c t o r y A 10000001
1 F a c t o r y A 10000010
2 F a c t o r y A 10000011
3 F a c t o r y A 10000100
4 U s e r B 10000101
5 U s e r B 10000110
6 U s e r B 10000111
7 U s e r B 10001000
AT49BV320C(T) 3372D–FLASH–5/04 AT49BV320C – Sector Address Table Sector Size (Bytes/Words) Address Range (A20 - A0) SA0 8K/4K 00000 - 00FFF SA1 8K/4K 01000 - 01FFF SA2 8K/4K 02000 - 02FFF SA3 8K/4K 03000 - 03FFF SA4 8K/4K 04000 - 04FFF SA5 8K/4K 05000 - 05FFF SA6 8K/4K 06000 - 06FFF SA7 8K/4K 07000 - 07FFF SA8 64K/32K 08000 - 0FFFF SA9 64K/32K 10000 - 17FFF SA10 64K/32K 18000 - 1FFFF SA11 64K/32K 20000 - 27FFF SA12 64K/32K 28000 - 2FFFF SA13 64K/32K 30000 - 37FFF SA14 64K/32K 38000 - 3FFFF SA15 64K/32K 40000 - 47FFF SA16 64K/32K 48000 - 4FFFF SA17 64K/32K 50000 - 57FFF SA18 64K/32K 58000 - 5FFFF SA19 64K/32K 60000 - 67FFF SA20 64K/32K 68000 - 6FFFF SA21 64K/32K 70000 - 77FFF SA22 64K/32K 78000 - 7FFFF SA23 64K/32K 80000 - 87FFF SA24 64K/32K 88000 - 8FFFF SA25 64K/32K 90000 - 97FFF SA26 64K/32K 98000 - 9FFFF SA27 64K/32K A0000 - A7FFF SA28 64K/32K A8000 - AFFFF SA29 64K/32K B0000 - B7FFF SA30 64K/32K B8000 - BFFFF SA31 64K/32K C0000 - C7FFF SA32 64K/32K C8000 - CFFFF SA33 64K/32K D0000 - D7FFF SA34 64K/32K D8000 - DFFFF SA35 64K/32K E0000 - E7FFF SA36 64K/32K E8000 - EFFFF SA37 64K/32K F0000 - F7FFF
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3372D–FLASH–5/04 SA38 64K/32K F8000 - FFFFF SA39 64K/32K 100000 - 107FFF SA40 64K/32K 108000 - 10FFFF SA41 64K/32K 110000 - 117FFF SA42 64K/32K 118000 - 11FFFF SA43 64K/32K 120000 - 127FFF SA44 64K/32K 128000 - 12FFFF SA45 64K/32K 130000 - 137FFF SA46 64K/32K 138000 - 13FFFF SA47 64K/32K 140000 - 147FFF SA48 64K/32K 148000 - 14FFFF SA49 64K/32K 150000 - 157FFF SA50 64K/32K 158000 - 15FFFF SA51 64K/32K 160000 - 167FFF SA52 64K/32K 168000 - 16FFFF SA53 64K/32K 170000 - 177FFF SA54 64K/32K 178000 - 17FFFF SA55 64K/32K 180000 - 187FFF SA56 64K/32K 188000 - 18FFFF SA57 64K/32K 190000 - 197FFF SA58 64K/32K 198000 - 19FFFF SA59 64K/32K 1A0000 - 1A7FFF SA60 64K/32K 1A8000 - 1AFFFF SA61 64K/32K 1B0000 - 1B7FFF SA62 64K/32K 1B8000 - 1BFFFF SA63 64K/32K 1C0000 - 1C7FFF SA64 64K/32K 1C8000 - 1CFFFF SA65 64K/32K 1D0000 - 1D7FFF SA66 64K/32K 1D8000 - 1DFFFF SA67 64K/32K 1E0000 - 1E7FFF SA68 64K/32K 1E8000 - 1EFFFF SA69 64K/32K 1F0000 -1F7FFF SA70 64K/32K 1F8000 - 1FFFF AT49BV320C – Sector Address Table (Continued) Sector Size (Bytes/Words) Address Range (A20 - A0)
AT49BV320C(T) 3372D–FLASH–5/04 AT49BV320CT – Sector Address Table Sector Size (Bytes/Words) Address Range (A20 - A0) SA0 64K/32K 00000 - 07FFF SA1 64K/32K 08000 - 0FFFF SA2 64K/32K 10000 - 17FFF SA3 64K/32K 18000 - 1FFFF SA4 64K/32K 20000 - 27FFF SA5 64K/32K 28000 - 2FFFF SA6 64K/32K 30000 - 37FFF SA7 64K/32K 38000 - 3FFFF SA8 64K/32K 40000 - 47FFF SA9 64K/32K 48000 - 4FFFF SA10 64K/32K 50000 - 57FFF SA11 64K/32K 58000 - 5FFFF SA12 64K/32K 60000 - 67FFF SA13 64K/32K 68000 - 6FFFF SA14 64K/32K 70000 - 77FFF SA15 64K/32K 78000 - 7FFFF SA16 64K/32K 80000 - 87FFF SA17 64K/32K 88000 - 8FFFF SA18 64K/32K 90000 - 97FFF SA19 64K/32K 98000 - 9FFFF SA20 64K/32K A0000 - A7FFF SA21 64K/32K A8000 - AFFFF SA22 64K/32K B0000 - B7FFF SA23 64K/32K B8000 - BFFFF SA24 64K/32K C0000 - C7FFF SA25 64K/32K C8000 - CFFFF SA26 64K/32K D0000 - D7FFF SA27 64K/32K D8000 - DFFFF SA28 64K/32K E0000 - E7FFF SA29 64K/32K E8000 - EFFFF SA30 64K/32K F0000 - F7FFF SA31 64K/32K F8000 - FFFFF SA32 64K/32K 100000 - 107FFF SA33 64K/32K 108000 - 10FFFF SA34 64K/32K 110000 - 117FFF SA35 64K/32K 118000 - 11FFFF SA36 64K/32K 120000 - 127FFF SA37 64K/32K 128000 - 12FFFF
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3372D–FLASH–5/04 SA38 64K/32K 130000 - 137FFF SA39 64K/32K 138000 - 13FFFF SA40 64K/32K 140000 - 147FFF SA41 64K/32K 148000 - 14FFFF SA42 64K/32K 150000 - 157FFF SA43 64K/32K 158000 - 15FFFF SA44 64K/32K 160000 - 167FFF SA45 64K/32K 168000 - 16FFFF SA46 64K/32K 170000 - 177FFF SA47 64K/32K 178000 - 17FFFF SA48 64K/32K 180000 - 187FFF SA49 64K/32K 188000 - 18FFFF SA50 64K/32K 190000 - 197FFF SA51 64K/32K 198000 - 19FFFF SA52 64K/32K 1A0000 - 1A7FFF SA53 64K/32K 1A8000 - 1AFFFF SA54 64K/32K 1B0000 - 1B7FFF SA55 64K/32K 1B8000 - 1BFFFF SA56 64K/32K 1C0000 - 1C7FFF SA57 64K/32K 1C8000 - 1CFFFF SA58 64K/32K 1D0000 - 1D7FFF SA59 64K/32K 1D8000 - 1DFFFF SA60 64K/32K 1E0000 - 1E7FFF SA61 64K/32K 1E8000 - 1EFFFF SA62 64K/32K 1F0000 - 1F7FFF SA63 8K/4K 1F8000 - 1F8FFF SA64 8K/4K 1F9000 - 1F9FFF SA65 8K/4K 1FA000 - 1FAFFF SA66 8K/4K 1FB000 - 1FBFFF SA67 8K/4K 1FC000 - 1FCFFF SA68 8K/4K 1FD000 - 1FDFFF SA69 8K/4K 1FE000 - 1FEFFF SA70 8K/4K 1FF000 - 1FFFFF AT49BV320CT – Sector Address Table (Continued) Sector Size (Bytes/Words) Address Range (A20 - A0)
AT49BV320C(T) 3372D–FLASH–5/04 Notes: 1. X can be V IL or VIH. 2. Refer to AC programming waveforms on page 26. 4. Manufacturer Code: 001FH, Device Code : 88C5H – AT49BV320C; 88C4H – AT49BV320CT 5. V IHPP (min) = 0.9V; VIHPP (max) = 1.95V. 6. V ILPP (max) = 0.4V. DC and AC Operating Range AT49BV320C(T)-70 Operating Temperature (Case) Ind. -40°C - 85°C VCC Power Supply 2.65V to 3.6V Operating Modes Mode CE OE WE RESET VPP Ai I/O Read V IL VIL VIH VIH XA i D OUT Program/Erase(2) VIL VIH VIL VIH VIHPP (5) Ai D IN Standby/Program Inhibit V IH X(1) XV IH X X High-Z Program Inhibit XX V IH VIH X XV IL XV IH X XXX V IH VILPP (6) Output Disable X V IH XV IH X High-Z R e s e t XXX V IL X X High-Z Product Identification Software V IH A0 = VIL, A1 - A20 = VIL Manufacturer Code(4) A0 = VIH, A1 - A20 = VIL Device Code(4)
22 AT49BV320C(T)
3372D–FLASH–5/04 Note: 1. In the erase mode, I CC is 65 mA. DC Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current V IN = 0V to VCC 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC 13 25 µA ICC (1) VCC Active Read Current f = 5 MHz; I OUT = 0 mA 12 25 mA ICC1 VCC Programming Current 45 mA IPP1 VPP Input Load Current 10 µA VIL Input Low Voltage 0.4 V VIH Input High Voltage V CCQ - 0.2 V VOL Output Low Voltage I OL = 100 µA 0.10 V VOH Output High Voltage I OH = -100 µA V CCQ - 0.1 V
AT49BV320C(T) 3372D–FLASH–5/04 AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characteri zed and is not 100% tested. AC Read Characteristics Symbol Parameter AT49BV320C(T)-70 UnitsMin Max tRC Read Cycle Time 70 ns tACC Address to Output Delay 70 ns tCE (1) CE to Output Delay 70 ns tOE (2) OE to Output Delay 0 20 ns tDF (3)(4) CE or OE to Output Float 0 25 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0n s tRO RESET to Output Delay 100 ns OUTPUT VALID OUTPUT HIGH Z RESET OE tOE tCE ADDRESS VALID tDF tOHtACC tRO CE ADDRESS tRC
24 AT49BV320C(T)
3372D–FLASH–5/04 Input Test Waveforms and Measurement Level tR, tF < 5 ns Output Test Load Note: This parameter is characte rized and is not 100% tested. VCC/2 VCC VCCQ Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V
AT49BV320C(T) 3372D–FLASH–5/04 AC Word Load Waveforms WE Controlled CE Controlled AC Word Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time 45 ns tAH Address Hold Time 0 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)4 0 n s tDS Data Setup Time 45 ns tDH, tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 30 ns
26 AT49BV320C(T)
3372D–FLASH–5/04 Program Cycle Waveforms Sector Erase Cycle Waveforms Notes: 1. Any address can be used to load the data. 2. OE must be high only when WE and CE are both low. 3. The data can be 40H or 10H. 4. The address depends on what sector is to be erased. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Word Programming Time 12 120 µs tAS Address Setup Time 45 ns tAH Address Hold Time 0n s tDS Data Setup Time 45 ns tDH Data Hold Time 0n s tWP Write Pulse Width 40 ns tWPH Write Pulse Width High 30 ns tWC Write Cycle Time 70 ns tRP Reset Pulse Width 500 ns tSEC1 Sector Erase Cycle Time (4K Word Sectors) 0.3 3.0 seconds tSEC2 Sector Erase Cycle Time (32K Word Sectors) 0.8 6.0 seconds tES Erase Suspend Time 15 µs tPS Program Suspend Time 20 µs OE PROGRAM CYCLE INPUT DATANote 3 ADDRESS tBPtWP CE WE A0 - A20 DATA tWPH tAS tAH tDH tDS tWC XX (1) OE (2) XX (1) WORD 0 WORD 1 SA (4) tWPH tWP CE WE A0-A20 DATA tAS tAH tEC tDH tDStWC
Table 4. Common Flash Interface Definition
28 AT49BV320C(T)
Table 4. Common Flash Interface Definition (Continued)
AT49BV320C(T) 3372D–FLASH–5/04 AT49BV320C(T) Ordering Information tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 70 25 0.025 AT49BV320C-70CI AT49BV320C-70TI 47C1 48T Industrial (-40° to 85° C) 70 25 0.025 AT49BV320CT -70CI AT49BV320CT -70TI 47C1 48T Industrial (-40° to 85° C) Package Type 47C1 47-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 48T 48-lead, Plastic Thin Small Outline Package (TSOP)
30 AT49BV320C(T)
3372D–FLASH–5/04 Packaging Information 47C1 – CBGA
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 47C1, 47-ball (8 x 6 Array), 0.75 mm Pitch, 7.0 x 10.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA) A47C1 7/2/03 TOP VIEW A1 BALL ID SIDE VIEW A B C D E F 7 65432 1 D BOTTOM VIEW E e
0.875 REF
3.125 REF
b A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE E 6.90 7.00 7.10 E1 5.25 TYP D 9.90 10.00 10.10 D1 3.75 TYP A – – 1.00 A1 0.22 – – e 0.75 BSC b 0.35 TYP
AT49BV320C(T) 3372D–FLASH–5/04 48T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) B48T 10/18/01 PIN 1 0º ~ 8º D1 D Pin 1 Identifier be E AA2 c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 11.90 12.00 12.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC
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