Download PDFAT49BV8192A-11TI ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 16
Technical content
Features
- Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time – 90 ns Internal Erase/Program Control Sector Architecture – One 8K Word (16K Bytes) Boot Block with Programming Lockout – Two 4K Word (8K Bytes) Parameter Blocks – One 496K Word (992K Bytes) Main Memory Array Block Fast Sector Erase Time – 10 seconds Byte-by-byte or Word-by-word Programming – 30 µs Typical Hardware Data Protection Data Polling for End of Program Detection Low Power Dissipation – 25 mA Active Current – 50 µA CMOS Standby Current Typical 10,000 Write Cycles
Description
The AT49BV008A(T) and AT49BV8192A(T) are 3-volt, 8-megabit Flash memories organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufac- tured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 90 ns with power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50 µA. The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available: the AT49BV008A/8192A locates the boot block at lowest order addresses (“bottom boot”); the AT49BV008AT/8192AT locates it at highest order addresses (“top boot”). To allow for simple in-system reprogrammability, the AT49BV008A(T)/8192A(T) does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE , OE and WE inputs to avoid 8-megabit (1M x 8/ 512K x 16) Flash Memory AT49BV008A AT49BV008AT AT49BV8192A AT49BV8192AT AT49LV8192A Rev. 1049I–03/01 Pin Configurations Pin Name Function A0 - A18 Addresses CE Chip Enable OE Output Enable WE Write Enable RESET Reset RDY/BUSY Ready/Busy Output VPP VPP can be left unconnected or connected to VCC, GND, 5V or 12V . The input has no effect on the operation of the device. I/O0 - I/O14 Data Inputs/Outputs I/O15 (A-1) I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) BYTE Selects Byte or Word Mode NC No Connect (continued)
AT49BV008A(T)/8192A(T)2 bus contention. Reprogramming the AT49BV008A(T)/ 8192A(T) is performed by first erasing a block of data and then by programming on a byte-by-byte or word-by-word basis. The device is erased by executing the Erase command sequence; the device internally controls the erase opera- tion. The memory is divided into four blocks for erase oper- ations. There are two 4K word parameter block sections, the boot block, and the main memory array block. The typi- cal number of program and erase cycles is in excess of 10,000 cycles. The optional 8K word boot block section includes a repro- gramming lock out feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 5.5 volts or less are used. The boot sector is designed to con- tain user secure code. For the AT49BV8192A(T), the BYTE pin controls whether the device data I/O pins operate in the byte or word config- uration. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the device is in byte con- figuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE . The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function. AT49BV8192A(T) TSOP Top View Type 1 A15 A14 A13 A12 A11 A10 NC NC WE RESET VPP NC NC A18 A17 A16 BYTE GND I/O15 / A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE AT49BV008A(T) TSOP Top View Type 1 A16 A15 A14 A13 A12 A11 WE RESET VPP RDY/BUSY A18 A17 GND NC A-1 A10 I/O7 I/O6 I/O5 I/O4 VCC VCC NC I/O3 I/O2 I/O1 I/O0 OE GND CE AT49BV8192A(T) CBGA Top View (Ball Down) A B C D E F 1 234567 A13 A14 A15 A16 BYTE GND A11 A10 A12 I/O14 I/O15 I/O7 WE I/O5 I/O6 I/O13 VPP RST NC I/O11 I/O12 I/O4 NC A18 NC I/O2 I/O3 VCC NC A17 I/O8 I/O9 I/O10 CE I/O0 I/O1 GND OE AT49BV008A(T) Standard Pin Definition CBGA Top View (Ball Down) A B C D E F 1 234567 A13 A14 A15 A16 NC GND A11 A10 A12 NC A-1 I/O7 WE I/O5 I/O6 NC VPP RST NC NC NC I/O4 NC A18 NC I/O2 I/O3 VCC NC A17 NC NC NC CE I/O0 I/O1 GND OE AT49BV008A(T) Alternate Pin Definition CBGA Top View (Ball Down) A B C D E F 1 234567 A14 A15 A16 A17 NC GND A12 A10 A13 NC A11 I/O7 WE I/O5 I/O6 NC VPP RST NC NC NC I/O4 NC A19 NC I/O2 I/O3 VCC NC A18 NC NC NC CE I/O0 I/O1 GND OE AT49BV8192A(T) SOIC (SOP) Top View VPP A18 A17 CE GND OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 RESET WE A10 A11 A12 A13 A14 A15 A16 BYTE GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC Note: “” denotes a white dot on the package.
AT49BV008A(T)/8192A(T) AT49BV008A(T) Block Diagram AT49BV8192A(T) Block Diagram Device Operation READ: The AT49BV008A(T)/8192A(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in pre- venting bus contention. COMMAND SEQUENCES: When the device is first pow- ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respec- tively) and OE high. The address is latched on the falling edge of CE or WE , whichever occurs last. The data is latched by the first rising edge of CE or WE . Standard microprocessor write timings are used. The address loca- tions used in the command sequences are not affected by entering the command sequences. VPP VCC GND OE CONTROL LOGIC DATA INPUTS/OUTPUTS I/O0 - I/O7 DATA INPUTS/OUTPUTS I/O0 - I/O7 WE CE RESET ADDRESS INPUTS Y DECODER INPUT/OUTPUT BUFFERS INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES PROGRAM DATA LATCHES Y-GATING AT49BV008A AT49BV008AT Y-GATING FFFFF FFFFFMAIN MEMORY (992K BYTES) BOOT BLOCK 16K BYTES PARAMETER BLOCK 2 8K BYTES PARAMETER BLOCK 1 8K BYTES PARAMETER BLOCK 1 8K BYTES PARAMETER BLOCK 2 8K BYTES BOOT BLOCK 16K BYTES MAIN MEMORY (992K BYTES) 08000 07FFF FC000 FBFFF 06000 05FFF FA000 F9FFF X DECODER 04000 03FFF F8000 F7FFF 00000 00000 VPP VCC GND OE CONTROL LOGIC DATA INPUTS/OUTPUTS I/O0 - I/O15 DATA INPUTS/OUTPUTS I/O0 - I/O15 WE CE RESET ADDRESS INPUTS Y DECODER INPUT/OUTPUT BUFFERS INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES PROGRAM DATA LATCHES Y-GATING AT49BV8192A AT49BV8192AT Y-GATING 7FFFF 7FFFFMAIN MEMORY (496K WORDS) BOOT BLOCK 8K WORDS PARAMETER BLOCK 2 4K WORDS PARAMETER BLOCK 1 4K WORDS PARAMETER BLOCK 1 4K WORDS PARAMETER BLOCK 2 4K WORDS BOOT BLOCK 8K WORDS MAIN MEMORY (496K WORDS) 04000 03FFF 7E000 7DFFF 03000 02FFF 7D000 7CFFF X DECODER 02000 01FFF 7C000 7BFFF 00000 00000
AT49BV008A(T)/8192A(T)4 RESET: A RESET input pin is provided to ease some sys- tem applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET pin the boot block array can be repro- grammed even if the boot block program lockout feature has been enabled (see Boot Block Programming Lockout Override section). ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased state of memory bits is a logic “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands. CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t EC. If the boot block lockout has been enabled, the chip erase will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four sectors that can be individually erased. There are two 4K word parameter block sections, one boot block, and the main memory array block. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE . The sector erase starts after the ris- ing edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. Whenever the main memory block is erased and repro- grammed, the two parameter blocks should be erased and reprogrammed before the main memory block is erased again. Whenever a parameter block is erased and repro- grammed, the other parameter block should be erased and reprogrammed before the first parameter block is erased again. Whenever the boot block is erased and repro- grammed, the main memory block and the parameter block should be erased and reprogrammed before the boot block is erased again. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logic “0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset hap- pens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t BP cycle time. The Data Polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti- vated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 03FFFH for the AT49BV008A; FC000H to FFFFFH for the AT49BV008AT; 00000H to 01FFFH for the AT49BV8192A; and 7E000H to 7FFFFH for the AT49BV8192AT. Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the soft- ware product identification mode (see Software Product Identification Entry and Exit sections) a read from the fol- lowing address location will show if programming the boot block is locked out – 00002H for the AT49BV008A and AT49BV8192A; FC002H for the AT49BV008AT; and 7E002H for the AT49BV8192AT. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts during the entire chip erase, sector erase or word programming operation. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The
AT49BV008A(T)/8192A(T) hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes ” on page 8 (for hard- ware operation) or “Software Product Identification Entry/Exit” on page 13. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV008A(T)/8192A(T) features Data Polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. TOGGLE BIT: In addition to Data Polling, the AT49BV008A(T)/8192A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. READY/BUSY : For the AT49BV008A(T), pin 12 is an open-drain Ready/Busy output pin that provides another method of detecting the end of a program or erase opera- tion. RDY/BUSY is actively pulled low during the internal program and erase cycles and it is released at the comple- tion of the cycle. The open-drain connection allows for OR- tying of several devices to the same RDY/BUSY line. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV008A(T)/8192A(T) in the following ways: (a) V CC sense: if V CC is below 1.8V (typical), the program function is inhibited. (b) VCC power on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE , CE and WE ) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V CC + 0.6V. AT49BV008A(T) ALTERNATE PIN DEFINITION: Two AT49BV008A(T) BGA pin definitions are shown. The stan- dard pin definition allows use of the JEDEC standard pro- gramming algorithm. If the alternate pin definition is used, the programming algorithm must be modified as shown in the Command Definition for Alternate Pin Definition table on page 7.
AT49BV008A(T)/8192A(T)6 Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don ’t Care); I/O7 - I/O0 (Hex) The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care) 2. The boot sector has the address range 00000H to 03FFFH for the AT49BV008A; FC000H to FFFFFH for the AT49BV008AT; 00000H to 01FFFH for the AT49BV8192A; and 7E000H to 7FFFFH for the AT49BV8192AT. 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses: (A0 - A18) For the AT49BV008A/8192A SA = 01XXX for BOOT BLOCK SA = 02XXX for P ARAMETER BLOCK 1 SA = 03XXX for P ARAMETER BLOCK 2 SA = 7FXXX for MAIN MEMORY ARRAY For the AT49BV008AT/8192AT SA = 7FXXX for BOOT BLOCK SA = 7DXXX for PARAMETER BLOCK 1 SA = 7CXXX for PARAMETER BLOCK 2 SA = 7BXXX for MAIN MEMORY ARRAY Command Definition in Hex(1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA (4) 30 Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D IN Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (3) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit(3) 1x x x x F 0 Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on RESET
AT49BV008A(T)/8192A(T) Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don ’t Care); I/O7 - I/O0 (Hex) The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care) 2. The boot sector has the address range 00000H to 03FFFH for the AT49BV008A; FC000H to FFFFFH for the AT49BV008AT. 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses: (A0 - A18) For the AT49BV008A SA = 02XXX for BOOT BLOCK SA = 04XXX for P ARAMETER BLOCK 1 SA = 06XXX for P ARAMETER BLOCK 2 SA = FEXXX for MAIN MEMORY ARRAY For the AT49BV008AT SA = FEXXX for BOOT BLOCK SA = FAXXX for PARAMETER BLOCK 1 SA = F8XXX for PARAMETER BLOCK 2 SA = F6XXX for MAIN MEMORY ARRAY Command Definition (in Hex) for Alternate Pin Definition of AT49BV008A(T)(1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 A555 AA 5AAA 55 A555 80 A555 AA 5AAA 55 A555 10 Sector Erase 6 A555 AA 5AAA 55 A555 80 A555 AA 5AAA 55 SA (4) 30 Byte/Word Program 4 A555 AA 5AAA 55 A555 A0 Addr D IN Boot Block Lockout(2) 6 A555 AA 5AAA 55 A555 80 A555 AA 5AAA 55 A555 40 Product ID Entry 3 A555 AA 5AAA 55 A555 90 Product ID Exit (3) 3 A555 AA 5AAA 55 A555 F0 Product ID Exit(3) 1x x x x F 0 Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on RESET
AT49BV008A(T)/8192A(T)8 Notes: 1. X can be V IL or VIH. 2. Refer to AC programming waveforms. 4. Manufacturer Code: 001FH Device Code: 22H (AT49BV008A); 00A0H (AT49BV8192A); 21H (AT49BV008AT); 00A3H (AT49BV8192AT) 5. See details under “Software Product Identification Entry/Exit” on page 13. Note: 1. In the erase mode, I CC is 50 mA. DC and AC Operating Range AT49BV008AT/LV8192A-90 AT49BV8192A-10 AT49BV8192A(T)-11 AT49BV008A(T)-12 Operating Temperature (Case) Com. 0 °C - 70°C Operating Modes Mode CE OE WE RESET VPP Ai I/O Read V IL VIL VIH VIH XA i D OUT Program/Erase(2) VIL VIH VIL VIH XA i D IN Standby/Program Inhibit VIH X(1) XV IH X X High-Z Program Inhibit X X V IH VIH X Program Inhibit X V IL XV IH X Output Disable X V IH XV IH X High-Z Reset X X X V IL X X High-Z Product Identification Hardware V IL VIL VIH VIH A1 - A18 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4) A1 - A18 = VIL, A9 = VH,(3) A0 = VIH Device Code(4) Software(5) VIH A0 = VIL, A1 - A18 = VIL Manufacturer Code(4) A0 = VIH, A1 - A18 = VIL Device Code(4) DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 10.0 µA ILO Output Leakage Current V I/O = 0V to VCC 10.0 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 50.0 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 0.5 mA ICC (1) VCC Active Current f = 5 MHz; I OUT = 0 mA 25.0 mA VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA 0.45 V VOH Output High Voltage I OH = -400 µA 2.4 V
AT49BV008A(T)/8192A(T) AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level tR, tF < 5 ns Output Test Load Note: 1. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbo l Parameter AT49BV008A(T)/8192A(T) Units - 9 0- 1 0- 1 1- 1 2 M i nM a xM i nM a xM i nM a xM i nM a x tACC Address to Output Delay 90 100 110 120 ns tCE (1) CE to Output Delay 90 100 110 120 ns tOE (2) OE t o O u t p u t D e l a y 4 5 4 505 005 0 n s tDF (3)(4) CE or OE to Output Float 30 30 0 30 0 30 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0000 n s tRO RESET to Output Delay 800 800 800 800 ns OE RESET CE tCE tOE tRO tACC tDF tOH ADDRESS HIGH ZOUTPUT OUTPUT ADDRESS VALID VALID Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V
AT49BV008A(T)/8192A(T)10 AC Byte/Word Load Waveforms WE Controlled CE Controlled AC Word Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time 10 ns tAH Address Hold Time 70 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)7 0 n s tDS Data Setup Time 70 ns tDH, tOEH Data, OE Hold Time 10 ns tWPH Write Pulse Width High 50 ns
AT49BV008A(T)/8192A(T) Program Cycle Waveforms Sector or Chip Erase Cycle Waveforms Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Byte/Word Programming Time 30 µs tAS Address Setup Time 0 ns tAH Address Hold Time 70 ns tDS Data Setup Time 70 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 70 ns tWPH Write Pulse Width High 50 ns tEC Erase Cycle Time 10 seconds OE INPUT DATA ADDRESS A055 5555 5555 AA 2AAA t BPt WPHt WP CE WE tAS tAH tDH tDS 5555 AA PROGRAM CYCLE A0-A18 DATA OE (1) AA8055 55 5555 5555 AA 2AAA 2AAA t WPHt WP CE WE t AS tAH t EC t DH t DS 5555A0-A18 DATA Note 2 Note 3 BYTE/ WORD 0 BYTE/ WORD 1 BYTE/ WORD 2 BYTE/ WORD 3 BYTE/ WORD 4 BYTE/ WORD 5
AT49BV008A(T)/8192A(T)12 Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns
AT49BV008A(T)/8192A(T) Software Product Identification Entry(1) Software Product Identification Exit(1)(6) Notes: 1. Data Format: I/O15 - I/O8 (Don ’t Care); I/O7 - I/O0 (Hex) Address Format: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care). 2. A1 - A18 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if pow- ered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH Device Code: 22H (AT49BV008A); 00A0H (AT49BV8192A); 21H (AT49BV008AT); 00A3H (AT49BV8192AT) 6. Either one of the Product ID Exit commands can be used. 7. If the alternate pin definition is used, 5555 should be replaced with A555, 2AAA should be replaced with 5AAA. Boot Block Lockout Enable Algorithm(1) Notes: 1. Data Format: I/O15 - I/O8 (Don ’t Care); I/O7 - I/O0 (Hex) Address Format: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care). 2. Boot Block Lockout feature enabled. 3. If the alternate pin definition is used, 5555 should be replaced with A555, 2AAA should be replaced with 5AAA. LOAD DATA AA TO ADDRESS 5555(7) LOAD DATA 55 TO ADDRESS 2AAA(7) LOAD DATA 90 TO ADDRESS 5555(7) ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 5555(7) LOAD DATA 55 TO ADDRESS 2AAA(7) LOAD DATA F0 TO ADDRESS 5555(7) EXIT PRODUCT IDENTIFICATION MODE(4) LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) OR PAUSE 1 second(2) LOAD DATA AA TO ADDRESS 5555(3) LOAD DATA 55 TO ADDRESS 2AAA(3) LOAD DATA 80 TO ADDRESS 5555(3) LOAD DATA AA TO ADDRESS 5555(3) LOAD DATA 55 TO ADDRESS 2AAA(3) LOAD DATA 40 TO ADDRESS 5555(3)
AT49BV008A(T)/8192A(T)14 AT49BV008A(T) Ordering Information tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 120 25 0.05 AT49BV008A-12TI 40T Industrial (-40° to 85°C) 90 25 0.05 AT49BV008AT -90CI 48C1 Industrial (-40° to 85°C) 120 25 0.05 AT49BV008AT -12CI 48C1 Industrial (-40° to 85°C) AT49BV8192A(T) Ordering Information tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 90 25 0.05 AT49LV8192A-90TC 48T Commercial (0° to 70°C) AT49BV8192AT-90CI 48C1 Industrial (-40° to 85°C) 100 25 0.05 AT49BV8192A-10CI 48C1 Industrial (-40° to 85°C) 110 25 0.05 AT49BV8192A-11CI 48C1 Industrial (-40° to 85°C) AT49BV8192A-11TI 48T Industrial (-40° to 85°C) 110 25 0.05 AT49BV8192AT -11CI 48C1 Industrial (-40° to 85°C) AT49BV8192AT-11TI 48T Industrial (-40° to 85°C) Package Type 48C1 48-ball, Chip-scale Ball Grid Array Package (CBGA) 40T 40-lead, Plastic Thin Small Outline Package (TSOP) 48T 48-lead, Plastic Thin Small Outline Package (TSOP)
AT49BV008A(T)/8192A(T) Packaging Information *Controlling dimension: millimeters A B C D E F 8 67 5432 1 3.75 (0.148) 1.75 (0.69) 1.48 (0.58) 0.30 (0.012) DIA BALL TYP 1.0 (0.040) 7.2 (0.283) 6.8 (0.268) 1.25 (0.049) MAX 0.25 (0.010) 7.2 (0.283) 6.8 (0.268) 0.75 (0.030) BSC NON-ACCUMULATIVE *Controlling dimension: millimeters *Controlling dimension: millimeters 48C1, 48-ball, Chip-scale Ball Grid Array Package (CBGA) Dimensions in Millimeters and (Inches)* 40T, 40-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* 48T, 48-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* JEDEC OUTLINE MO-142 D
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