Download PDFAT43312A ATMEL
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Technical content
Features
- Full Compliance with USB Spec Rev 1.1 Four Downstream Ports Full-speed and Low-speed Data Transfers Bus-powered Controller Bus-powered or Self-powered Hub Operation Per Port Overcurrent Monitoring Individual Port Power Control USB Connection Status Indicators 5V Operation with On-chip 3.3V Format 32-lead SOIC and LQFP Overview Introduction The AT43312A is a 5 port USB hub chip supporting one upstream and four down- stream ports. The AT43312A connects to an upstream hub or Host/Root Hub via Port0 and the other ports connect to external downstream USB devices. The hub re-trans- mits the USB differential signal between Port0 and Ports[1:4] in both directions. A USB hub with the AT43312A can operate as a bus-powered or self-powered through chip’s power mode configuration pin. In the self-powered mode, port power can be switched or unswitched. Overcurrent reporting and port power control can be individual or glo- bal. An on-chip power supply eliminates the need for an external 3.3V supply. The AT43312A supports the 12-Mb/sec full speed as well as 1.5-Mb/sec slow speed USB transactions. To reduce EMI, the AT43312A’s oscillator frequency is 6 MHz even though some internal circuitry operates at 48 MHz. The AT43312A consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller. Self- and Bus- powered USB Hub Controller AT43312A Rev. 1255F–USB–3/04 SOIC PWR2 PWR3 PWR4 VCC5 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 OVC1 LPSTAT SELF/BUS STAT4 PWR1 DP4 DM4 DP3 DM3 VSS DP2 DM2 CEXT DP1 DM1 DP0 DM0 STAT1 STAT2 STAT3 LQFP Top View DP3 DM4 DP4 PWR1 PWR2 PWR3 PWR4 VCC5 DMO STAT1 STAT2 STAT3 STAT4 SELF/BUS LPSTAT OVC1 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 DM3 VSS DP2 DM2 CEXT DP1 DM1 DP0
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Figure 1. Block Diagram Specification Version 1.1, September 23, 1998.
Table 1. 32-lead SOIC Assignment
4 VCC5 V
5 VSS V
9 TEST I
10 OVC4
11 OVC3 I
12 OVC2 I
13 OVC1 I
14 LPSTAT I
15 SELF/BUS I
16 STAT4 O
17 STAT3 O
18 STAT2 O
19 STAT1 O
20 DM0 B
21 DP0 B
22 DM1 B
23 DP1 B
24 CEXT O
25 DM2 B
26 DP2 B
27 VSS V
28 DM3 B
29 DP3 B
30 DM4 B
31 DP4 B
32 PWR1
4 AT43312A
Table 2. 32-lead LQFP Assignment
8 VCC5 V
9 VSS V
10 OSC1 I
11 OSC2 O
12 LFT I
13 TEST
14 OVC4 I
15 OVC3 I
16 OVC2 I
17 OVC1 I
18 LPSTAT I
19 SELF/BUS I
20 ST AT4 O
21 ST AT3 O
22 ST AT2 O
23 ST AT1 O
24 DMO B
25 DP0 B
26 DM1 B
27 DP1 B
28 CEXT O
29 DM2 B
30 DP2 B
31 VSS V
32 DM3 B
1255F–USB–3/04 Signal Description OSC1 Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. OSC2 Oscillator Output. Output of the inverting oscillator amplifier. LFT PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel with a 100Ω resistor in series with a 10 nF capacitor to ground (VSS). SELF/BUS Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high on this pin enables the self-powered mode, a low enables the bus-powered mode. LPSTAT Local Power Status. In the self-powered mode, this is an input pin that should be con- nected to the local power supply through a 47 kΩ resistor. The voltage on this pin is used by the chip for reporting the condition of the local power supply. In the bus-pow- ered mode, this pin is not used. DP0 Upstream Plus USB I/O. This pin should be connected to CEXT through an external 1.5 kΩ pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to the Host Controller or an upstream Hub. DM0 Upstream Minus USB I/O. DP[1:4] Port Plus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. DM[1:4] Port Minus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor OVC [1:4] Overcurrent. This is the input signal used to indicate to the AT43312A that an overcur- rent is detected at the port. If OVCx is asserted, AT43312A will assert the PWRx pin and report the status to the USB Host. PWR [1:4] Power Switch. This is an output signal used to enable or disable the external voltage regulator supplying power to a port. PWRx is de-asserted when a power supply problem is detected at OVCx. STAT [1:4] Connect Status. This is an output pin indicating that a port is properly connected. STATx is asserted when the port is enabled. CEXT External Capacitor. For proper operation of the on chip regulator, a 0.27 µF capacitor must be connected to this pin. TEST Test. This pin should be connected to a logic high for normal operation. VCC 5V Power Supply. VSS Ground.
6 AT43312A
1255F–USB–3/04 Functional
Description
Summary The Atmel AT43312A is a USB hub controller for use in a standalone hub as well as an add-on hub for an existing non-USB peripheral such a PC display monitor or keyboard. In addition to supporting the standard USB hub functionality, the AT43312A has addi- tional features to enhance the user friendliness of the hub. USB Ports The AT43312A’s upstream port, Port0, is a full-speed port. A 1.5 kΩ pull-up resistor to the 3.3V regulator output, CEXT, is required for proper operation. The downstream ports support both full-speed as well as low-speed devices. 15 k Ω pull-down resistors are required at their inputs. Full-speed signal requirements demand controlled rise/fall times and impedance match- ing of the USB ports. To meet these requirements, 22Ω resistors must be inserted in series between the USB data pins and the USB connectors. Hub Repeater The Hub Repeater is responsible for port connectivity setup and tear-down. It also sup- ports exception handling such as bus fault detection and recovery, and connect/disconnect detection. Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is received at Port0, the AT43312A propagates it to all the enabled downstream ports. Conversely, a packet from a downstream port is trans- mitted from Port0. The AT43312A supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices attached to the downstream ports are determined to be either full-speed or low- speed depending which data line (DP or DM) is pulled high. If a port is enumerated as low-speed, its output buffers operate at a slew rate of 75 - 300 ns, and the AT43312A will not propagate any traffic to that port unless it is prefaced with a preamble PID. Low- speed data following the preamble PID is propagated to both low- and full-speed devices. The AT43312A will enable low-speed drivers within four full-speed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP. Packets out of Port0 are always transmitted using the full-speed drivers. All the AT43312A ports independently drive and monitor their DP and DM pins so that they are able to detect and generate the “J”, “K”, and SE0 bus signaling states. Each hub port has single-ended and differential receivers on its DP and DM lines. The port I/O buffers comply with the voltage levels and drive requirements as specified in the USB Specifications Rev 1.0. The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets reset every time an SOF token is received from the Host. Serial Interface EngineThe Serial Interface Engine handles the USB communication protocol. It performs the USB clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC genera- tion and checking, USB packet ID decoding and generation, and data serialization and de-serialization. The on chip phase locked loop generates the high frequency clock for the clock/data separation circuit.
1255F–USB–3/04 Power Management A hub is a high-powered device and is allowed to draw up to 500 mA of current from the host or upstream hub. The AT43312A chip itself and its external hub circuitry consume much less than 100 mA. The AT43312A’s power management logic works with external devices to detect overcurrent and control power to the ports. Overcurrent sensing is on a per-port basis and is achieved through the OVCx pins. Whenever the voltage at OVCx is asserted, the AT43312A treats it as an overcurrent condition. This could be caused by an overload, or even a short circuit and could cause the AT43312A to set the port’s PORT_OVER_CURRENT status bit and its C_PORT_OVER_CURRENT status change bit. At the same time, power to the offend- ing port is shut off and its STATx generates a square wave with a frequency of about 1 second. An external device is needed to monitor the overcurrent condition and perform the actual switching of the ports’ power under control of the AT43312A. Any type of suitable switch or device is acceptable. However, it should have a low-voltage drop across it even when the port absorbs full-power. In its simplest form this switch can be a P-chan- nel MOSFET. One advantage of using a MOSFET switch is its very low-voltage drop and low-cost. Each one of the AT43312A’s port has its own power control pin which is asserted only when a SetPortFeature[PORT-POWER] request is received from the host. PWRx is de- asserted under the following conditions: 1. Power-up 2. Reset and initialization 3. Overcurrent condition 4. Requested by the host through a ClearPortFeature [PORT_POWER] for ALL the ports Self-powered Mode In the self-powered mode, power to the downstream ports must be supplied by an exter- nal power supply. This power supply must be capable of supplying 500 mA per port for a total of 2A. The USB specifications require that the voltage drop at the power switch and board traces be no more than 100 mV. A good conservative maximum drop at the power switch itself should be no more than 75 mV. Careful design and selection of the power switch and PC board layout is required to meet the specifications. When using a MOS- FET switch, its resistance must be 140 m Ω or less under worst case conditions. A suitable MOSFET switch for an AT43312A based hub is an integrated high side dual MOSFET switch such as the Micrel MIC2526.
8 AT43312A
Figure 2. Self-powered Hub Power Supply
Figure 3. Bus Powered Hub Power Supply port’s STATx. Any condition that causes the port to be disabled inactivates STATx. the external voltage exceed 5.5V. To do so will put the chip under excessive stress. the Host before the Hub Controller can apply power to external devices. tings. At power up, all bits in this register will be set to 0’s.
10 AT43312A
AT43312A. Endpoint 0 supports control transfers. Requests and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint descriptor for Endpoint0. Register, using a bitmap scheme. Table 3. Control Status Register
0 Hub configuration status 0
1 Hub remote wakeup status 0
2 Endpoint0 STALL status 0
3 Endpoint1 STALL status 0
Table 4. Status Change Register
0 Hub status change 0
1 Port1 status change 0
2 Port2 status change 0
3 Port3 status change 0
4 Port4 status change 0
configured by the Host via Endpoint 0. All the clock signals required to run the AT43311 are derived from an on-chip oscillator. turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used. because a resonator would not have the frequency accuracy and stability. the oscillator, a series resistor between OSC2 and the crystal pin is recommended. tain good noise margins at the low switching level. Figure 4. Oscillator and PLL Connections package pins are recommended.
6.000 MHz
12 AT43312A
1255F–USB–3/04 Power Supply The AT43312A is powered from the USB bus, but has an internal voltage regulator to supply the 3.3V operating power to its circuitry. For proper operation, an external high quality, low ESR, 0.27 µF or larger, capacitor should be connected to the output of the regulator, CEXT pin and ground. The CEXT pin can also be used to supply the voltage to the 1.5K pull-up resistor at Port 0’s DP pin. To provide the best operating condition for the AT43312A, careful consideration of the power supply connections are recommended. Use short, low impedance connections to both power supply lines: VCC and VSS. Use sufficient decoupling capacitance to reduce noise: 0.1 µF of high quality ceramic capacitor soldered as close as possible to the VCC and VSS package pins. Package pins are recommended. The AT43312A can also operate directly off a 3.3V power supply. In this case, leave the VCC pin floating and connect the 3.3V power to the CEXT pin.
may affect device reliability. Table 5. Power Supply Table 6. USB Signals: DPx, DMx
14 AT43312A
Note: OSC2 must not be used to drive other circuitry. Note: With external 22Ω series resistor. Figure 5. Data Signal Rise and Fall Time Table 7. PWR , STAT, OVC Table 8. Oscillator Signals: OSC1, OSC2 Table 9. DPx, DMx Driver Characteristics, Full-speed Operation
Note: 1. With 6.000 MHz, 100 ppm crystal. Figure 6. Full-speed Load Table 10. DPx, DMx Source Timings, Full-speed Operation Table 11. DPx, DMx Driver Characteristics, Low-speed Operation
16 AT43312A
Figure 7. Low-speed Downstream Port Load Table 12. DPx, DMx Hub Timings, Full-speed Operation Table 13. DPx, DMx Hub Timings, Low-speed Operation
18 AT43312A
Figure 11. Hub Differential Delay, Differential Jitter, and SOP Distortion Figure 12. Hub EOP Delay and EOP Skew
Table 14. Hub Event Timings
20 AT43312A
Figure 13. AT43312A Self-powered USB Hub
Figure 14. AT43312A Self-powered USB Hub
22 AT43312A
Figure 15. AT43312A Bus-powered USB Hub
Figure 16. AT43312A Bus-powered USB Hub
24 AT43312A
1255F–USB–3/04
Ordering Information
Ordering Code Package Operating Range AT43312A-AC AT43312A-SC 32AA 32R Commercial (0°C to 70°C) Package Type 32AA 32-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP) 32R 32-lead, 0.440" Wide, Plastic Gull Wing Small Outline (SOIC)
1255F–USB–3/04
Package Information
32AA – LQFP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 32AA, 32-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.8 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) B32AA 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A1 A2 A D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-026, Variation BBA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.60 A1 0.05 – 0.15 A2 1.35 1.40 1.45 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP
26 AT43312A
1255F–USB–3/04 32R – SOIC PIN 1 0º ~ 8º San Jose, CA 95131 TITLE DRAWING NO. R REV. 32R, 32-lead, 0.440" Body Width, Plastic Gull Wing Small Outline (SOIC) B32R 06/04/2002 A 2.29 – 2.54 A1 0.102 – 0.254 D 20.83 – 21.08 Note 1 E 14.05 – 14.40 E1 11.05 – 11.30 Note 1 B 0.356 – 0.508 C 0.1 – 0.22 L 0.53 – 1.04 e 1.27 TYP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A E C e D L B Note: 1. Dimensions D and E do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010").
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