AT34C02_07 ATMEL

Document overview

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  • PDF pages: 21

Technical content

Features

  • Permanent Software Write Protection for the First-half of the Array – Software Procedure to Verify Write Protect Status
  • Hardware Write Protection for the Entire Array
  • Low-voltage Operation – 1.8 (V CC = 1.8V to 5.5V)
  • Internally Organized 256 x 8
  • Two-wire Serial Interface
  • Schmitt Trigger, Filtered Inputs for Noise Suppression
  • Bidirectional Data Transfer Protocol
  • 100 kHz (1.8V) and 400 kHz (2.7V and 5.0V) Compatibility
  • 16-byte Page Write Modes
  • Partial Page Writes Are Allowed
  • Self-timed Write Cycle (5 ms max)
  • High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
  • Automotive Grade Devices Available
  • 8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP , and 8-ball dBGA2 Packages
  • Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers

Description

The AT34C02 provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a software write protection feature while hardware write pro- tection for the entire array is available via an external pin as well. Once the software write protection is enabled, by sending a special command to the device, it cannot be reversed. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the application. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT34C02 is available in space saving 8-lead PD IP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP and 8-ball dBGA2 packages and is accessed via a two-wire serial interface. In addition, it is available in 1.8V (1.8V to 5.5V) versions. Table 1. Pin Configurations

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Figure 1. Block Diagram

EEPROM device and negative edge clock data out of each device. to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. a pull-up resistor, Atmel recommends using 10kΩ or less. Note: 1. This parameter is characterized and is not 100% tested. Table 2. AT34C02 Write Protection Modes Table 3. Pin Capacitance(1)

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Note: 1. V IL min and VIH max are reference only and are not tested. Table 4. DC Characteristics VCC = +1.8V to +5.5V (unless otherwise noted).

Note: 1. This parameter is characterized and is not 100% tested. Table 5. AC Characteristics CL = 1 TTL Gate and 100 pF (unless otherwise noted).

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0958Q–SEEPR–1/07 Memory Organization AT34C02, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each. Random word addressing requires a 8-bit data word address. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter- nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 5 on page 8). Data c hanges during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place th e EEPROM in a standby power mode (see Figure 5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT34C02 features a low-power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA hi gh in each cycle while SCL is high and then (c) create a start condition.

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Figure 5. Start and Stop Condition Figure 6. Output Acknowledge

0958Q–SEEPR–1/07 Device Addressing The 2K EEPROM device requires an 8-bit dev ice address word following a start condi- tion to enable the chip for a read or write operation (see Figure 8 on page 12). The device address word consists of a m andatory one-zero sequ ence for the first four most-significant bits (1010) for normal re ad and write operations and 0110 for writing to the write protect register. The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02 EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the r ead/write operation select bit. A read opera- tion is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. The device will not acknowledge if the write protect register has been programmed and the control code is 0110. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then cloc k in the first 8-bit data word. Following receipt of the 8-bit data word, the EE PROM will output a zero and the addressing device, such as a microcontroller, must te rminate the write sequence with a stop condi- tion. At this time the EEPROM enter s an internally-tim ed write cycle, t WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 9 on page 12). The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. PAGE WRITE: The 2K device is capable of 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the fi rst data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 10 on page 13). The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send- ing a start condition followed by the dev ice address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.

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0958Q–SEEPR–1/07 Write Protection The software write protection, once enabled, permanently write protects only the first- half of the array (00H - 7FH) while the hardware write protection, via the WP pin, is used to protect the entire array. SOFTWARE WRITE PROTECTION: The software write protec tion is enabled by send- ing a command, similar to a normal write command, to the device which programs the write protect register. This must be done wit h the WP pin low. The write protect register is programmed by sending a write command with the device address of 0110 instead of 1010 with the address and data bit being don’t cares (see Figure 7 on page 11). Once the software write protection has been enabled, the device will no longer acknowledge the 0110 control byte. The software write protection cannot be reversed even if the device is powered down. The write cycle time must be observed. HARDWARE WRITE PROTECTION: The WP pin can be connected to V CC, GND, or left floating. Connecting the WP pin to V CC will write protect the en tire array, regardless of whether or not the software write pr otection has been enabled. The software write protection register cannot be programm ed when the WP pin is connected to V CC. If the WP pin is connected to GND or left floating , the write protection mode is determined by the status of the software write protect register.

Figure 7. Setting Write Protect Register operations: current address read, random address read and sequential read. acknowledged by the EEPROM, the current addr ess data word is serially clocked out. generate a following stop condition (see Figure 11 on page 13).

1010 R X ACK Read Array

1010 W Programmed ACK Can Write to Second Half (80H - FFH) Only

1010 W Not Programmed ACK Can Write to Full Array

0110 R Programmed No ACK Stop - Indicates Write Protect Register is Programmed

0110 W Programmed No ACK Stop - Indicates Write Protect Register is Programmed

0110 W Not Programmed ACK Program Writ e Protect Register (irreversible)

1010 W Programmed ACK Device Write Protect

1010 W Not Programmed ACK Device Write Protect

0110 W Not Programmed ACK Cannot Program Write Protect Register

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tion (see Figure 13 on page 13). protected at the first half of the array. Figure 8. Device Address Figure 9. Byte Write

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0958Q–SEEPR–1/07 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics Tables. 2. “U” and “Q” designate Green package + RoHS compliant. 3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Information(1) Ordering Code Package Operation Range AT34C02-10PU-1.8(2) AT34C02N-10SU-1.8(2) AT34C02-10TU-1.8(2) AT34C02Y1-10YU-1.8(2) AT34C02U3-10UU-1.8(2) 8P3 8S1 8A2 8Y1 8U3-1 Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT34C02N-10SE-2.7 AT34C02-10TE-2.7 8S1 8A2 Automotive (–40°C to 125°C) AT34C02N-10SQ-2.7 (2) AT34C02-10TQ-2.7(2) 8S1 8A2 Lead-free/Halogen-free/Automotive (–40°C to 125°C) AT34C02-W1.8-11(3) Die Sale Industrial Temperature (–40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8U3-1 8-ball, die Ball Grid Array Package (dBGA2) Options –1.8 Low Voltage (1.8V to 5.5V)

0958Q–SEEPR–1/07 Packaging Information 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D E e Lb2 b A2 A N eA c

4 PLCS

(Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2

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0958Q–SEEPR–1/07 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

0958Q–SEEPR–1/07 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

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0958Q–SEEPR–1/07 8Y1 – MAP A – – 0.90 A1 0.00 – 0.05 D 4.70 4.90 5.10 E 2.80 3.00 3.20 D1 0.85 1.00 1.15 E1 0.85 1.00 1.15 b 0.25 0.30 0.35 e 0.65 TYP L 0.50 0.60 0.70 PIN 1 INDEX AREA D E A A1 b 8 7 6 e L PIN 1 INDEX AREA 1 2 34 A Top View End View Bottom View Side View San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 C8Y1 2/28/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

0958Q–SEEPR–1/07 8U3-1 – dBGA2 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. PO8U3-1 A 6/24/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) A 0.71 0.81 0.91 A1 0.10 0.15 0.20 A2 0.40 0.45 0.50 b 0.20 0.25 0.30 D 1.50 BSC E 2.00 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF 1. Dimension “b” is measured at the maximum solder ball diameter. This drawing is for general information only. Bottom View

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E Top View PIN 1 BALL PAD CORNER A Side View PIN 1 BALL PAD CORNER e 678 d (e1) (d1)

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0958Q–SEEPR–1/07

Revision History

Doc. Rev. Date Comments 0958Q 1/2007 Revision history implemented. Added Note to Page 1: Not recommended for new design; please refer to AT34CO2C datasheet.

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