Download PDFAT29C512 ATMEL
Document overview
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Technical content
Features
- Fast Read Access Time – 70 ns 5-volt Only Reprogramming Sector Program Operation – Single Cycle Reprogram (Erase and Program) – 512 Sectors (128 Bytes/Sector) – Internal Address and Data Latches for 128 Bytes Internal Program Control and Timer Hardware and Software Data Protection Fast Sector Program Cycle Time – 10 ms DATA Polling for End of Program Detection Low Power Dissipation – 50 mA Active Current – 100 µA CMOS Standby Current Typical Endurance > 10,000 Cycles Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs Commercial and Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option 1. Description The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man- ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the commercial tem- perature range. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. To allow for simple in-system reprogrammability, the AT29C512 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are loaded into the device and then simultaneously programmed. During a reprogram cycle, the address locati ons and 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin. 512K (64K x 8) 5-volt Only Flash Memory AT29C512 0456H–FLASH–2/05
0456H–FLASH–2/05 AT29C512 2. Pin Configurations 2.1 32-lead PLCC Top View 2.2 32-lead TSOP (Type 1) Top View Pin Name Function A0 - A15 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect I/O0 A14 A13 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A12 A15 NC NC VCC WE NC A11 A13 A14 NC WE VCC NC NC A15 A12 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0
0456H–FLASH–2/05 AT29C512 3. Block Diagram 4. Device Operation
4.1 Read
The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
4.2 Byte Load
Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.
4.3 Program
The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same man- ner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transi- tion is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high-to-low transition of WE (or CE ). A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of t WC, a read operation will effectively be a polling operation.
0456H–FLASH–2/05 AT29C512
4.4 Software Data Protection
A software controlled data protection feature is available on the AT29C512. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program com- mands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. Once set, the software data pro- tection feature remains active unless its dis able command is issued. Power transitions will not reset the software data protection feature; however, the software feature will guard against inad- vertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t WC, a read operation will effectively be a polling operation. After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.
4.5 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29C512 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical), the program function is inhibited; (b) VCC power on delay – once V CC has reached the V CC sense level, the device will automatically time out 5 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
4.6 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e., using the device code), and have the system software use the appropriate sector size for pro- gram operations. In this manner, the user can have a common board design for 256K to 4- megabit densities and, with each density’s sector size in a memory map, have the system soft- ware apply the appropriate sector size. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
0456H–FLASH–2/05 AT29C512
4.7 DATA Polling
The AT29C512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
4.8 Toggle Bit
In addition to DATA polling the AT29C512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
4.9 Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details. 5. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE
0456H–FLASH–2/05 AT29C512 Notes: 1. X can be V IL or VIH. 2. Refer to AC Programming Waveforms. 4. Manufacturer Code: 1F , Device Code: 5D. 5. See details under Software Product Identification Entry/Exit. 6. DC and AC Operating Range AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15 Operating Temperature (Case) VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10% Note: Not recommended for New Designs. 7. Operating Modes Mode CE OE WE Ai I/O Read V IL VIL VIH Ai D OUT Program(2) VIL VIH VIL Ai D IN 5V Chip Erase V IL VIH VIL Ai Standby/Write Inhibit V IH X(1) X X High Z Program Inhibit X X V IH Program Inhibit X V IL X Output Disable X V IH X High Z Product Identification Hardware V IL VIL VIH A1 - A15 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4) A1-A15 = VIL, A9 = VH,(3) A0 = VIH Device Code(4) Software(5) A0 = VIL Manufacturer Code(4) A0 = VIH Device Code(4) 8. DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA Ind. 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3m A ICC VCC Active Current f = 5 MHz; I OUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA 0.45 V VOH1 Output High Voltage I OH = -400 µA 2.4 V VOH2 Output High Voltage CMOS I OH = -100 µA; VCC = 4.5V 4.2 V
0456H–FLASH–2/05 AT29C512 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 9. AC Read Characteristics Symbol Parameter AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15 UnitsMin Max Min Max Min Max Min Max tACC Address to Output Delay 70 90 120 150 ns tCE (1) CE to Output Delay 70 90 120 150 ns tOE (2) OE to Output Delay 0 35 0 40 0 50 0 70 ns tDF (3)(4) CE or OE to Output Float 0 10 0 25 0 30 0 40 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 0 ns Note: Not recommended for New Designs.
0456H–FLASH–2/05 AT29C512 11. Input Test Waveforms and Measurement Level 12. Output Test Load Note: 1. This parameter is characterized and is not 100% tested. tR, tF < 5 ns OUTPUT PIN 5.0V 30pF 1.8K 1.3K OUTPUT PIN 5.0V 100pF 1.8K 1.3K 70 ns 90/120/150 ns 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V
0456H–FLASH–2/05 AT29C512 15. AC Byte Load Waveforms
15.1 WE Controlled
15.2 CE Controlled
- AC Byte Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)9 0 n s tDS Data Set-up Time 35 ns tDH, tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 100 ns tDHtDS tAS tAH tWP CE ADDRESS DATA IN OE tOES tOEH WE tCS tCH tWPH tDHtDS tAS tAH tWP WE ADDRESS DATA IN OE tOES tOEH CE tCS tCH tWPH
0456H–FLASH–2/05 AT29C512 17. Program Cycle Waveforms(1)(2)(3) Notes: 1. A7 through A15 must specify the sector address during each high-to-low transition of WE (or CE). 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the sector being programmed will be indeterminate. 16. Program Cycle Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 35 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 90 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 100 ns
0456H–FLASH–2/05 AT29C512 18. Software Data Protection Enable Algorithm(1) Notes: 1. Data Format: I/O7 - I/O0 (Hex);Address Format: A14 - A0 (Hex). 2. Data Protect state will be activated at end of program cycle. 3. Data Protect state will be deactivated at end of pro- gram period. 4. 128 bytes of data MUST BE loaded. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA TO PAGE (128 BYTES)(4) WRITES ENABLED ENTER DATA PROTECT STATE(2) 19. Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA TO PAGE (128 BYTES)(4) EXIT DATA PROTECT STATE (3) 20. Software Protected Program Cycle Waveform(1)(2)(3) Notes: 1. A7 through A15 must specify the page address during each high-to-low transition of WE (or CE) after the software code has been entered. 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the sector being programmed will be indeterminate. OE (1) CE WE DATA (3) BYTE 0 BYTE 126 BYTE 127 tDH tBLC tDS tWP tWPH tAH A0-A6 A7-A15 (2) tWC 5555 2AAA 5555 AA 55 A0 tAS SECTOR ADDRESS BYTE ADDRESS
0456H–FLASH–2/05 AT29C512 Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics. 22. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics. 24. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 21. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns 23. Toggle Bit Characteristics (1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns WE CE OE I/O6 (2) tOEH HIGH ZtDH tOE tWR
0456H–FLASH–2/05 AT29C512 25. Software Product Identification Entry (1) 26. Software Product Identification Exit (1) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A15 = V IL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code is 1F . The Device Code is 5D. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 PAUSE 10 mS ENTER PRODUCT IDENTIFICATION MODE (2)(3)(5) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 PAUSE 10 mS EXIT PRODUCT IDENTIFICATION MODE (4)
0456H–FLASH–2/05 AT29C512 27. Normalized I CC Graphs NORMALIZED SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE (C) -55 1.4 1.3 1.2 1.1 1.0 0.8 0.9 -25 5 35 65 95 125 N O R M A L I Z E D I C C NORMALIZED SUPPLY CURRENT vs. ADDRESS FREQUENCY FREQUENCY (MHz) 1.1 1.0 0.9 0.8 0.7 1234567 N O R M A L I Z E D I C C V CC = 5V T = 25C NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) 4.50 1.4 1.2 1.0 0.8 0.6 4.75 5.00 5.25 5.50 N O R M A L I Z E D I C C
0456H–FLASH–2/05 AT29C512 28. Ordering Information
28.1 Standard Package
(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 50 0.1 AT29C512-70JC AT29C512-70TC 32J 32T Commercial (0° to 70°C) 50 0.3 AT29C512-70JI AT29C512-70TI 32J 32T Industrial (-40° to 85°C) 50 0.1 AT29C512-90JC AT29C512-90TC 32J 32T Commercial (0° to 70°C) 50 0.3 AT29C512-90JI AT29C512-90TI 32J 32T Industrial (-40° to 85°C) 120 50 0.1 AT29C512-12JC AT29C512-12TC 32J 32T Commercial (0° to 70°C) 50 0.3 AT29C512-12JI AT29C512-12TI 32J 32T Industrial (-40° to 85°C) 150 50 0.1 AT29C512-15JC AT29C512-15TC 32J 32T Commercial (0° to 70°C) 50 0.3 AT29C512-15JI AT29C512-15TI 32J 32T Industrial (-40° to 85°C) Note: Not recommended for New Designs.
28.2 Green Package Option (Pb/Halide-free)
(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 70 50 03 AT29C512-70JU AT29C512-70TU 32J 32T Industrial (-40° to 85°C) 90 50 0.3 AT29C512-90JU AT29C512-90TU 32J 32T Industrial (-40° to 85°C) Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32T 32-lead, Thin Small Outline Package (TSOP)
0456H–FLASH–2/05 AT29C512 29. Packaging Information 29.1 32J – PLCC DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131R TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B32J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 Note 2 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 Note 2 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP
0456H–FLASH–2/05 AT29C512 29.2 32T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) B32T 10/18/01 PIN 1 D1 D Pin 1 Identifier be E A 0º ~ 8º c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC
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