AT29C256 ATMEL

Document overview

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Technical content

Features

  • Fast Read Access Time – 70 ns  5-volt Only Reprogramming  Page Program Operation – Single Cycle Reprogram (Erase and Program) – Internal Address and Data Latches for 64 Bytes  Internal Program Control and Timer  Hardware and Software Data Protection  Fast Program Cycle Times – Page (64 Byte) Program Time – 10 ms – Chip Erase Time – 10 ms  DATA Polling for End of Program Detection  Low-power Dissipation – 50 mA Active Current –3 0 0 µA CMOS Standby Current  Typical Endurance > 10,000 Cycles  Single 5V ± 10% Supply  CMOS and TTL Compatible Inputs and Outputs  Commercial and Industrial Temperature Ranges

Description

The AT29C256 is a five-volt-only in-system Flash programmable and erasable read only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 300 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. 256K (32K x 8) 5-volt Only Flash Memory AT29C256 Rev. 0046P–FLASH–10/04 PLCC and LCC Top View Note: PLCC package pins 1 and 17 are DON’T CONNECT. Pin Configurations Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect NC I/O0 A11 NC OE A10 CE I/O7 I/O6 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 A12 WE DC VCC A14 A13 TSOP Top View Type 1 OE A11 A13 A14 VCC WE A12 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0

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0046P–FLASH–10/04 To allow for simple in-system reprogra mmability, the AT29C256 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from a static RAM. Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are loaded into the device and then simultaneously programmed. The contents of the entire device may be erased by using a six-byte software code (although erasure before pro- gramming is not needed). During a reprogram cycle, the address locations and 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automat ically erase the page and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected a new access for a read, program or chip erase can begin. Block Diagram Device Operation READ: The AT29C256 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. BYTE LOAD: A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the software codes for data protection and chip erasure.

0046P–FLASH–10/04 PROGRAM: The device is reprogrammed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be indeterminate. Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be pro- grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to- high transition of WE (or CE ) of the preceding byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A6 to A14 specify the page address. The page address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify the byte address within the page. The by tes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of t WC, a read operation will effectively be a polling operation. SOFTWARE DATA PROTECTION: A software controlled data protection feature is available on the AT29C256. Once the software protection is enabled a software algo- rithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabl ed by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to spec ific addresses with specific data must be performed. After the software data protection is enabled the same three program com- mands must begin each program cycle in order for the programs to occur. All software program commands must obey the page program timing specifications. Once set, the software data protection feature remains ac tive unless its disable command is issued. Power transitions will not reset the software data protection feature, however the soft- ware feature will guard against inadvertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the three-byte command sequence will start the internal write timers . No data will be written to the device; how- ever, for the duration of t WC, a read operation will effectively be a polling operation. After the software data protection’s three-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respec- tively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT29C256 in the following ways: (a) V CC sense – if V CC is below 3.8V (typical), the program function is inhibited; (b) V CC power on delay – once V CC has reached the VCC sense level, the device will automatically time out 5 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.

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0046P–FLASH–10/04 PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer and may be accessed by a hardware operation. For details, see Operating Modes or Product Identification. DATA POLLING: The AT29C256 features DATA polling to indicate the end of a pro- gram cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been com- pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT29C256 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a six-byte software code. Please see Software Chip Erase application note for details. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE

0046P–FLASH–10/04 Notes: 1. X can be V IL or VIH. 2. Refer to AC Programming Waveforms. 3. V H = 12.0V ± 0.5V. 4. Manufacturer Code: 1F , Device Code: DC. 5. See details under Software Product Identification Entry/Exit. DC and AC Operating Range AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15 Operating Temperature (Case) VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V± 10% Note: Not recommended for New Designs. Operating Modes Mode CE OE WE Ai I/O Read V IL VIL VIH Ai D OUT Program(2) VIL VIH VIL Ai D IN 5V Chip Erase V IL VIH VIL Ai Standby/Write Inhibit V IH X(1) X X High Z Write Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH X High Z High Voltage Chip Erase V IL VH (3) VIL X High Z Product Identification Hardware VIL VIL VIH A1-A14 = VIL, A9 = VH, A0 = VIL Manufacturer Code(4) A1-A14 = VIL, A9 = VH, A0 = VIH Device Code(4) Software(5) A0 = VIL Manufacturer Code(4) A0 = VIH Device Code(4) DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3m A ICC VCC Active Current f = 5 MHz; I OUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA 0.45 V VOH1 Output High Voltage I OH = -400 µA 2.4 V VOH2 Output High Voltage CMOS I OH = -100 µA; VCC = 4.5V 4.2 V

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0046P–FLASH–10/04 AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15 UnitsMin Max Min Max Min Max Min Max tACC Address to Output Delay 70 90 120 150 ns tCE (1) CE to Output Delay 70 90 120 150 ns tOE (2) OE to Output Delay 0 40 0 40 0 50 0 70 ns tDF (3)(4) CE or OE t o O u t p u t F l o a t 02 502 503 0 0 40 ns tOH Output Hold from OE, CE or Address, whichever occurred first 000 0 ns Note: Not recommended for New Designs.

0046P–FLASH–10/04 Input Test Waveforms and Measurement Level Output Test Load Note: 1. This parameter is characterized and is not 100% tested. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V tR, tF < 5 ns

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0046P–FLASH–10/04 AC Byte Load Waveforms WE Controlled CE Controlled AC Byte Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)9 0 n s tDS Data Set-up Time 35 ns tDH,tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 100 ns

0046P–FLASH–10/04 Program Cycle Waveforms(1)(2)(3) Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE). 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the page being programmed will be indeterminate. Program Cycle Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 35 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 90 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 100 ns

10 AT29C256

0046P–FLASH–10/04 Software Data Protection Enable Algorithm(1) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data Protect state will be re-activated at end of pro- gram cycle. 3. Data Protect state will be deactivated at end of pro- gram period. 4. 64 bytes of data MUST BE loaded. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA TO PAGE (64 BYTES)(4) WRITES ENABLED(2) ENTER DATA PROTECT STATE Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA TO PAGE (64 BYTES)(4) EXIT DATA PROTECT STATE (3) Software Protected Program Cycle Waveform(1)(2)(3) Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE) after the software code has been entered. 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the page being programmed will be indeterminate.

0046P–FLASH–10/04 Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 0 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 0 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns

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0046P–FLASH–10/04 Software Product Identification Entry(1) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A14 = V IL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code is 1F . The Device Code is DC. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 PAUSE 10 mS ENTER PRODUCT IDENTIFICATION MODE (2)(3)(5) Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 PAUSE 10 mS EXIT PRODUCT IDENTIFICATION MODE (4)

0046P–FLASH–10/04 NORMALIZED SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE (C) -55 1.4 1.3 1.2 1.1 1.0 0.8 0.9 -25 5 35 65 95 125 N O R M A L I Z E D I C C NORMALIZED SUPPLY CURRENT vs. ADDRESS FREQUENCY FREQUENCY (MHz) 1.1 1.0 0.9 0.8 0.7 1234567 N O R M A L I Z E D I C C V CC = 5V T = 25C NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) 4.50 1.4 1.2 1.0 0.8 0.6 4.75 5.00 5.25 5.50 N O R M A L I Z E D I C C

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0046P–FLASH–10/04

Ordering Information

(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 70 50 0.3 AT29C256-70JC AT29C256-70TC 32J 28T Commercial (0° to 70°C) AT29C256-70JI AT29C256-70TI 32J 28T Industrial (-40° to 85°C) 90 50 0.3 AT29C256-90JC AT29C256-90TC 32J 28T Commercial (0° to 70°C) AT29C256-90JI AT29C256-90TI 32J 28T Industrial (-40° to 85°C) 120 50 0.3 AT29C256-12JC AT29C256-12TC 32J 28T Commercial (0° to 70°C) AT29C256-12JI AT29C256-12TI 32J 28T Industrial (-40° to 85°C) 150 50 0.3 AT29C256-15JC AT29C256-15TC 32J 28T Commercial (0° to 70°C) AT29C256-15JI AT29C256-15TI 32J 28T Industrial (-40° to 85°C) Note: Not recommended for New Designs. Package Type 32J 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP)

0046P–FLASH–10/04 Packaging Information 32J – PLCC DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131R TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B32J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 Note 2 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 Note 2 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP

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0046P–FLASH–10/04 28T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) C28T 12/06/02 PIN 1 0º ~ 5º D1 D Pin 1 Identifier Area be E A c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC

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