AT28HC256 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 12

Technical content

Features

  • Fast Read Access Time - 70 ns
  • Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer
  • Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum 1 to 64-Byte Page Write Operation
  • Low Power Dissipation 80 mA Active Current 3 mA Standby Current
  • Hardware and Software Data Protection
  • DATA Polling for End of Write Detection
  • High Reliability CMOS Technology Endurance: 104 or 105 Cycles Data Retention: 10 Years
  • Single 5V ± 10% Supply
  • CMOS and TTL Compatible Inputs and Outputs
  • JEDEC Approved Byte-Wide Pinout
  • Full Military, Commercial, and Industrial Temperature Ranges

Description

The AT28HC256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. (continued) Note: PLCC package pins 1 and 17 are DON’T CONNECT. CERDIP, PDIP, FLATPACK Top View LCC, PLCC Top View Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect Pin Configurations TSOP Top View PGA Top View 0007F AT28HC256 2-279

The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external compo- nents. The device contains a 64-byte page register to al- low writing of up to 64-bytes simultaneously. During a write cycle, the address and 1 to 64-bytes of data are in- ternally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inad- vertent writes. The device also includes an extra 64-bytes of E 2PROM for device identification or tracking. Description (Continued) All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE and A9 *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* 2-280 AT28HC256

READ: The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cy- cle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a poll- ing operation. PAGE WRITE: The page write operation of the AT28HC256 allows 1 to 64-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be writ- ten within 150 µs (t BLC ) of the previous byte. If the tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to D AT A Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, succes- sive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. (continued) DATA PROTECTION: If precautions are not taken, inad- vertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel has incorporated both hardware and software fea- tures that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28HC256 in the follow- ing ways: (a) V CC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typi- cal) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28HC256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after t WC the entire AT28HC256 will be pro- tected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256. This is done by pre- ceding the data to be written by the same 3-byte command sequence. Once set, SDP will remain active unless the disable com- mand sequence is issued. Power transitions do not dis- able SDP and SDP will protect the AT28HC256 during power-up and power-down conditions. All command se- quences must conform to the page write timing specifica- tions. It should also be noted that the data in the enable and disable command sequences is not written to the de- vice and the memory addresses used in the sequence may be written with data in either a byte or page write op- eration. After setting SDP, any attempt to write to the device with- out the three byte command sequence will start the inter- nal write timers. No data will be written to the device; how- ever, for the duration of t WC , read operations will effec- tively be polling operations. AT28HC256 2-281

Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC + 1V 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current TTL CE = 2.0V to VCC + 1V AT28HC256-90, -12 3 mA AT28HC256-70 60 mA ISB2 VCC Standby Current CMOS CE = -3.0V to VCC + 1V AT28HC256-90, -12 300 µA ICC VCC Active Current f = 5 MHz; I OUT = 0 mA 80 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 6.0 mA .45 V VOH Output High Voltage I OH = -4 mA 2.4 V DC Characteristics AT28HC256-70 AT28HC256-90 AT28HC256-12 Operating Temperature (Case) VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% DC and AC Operating Range Mode CE OE WE I/O Read V IL VIL VIH D OUT Write (2) VIL VIH VIL D IN Standby/Write Inhibit V IH X (1) X High Z Write Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH X High Z Chip Erase V IL VH (3) VIL High Z 2. Refer to AC Programming Waveforms. Operating Modes DEVICE IDENTIFICATION: An extra 64-bytes of E2PROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using ad- dress locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regu- lar memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Soft- ware Chip Erase application note for details. Device Operation (Continued) 2-282 AT28HC256

AT28HC256-70 AT28C256-90 AT28HC256-12 Symbol Parameter Min Max Min Max Min Max Units tACC Address to Output Delay 70 90 120 ns tCE (1) CE to Output Delay 70 90 120 ns tOE (2) OE to Output Delay 0 35 0 40 0 50 ns tDF (3, 4) CE or OE to Output Float 0 35 0 40 0 50 ns tOH Output Hold from OE, CE or Address, whichever occurred first 000 n s AC Read Characteristics Notes: 1.CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2.OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AC Read Waveforms (1, 2, 3, 4) tR , tF < 5 ns Input Test Waveforms and Measurement Level Output Test Load Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V Pin Capacitance (f = 1 MHz, T = 25°C) (1) Note: 1. This parameter is characterized and is not 100% tested. AT28HC256 2-283

Note: 1. NR = No Restriction Symbol Parameter Min Max Units tAS , tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 100 ns tDS Data Set-up Time 50 ns tDH , tOEH Data, OE Hold Time 0 ns tDV Time to Data Valid NR (1) AC Write Characteristics AC Write Waveforms WE Controlled CE Controlled 2-284 AT28HC256

Symbol Parameter Min Typ Max Units tWC Write Cycle Time AT28HC256 5 10 ms AT28HC256F 2 3.0 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 50 ns Page Mode Write Characteristics Chip Erase Waveforms tS = tH = 5 µsec (min.) tW = 10 msec (min.) VH = 12.0V ± 0.5V Page Mode Write Waveforms (1, 2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. AT28HC256 2-285

Software Protected Write Cycle Waveforms (1, 2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. LOAD LAST BYTE TO LAST ADDRESS LOAD DATA A0 TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AA TO ADDRESS 5555 Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64-bytes of data are loaded. ENTER DATA PROTECT STATE WRITES ENABLED (2) Software Data Protection Enable Algorithm (1) LOAD DATA XX TO ANY ADDRESS (4) LOAD LAST BYTE TO LAST ADDRESS LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AA TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AA TO ADDRESS 5555 LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE (3) Software Data Protection Disable Algorithm (1) LOAD DATA XX TO ANY ADDRESS (4) 2-286 AT28HC256

Notes: 1. These parameters are characterized and not 100% tested. Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay (2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. Toggle Bit Characteristics (1) 2. See AC Read Characteristics. Symbol Parameter Min Typ Max Units tDH Data Hold Time 0 ns tOEH OE Hold Time 0 ns tOE OE to Output Delay (2) ns tWR Write Recovery Time 0 ns Data Polling Characteristics (1) 2. See AC Read Characteristics. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary 3. Any address location may be used but the address should not vary. Data Polling Waveforms AT28HC256 2-287

Note: 1. See Valid Part Number table below. Ordering Information (1) tACC (ns) ICC (mA) Ordering Code Package Operation Range Active Standby 70 80 60 AT28HC256(E,F)-70JC 32J Commercial AT28HC256(E,F)-70PC 28P6 (0 °C to 70°C) 80 0.3 AT28HC256(E,F)-70JI 32J Industrial AT28HC256(E,F)-70PI 28P6 (-40 °C to 85°C) 90 80 0.3 AT28HC256(E,F)-90JC 32J Commercial AT28HC256(E,F)-90PC 28P6 (0 °C to 70°C) 80 0.3 AT28HC256(E,F)-90JI 32J Industrial AT28HC256(E,F)-90PI 28P6 (-40 °C to 85°C) 80 0.3 AT28HC256(E,F)-90DM/883 28D6 Military/883C AT28HC256(E,F)-90FM/883 28F Class B, Fully Compliant AT28HC256(E,F)-90LM/883 32L (-55 °C to 125°C) AT28HC256(E,F)-90UM/883 28U 120 80 0.3 AT28HC256(E,F)-12JC 32J Commercial AT28HC256(E,F)-12PC 28P6 (0 °C to 70°C) AT28HC256(E,F)-12SC 28S AT28HC256(E,F)-12TC 28T 80 0.3 AT28HC256(E,F)-12JI 32J Industrial AT28HC256(E,F)-12PI 28P6 (-40 °C to 85°C) AT28HC256(E,F)-12SI 28S AT28HC256(E,F)-12TI 28T 80 0.3 AT28HC256(E,F)-12DM/883 28D6 Military/883C AT28HC256(E,F)-12FM/883 28F Class B, Fully Compliant AT28HC256(E,F)-12LM/883 32L (-55 °C to 125°C) AT28HC256(E,F)-12UM/883 28U 90 80 0.3 5962-88634 03 UX 28U Military/883C 5962-88634 03 XX 28D6 Class B, Fully Compliant 5962-88634 03 YX 32L (-55 °C to 125°C) 5962-88634 03 ZX 28F 80 0.3 5962-88634 04 UX 28U Military/883C 5962-88634 04 XX 28D6 Class B, Fully Compliant 5962-88634 04 YX 32L (-55 °C to 125°C) 5962-88634 04 ZX 28F 120 80 0.3 5962-88634 01 UX 28U Military/883C 5962-88634 01 XX 28D6 Class B, Fully Compliant 5962-88634 01 YX 32L (-55 °C to 125°C) 5962-88634 01 ZX 28F 80 0.3 5962-88634 02 UX 28U Military/883C 5962-88634 02 XX 28D6 Class B, Fully Compliant 5962-88634 02 YX 32L (-55 °C to 125°C) 5962-88634 02 ZX 28F AT28HC256 2-289

28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28 Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Plastic Thin Small Outline Package (TSOP) 28U 28 Pin, Ceramic Pin Grid Array (PGA) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28HC256 70 JC, JI, PC, PI AT28HC256 90 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256E 90 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256F 90 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256 12 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256E 12 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256F 12 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 Ordering Information Note Previous data sheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required. 2-290 AT28HC256