AT28C16-T ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 8

Technical content

Features

  • Ideal Rewriteable Attribute Memory
  • Simple Write Operation Self-Timed Byte Writes On-chip Address and Data Latch for SRAM-like Write Operation Fast Write Cycle Time - 1 ms 5-Volt-Only Nonvolatile Writes
  • End of Write Detection RDY/ BUSY Output DATA Polling
  • High Reliability Endurance: 100,000 Write Cycles Data Retention: 10 Years Minimum
  • Single 5-Volt Supply for Read and Write
  • Very Low Power 30 mA Active Current 100 µA Standby Current

Description

The AT28C16-T is the ideal nonvolatile attribute memory: it is a low power, 5-volt-only byte writeable nonvolatile memory (E2PROM). Standby current is typically less than 100 µΑ . The AT28C16-T is written like a Static RAM, eliminating complex program- ming algorithms. The fast write cycle times of 1 ms, allow quick card reconfiguration in-system. Data retention is specified as 10 years minimum, precluding the necessity for batteries. Three access times have been specified to allow for varying layers of buffering between the memory and the PCMCIA interface. The AT28C16-T is accessed like a Static RAM for read and write operations. During a byte write, the address and data are latched internally. Following the initiation of a write cycle, the device will go to a busy state and automatically write the latched data using an internal control timer. The device provides two methods for detecting the end of a write cycle; the RDY/ BUSY output and DATA POLLING of I/O7. 0285C AT28C16-T 2-175

(including NC Pins) All Output Voltages CC + 0.6V Voltage on OE and A9 *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* 2-176 AT28C16-T

READ: The AT28C16-T is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location detemined by the address pins is asserted on the outputs. The outputs are put in a high im- pedance state whenever CE or OE is high. This dual-line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the AT28C16-T is similar to writing into a Static RAM. A low pulse on WE or CE input with OE high and CE or WE low (respectively) initiates a byte write. The address is latched on the falling edge of WE or CE (whichever occurs last) and the data is latched on the rising edge of WE or CE (whichever occurs first). Once a byte write is started it will automatically time itself to completion. For the AT28C16-T the write cycle time is 1 ms maximum. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation. READY/ BUSY: Pin 1 is an open drain READY/BUSY out- put that indicates the current status of the self-timed inter- nal write cycle. READY/ BUSY is actively pulled low during the write cycle and is released at the completion of the write. The open drain output allows OR-tying of several devices to a common interrupt input. DATA POLLING: The AT28C16-T also provides DATA polling to signal the completion of a write cycle. During a write cycle, an attempted read of the the data being written results in the complement of that data for I/O 7 (the other outputs are indeterminate). When the write cycle is fin- ished, true data appears on all ouputs. WRITE PROTECTION: Inadvertent writes to the device are protected against in the following ways: (a) V CC sense— if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power on delay— once V CC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a byte write; (c) Write Inhibit— holding any one of OE low, CE high or WE high inhibits byte write cycles. CHIP CLEAR: The contents of the entire memory of the AT28C16-T may be set to the high state by the Chip Clear operation. By setting CE low and OE to 12V, the chip is cleared when a 10ms low pulse is applied to WE. DEVICE IDENTIFICATION: An extra 32-bytes of E2PROM memory are available to the user for device identifcation. By raising A9 to 12V (± 0.5V) and using ad- dress locations 7E0H to 7FFH the additional bytes may be written to or read from in the same manner as the regular memory array. AT28C16-T 2-177

Temperature (Case) Com. 0°C - 70°C Ind. -40°C - 85°C VCC Power Supply 5V ± 10% DC and AC Operating Range Mode CE OE WE I/O Read V IL VIL VIH D OUT Write (2) VIL VIH VIL D IN Standby/Write Inhibit V IH X (1) X High Z Write Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH X High Z Chip Erase V IL VH (3) VIL High Z 2. Refer to AC Programming Waveforms. Operating Modes Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC + 1V 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1.0V 100 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1.0V Com. 2 mA Ind. 3 mA ICC VCC Active Current f = 5 MHz; I OUT = 0 mA Com. 30 mA Ind. 45 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA .4 V VOH Output High Voltage I OH = -400 µA 2.4 V DC Characteristics 2-178 AT28C16-T

tC (R) t RC Read Cycle Time 150 ns tA (A) t ACC Address Access Time 150 ns tA (CE) t CE (1) CE Access Time 150 ns tA (OE) t OE (2) OE Access Time 0 75 ns tEN (CE) t Lz (4) Output Enable Time From CE 0 ns tEN (OE) t OLZ (4) Output Enable Time From OE 0 ns tV (A) t OH Output Hold Time 0 ns tDIS (CE) t DF (3, 4) Output Disable Time From CE 0 50 ns tDIS (OE) t DF (3, 4) Output Disable Time From OE 0 50 ns AC Read Characteristics Notes: 1.CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2.OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AC Read Waveforms (1, 2, 3, 4) tR , tF < 5 ns Input Test Waveforms and Measurement Level Output Test Load Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V Pin Capacitance (f = 1 MHz, T = 25°C) (1) Note: 1. This parameter is characterized and is not 100% tested. AT28C16-T 2-179

Symbol Parameter Min Max Units tSU (A) t AS Address Setup Time 10 ns tSU (OE-WE) t OES Output Disable Time To WE 10 ns tSU (CE-WE) t CS Chip Enable Time To WE 0 ns tW (WE) t WP Write Enable Pulse Width 100 1000 ns tSU (D-WEH) t DS Data Setup To WE High 50 ns tH (A) t AH Address Hold Time From WE 50 ns tH (D) t DH Data Hold Time From WE High 10 ns tH (OE-WE) t OEH Output Enable Hold Time From WE High 10 ns tH (CE-WE) t CH Chip Enable Hold Time From WE High 0 ns tD (B) t DB Delay From WE High To BUSY Asserted 50 ns tC (W) t WC Write Cycle Time 1 ms AC Write Characteristics AC Write Waveforms 2-180 AT28C16-T

Note: 1. Data Polling AC Timing Characteristics are the same as the AC Read Characteristics. Data Polling Waveforms Chip Erase Waveforms tS = tH = 1 µsec (min.) tW = 10 msec (min.) VH = 12.0 ± 0.5V AT28C16-T 2-181

(ns) ICC (mA) Ordering Code Package Operation Range Active Standby 150 30 0.1 AT28C16-15TC 28T Commercial (0°C to 70°C) 45 0.1 AT28C16-15TI 28T Industrial (-40°C to 85°C) Ordering Information (1) Notes: 1. See Valid Part Number table below. 2. The 28C16 200 ns and 250 ns speed selections have been removed from valid selections table and are replaced by the faster 150 ns TAA offering. Package Type 28T 28 Lead, Plastic Thin Small Outline Package (TSOP) The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C16 15 TC, TI Valid Part Numbers 2-182 AT28C16-T