AT27C256R ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 9

Technical content

Features

  • Fast Read Access Time - 45 ns
  • Low Power CMOS Operation 100 µA max. Standby 20 mA max. Active at 5 MHz
  • JEDEC Standard Packages 28-Lead 600-mil PDIP 32-Lead PLCC 28-Lead TSOP and SOIC
  • 5V ± 10% Supply
  • High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity
  • Rapid Programming Algorithm - 100 µs/byte (typical)
  • CMOS and TTL Compatible Inputs and Outputs
  • Integrated Product Identification Code
  • Commercial and Industrial Temperature Ranges Pin Configurations Pin Name Function A0 - A14 Addresses O0 - O7 Outputs CE Chip Enable OE Output Enable NC No Connect PDIP, SOIC Top View Note: PLCC Package Pins 1 and 17 are DON’T CONNECT. PLCC Top View TSOP Top View Type 1 0014G AT27C256R 3-125

The AT27C256R is available in a choice of industry stand- ard JEDEC-approved one time programmable (OTP) plastic DIP, PLCC, SOIC, and TSOP packages. All de- vices feature two-line control ( CE, OE) to give designers the flexibility to prevent bus contention. With 32K byte storage capability, the AT27C256R allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s 27C256R has additional features to ensure high quality and efficient production use. The Rapid Program- ming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper program- ming algorithms and voltages. Description (Continued) Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excur- sions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in de- vice non-conformance. At a minimum, a 0.1 µF high fre- quency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the V CC and Ground terminals. This capacitor should be posi- tioned as close as possible to the point where the power supply is connected to the array. System Considerations 3-126 AT27C256R

(1) VPP Supply Voltage with *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns. Maximum out- put pin voltage is V CC + 0.75V dc which may over- shoot to +7.0V for pulses of less than 20 ns. Absolute Maximum Ratings* Operating Modes Mode \\ Pin CE OE Ai V PP Outputs Read V IL VIL Ai V CC D OUT Output Disable V IL VIH X (1) VCC High Z Standby V IH X (1) X (1) VCC High Z Rapid Program (2) VIL VIH Ai V PP D IN PGM Verify (2) X (1) VIL Ai V PP D OUT Optional PGM Verify (2) VIL VIL Ai V CC D OUT PGM Inhibit (2) VIH VIH X (1) VPP High Z Product Identification (4) VIL VIL A9 = VH (3) A0 = VIH or VIL A1 - A14 = VIL VCC Identification Code Notes: 1. X can be VIL or VIH. 2. Refer to Programming characteristics. 4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identi- fication byte and high (VIH) to select the Device Code byte. AT27C256R 3-127

AC Characteristics for Read Operation AT27C256R Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Units tACC (3) Address to Output Delay CE = OE = VIL 45 55 70 90 120 150 ns tCE (2) CE to Output DelayOE = VIL 45 55 70 90 120 150 ns tOE (2, 3) OE to Output DelayCE = VIL 20 25 30 30 35 40 ns tDF (4, 5) OE or CE High to Output Float, whichever occurred first20 20 25 25 30 35 ns tOH Output Hold from Address, CE or OE, whichever occurred first 777000 n s Notes: 2, 3, 4, 5. - see AC Waveforms for Read Operation. DC and AC Operating Conditions for Read Operation AT27C256R Operating Temp. (Case) VCC Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% DC and Operating Characteristics for Read Operation Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC ±1 µA ILO Output Leakage Current V OUT = 0V to VCC ±5 µA IPP1 (2) VPP (1) Read/Standby Current VPP = VCC 10 µA ISB VCC (1) Standby Current ISB1 (CMOS), CE = VCC ± 0.3V 100 µA ISB2 (TTL), CE = 2.0 to VCC + 0.5V 1m A ICC VCC Active Current f = 5 MHz, IOUT = 0 mA, CE = VIL 20 mA VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -400 µA 2.4 V Notes: 1. VCC must be applied simultaneously or before VPP , and removed simultaneously or after VPP . 2. VPP may be connected directly to VCC , except during program- ming. The supply current would then be the sum of ICC and IPP . 3-128 AT27C256R

Pin Capacitance (f = 1MHz, T = 25°C) (1) Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. AC Waveforms for Read Operation (1) Notes: 1. Timing measurement reference level is 1.5V for -45 and -55 devices. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing measurement refer- ence levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V and VIH = 2.4V. 2.OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE . 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC . 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven.Input Test Waveforms and Measurement Levels tR , tF < 5 ns (10% to 90%) For -45 and -55 devices only: For -70, -90, -12, and -15 devices: Output Test Load Note: C L= 100 pF including jig capacitance, except for the -45 and -55 devices, where C L= 30 pF. tR , tF < 20 ns (10% to 90%) AT27C256R 3-129

(1) Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C256R a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions Limits UnitsMin Max ILI Input Load Current V IN = VIL,VIH ±10 µA VIL Input Low Level -0.6 0.8 V VIH Input High Level 2.0 V CC + 1 V VOL Output Low Volt. I OL = 2.1 mA 0.4 V VOH Output High Volt. I OH = -400 µA2 . 4 V ICC2 VCC Supply Current (Program and Verify) 25 mA IPP2 VPP Current CE = VIL 25 mA VID A9 Product Identification Voltage 11.5 12.5 V 3-130 AT27C256R

AC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Sym- bol Parameter Test Conditions*(1) Limits UnitsMin Max tAS Address Setup Time 2 µs tOES OE Setup Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP OE High to Out- put Float Delay (2) 01 3 0 n s tVPS VPP Setup Time 2 µs tVCS VCC Setup Time 2 µs tPW CE Program Pulse Width (3) 95 105 µs tOE Data Valid from OE (2) 150 ns tPRT VPP Pulse Rise Time During Programming 50 ns *AC Conditions of Test: Notes: 1. V CC must be applied simultaneously or before VPP and removed simultaneously or after VPP . 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven — see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%. Atmel’s 27C256R Integrated Product Identification Code Codes Pins Hex DataA0 O7 O6 O5 O4 O3 O2 O1 O0 M a n u f a c t u r e r000011110 1 E D e v i c e T y p e 1100011008 C Rapid Programming Algorithm A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse without verification. Then a verifica- tion/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 succes- sive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and VCC to 5.0V. All bytes are read again and compared with the origi- nal data to determine if the device passes or fails. AT27C256R 3-131

(continued) tACC (ns) ICC (mA) Ordering Code Package Operation Range Active Standby 45 20 0.1 AT27C256R-45JC 32J Commercial AT27C256R-45PC 28P6 (0 °C to 70°C) AT27C256R-45RC 28R AT27C256R-45TC 28T 20 0.1 AT27C256R-45JI 32J Industrial AT27C256R-45PI 28P6 (-40 °C to 85°C) AT27C256R-45RI 28R AT27C256R-45TI 28T 55 20 0.1 AT27C256R-55JC 32J Commercial AT27C256R-55PC 28P6 (0 °C to 70°C) AT27C256R-55RC 28R AT27C256R-55TC 28T 20 0.1 AT27C256R-55JI 32J Industrial AT27C256R-55PI 28P6 (-40 °C to 85°C) AT27C256R-55RI 28R AT27C256R-55TI 28T 70 20 0.1 AT27C256R-70JC 32J Commercial AT27C256R-70PC 28P6 (0 °C to 70°C) AT27C256R-70RC 28R AT27C256R-70TC 28T 20 0.1 AT27C256R-70JI 32J Industrial AT27C256R-70PI 28P6 (-40 °C to 85°C) AT27C256R-70RI 28R AT27C256R-70TI 28T 90 20 0.1 AT27C256R-90JC 32J Commercial AT27C256R-90PC 28P6 (0 °C to 70°C) AT27C256R-90RC 28R AT27C256R-90TC 28T 20 0.1 AT27C256R-90JI 32J Industrial AT27C256R-90PI 28P6 (-40 °C to 85°C) AT27C256R-90RI 28R AT27C256R-90TI 28T 120 20 0.1 AT27C256R-12JC 32J Commercial AT27C256R-12PC 28P6 (0 °C to 70°C) AT27C256R-12RC 28R AT27C256R-12TC 28T 20 0.1 AT27C256R-12JI 32J Industrial AT27C256R-12PI 28P6 (-40 °C to 85°C) AT27C256R-12RI 28R AT27C256R-12TI 28T

Ordering Information

32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28R 28 Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Plastic Thin Small Outline Package (TSOP) tACC (ns) ICC (mA) Ordering Code Package Operation Range Active Standby 150 20 0.1 AT27C256R-15JC 32J Commercial AT27C256R-15PC 28P6 (0 °C to 70°C) AT27C256R-15RC 28R AT27C256R-15TC 28T 20 0.1 AT27C256R-15JI 32J Industrial AT27C256R-15PI 28P6 (-40 °C to 85°C) AT27C256R-15RI 28R AT27C256R-15TI 28T Ordering Information (Continued) AT27C256R 3-133