AT27C2048_07 ATMEL

Document overview

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Technical content

Features

  • Fast Read Access Time – 55 ns  Low Power CMOS Operation – 100 µA Maximum Standby – 35 mA Maximum Active at 5 MHz  JEDEC Standard Packages – 40-lead PDIP – 44-lead PLCC – 40-lead VSOP  Direct Upgrade from 512-Kbit and 1-Mbit (AT27C516 and AT27C1024) EPROMs  5V ± 10% Power Supply  High Reliability CMOS Technology – 2,000V ESD Protection – 200 mA Latchup Immunity  Rapid Programming Algorithm – 50 µs/Word (Typical)  CMOS and TTL Compatible Inputs and Outputs  Integrated Product Identification Code  Industrial Temperature Range 1. Description The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time program- mable read-only memory (OTP EPROM) orga nized 128K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16 organization makes this part ideal for high-performance 16 and 32 bit microprocessor systems. In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply cur- rent is typically less than 10 µA. The AT27C2048 is available in industry-standard JEDEC-approved one-time pro- grammable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. With high density 128K word storage capability, the AT27C2048 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s AT27C2048 has additional features that ensure high quality and efficient pro- duction use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. 2-Megabit (128K x 16) OTP EPROM AT27C2048 0632F–EPROM–12/07

0632F–EPROM–12/07 AT27C2048 2. Pin Configurations Note: Both GND pins must be connected. 2.1 40-lead PDIP Top View Pin Name Function A0 - A16 Addresses O0 - O15 Outputs CE Chip Enable OE Output Enable PGM Program Strobe NC No Connect DC Don’t Connect VPP CE O15 O14 O13 O12 O11 O10 GND OE VCC PGM A16 A15 A14 A13 A12 A11 A10 GND 2.2 40-lead VSOP (T ype 1) Top View 2.3 44-lead PLCC Top View Note: Note: PLCC package pins 1 and 23 are Don’t Connect. A10 A11 A12 A13 A14 A15 A16 PGM VCC VPP CE O15 O14 O13 O12 O11 O10 GND OE GND O12 O11 O10 GND NC A13 A12 A11 A10 GND NC OE DC O13 O14 O15 CE VPP DC VCC PGM A16 A15 A14

0632F–EPROM–12/07 AT27C2048 3. System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by th e system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Addi tionally, to stabilize the supply vo ltage level on prin ted circuit boards with large EPROM arrays, a 4.7 µF bulk electr olytic capacitor shoul d be utilized, again con- nected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. Block Diagram Note: 1. Maximum voltage is -0.6V DC which may undershoot to -2 .0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. 5. Absolute Maximum Ratings* Voltage on Any Pin with Voltage on A9 with VPP Supply Voltage with *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. GND VPP VCC DATA OUTPUTS O0 - O15 OE, CE AND PROGRAM LOGIC Y DECODER X DECODER OUTPUT BUFFERS Y -GATING CELL MATRIX IDENTIFICATION A0 - A17 ADDRESS INPUTS OE CE

0632F–EPROM–12/07 AT27C2048 Notes: 1. X can be V IL or VIH. 2. Refer to the Programming characteristics. 3. V H = 12.0 ± 0.5V. 4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word. 5. Standby V CC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB. Notes: 1. V CC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. V PP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP. 6. Operating Modes Mode/Pin CE OE PGM Ai V PP Outputs Read V IL VIL X(1) Ai X (1) DOUT Output Disable X V IH X X X High Z Standby V IH XX X X (5) High Z Rapid Program(2) VIL VIH VIL Ai V PP DIN PGM Verify V IL VIL VIH Ai V PP DOUT PGM Inhibit V IH XX X V PP High Z Product Identification(4) VIL VIL X A9 = VH (3) A0 = VIH or VIL A1 - A16 = VIL VCC Identification Code 7. DC and AC Operating Cond itions for Read Operation AT27C2048 -55 -90 Industrial Operating Temperature (Case) -40 ° C - 85° C- 4 0 ° C - 85° C VCC Power Supply 5V ± 10% 5V ± 10% 8. DC and Operating Characteristics for Read Operation Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC ± 1µ A ILO Output Leakage Current V OUT = 0V to VCC ± 5µ A IPP1 (2) VPP (1) Read/Standby Current V PP = VCC 10 µA ISB VCC (1) Standby Current ISB1 (CMOS) CE = VCC ± 0.3V 100 µA ISB2 (TTL) CE = 2.0 to VCC + 0.5V 1m A ICC VCC Active Current f = 5 MHz, I OUT = 0 mA, CE = VIL 35 mA VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -400 µA 2.4 V

0632F–EPROM–12/07 AT27C2048 Note: 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram. 10. AC Waveforms for Read Operation(1) 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as t he point when data is no longer driven. 9. AC Characteristics for Read Operation Symbol Parameter Condition AT27C2048 Units -55 -90 Min Max Min Max tACC (3) Address to Output Delay CE = OE = VIL 55 90 ns tCE (2) CE to Output Delay OE = VIL 55 90 ns tOE (2)(3) OE to Output Delay CE = VIL 20 35 ns tDF (4)(5) OE or CE High to Output Float, Whichever Occurred First 20 20 ns tOH (4) Output Hold from Address, CE or OE, Whichever Occurred First 70 n s

0632F–EPROM–12/07 AT27C2048 11. Input Test Waveforms and Measurement Levels For -55 devices only: tR, tF < 5 ns (10% to 90%) For -90 devices: tR, tF < 20 ns (10% to 90%) 12. Output Test Load Note: CL = 100 pF including jig capacitance, except for the -55 devices, where CL = 30 pF . 13. Pin Capacitance Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Symbol Typ Max Units Conditions CIN 41 0 p F V IN = 0V COUT 81 2 p F V OUT = 0V

0632F–EPROM–12/07 AT27C2048 14. Programming Waveforms(1) Notes: 1. The Input Timing Reference is 0.8V for V IL and 2.0V for VIH. 2. t OE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C2048, a 0.1 µF capacitor is required across V PP and ground to suppress spurious voltage transients. 15. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions Limits UnitsMin Max ILI Input Load Current V IN = VIL, VIH ±10 µA VIL Input Low Level -0.6 0.8 V VIH Input High Level 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -400 µA 2.4 V ICC2 VCC Supply Current (Program and Verify) 50 mA IPP2 VPP Supply Current CE = VIL 30 mA VID A9 Product Identification Voltage 11.5 12.5 V

0632F–EPROM–12/07 AT27C2048 Notes: 1. V CC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing diagram. 3. Program Pulse width tolerance is 50 µsec ± 5%. 16. AC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions (1) Limits UnitsMin Max tAS Address Setup Time Input Rise and Fall Times (10% to 90%) 20 ns Input Pulse Levels 0.45V to 2.4V Input Timing Reference Level 0.8V to 2.0V Output Timing Reference Level 0.8V to 2.0V 2µ s tOES OE Setup Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP OE High to Output Float Delay(2) 01 3 0 n s tVPS VPP Setup Time 2 µs tVCS VCC Setup Time 2 µs tPW PGM Program Pulse Width(3) 47.5 52.5 µs tOE Data Valid from OE 150 ns tPRT VPP Pulse Rise Time During Programming 50 ns 17. Atmel’s 27C2048 Intergrated Product Identification Code Codes Pins Hex DataA0 O15-O8 O7 O6 O5 O4 O3 O2 O1 O0 M a n u f a c t u r e r 0 0 00011110 0 0 1 E D e v i c e T y p e 1 0 11110111 0 0 F 7

0632F–EPROM–12/07 AT27C2048 18. Rapid Programming Algorithm A 50 µs CE pulse width is used to program. The address is set to the first location. V CC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verifi- cation after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed. After the word verifies prope rly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and V CC to 5.0V. All words are read again and com- pared with the original data to determine if the device passes or fails.

0632F–EPROM–12/07 AT27C2048 19. Ordering Information Note: 1. The 40-lead VSOP package is not recommended for new designs.

19.1 Standard Package

(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 55 35 0.1 AT27C2048-55JI AT27C2048-55PI AT27C2048-55VI 44J 40P6 40V(1) Industrial (-40° C to 85° C) 90 35 0.1 AT27C2048-90JI AT27C2048-90PI AT27C2048-90VI 44J 40P6 40V (1) Industrial (-40° C to 85° C) Note: Not recommended for new designs. Use Green package option.

19.2 Green Package (Pb/Halide-free)

(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 55 35 0.1 AT27C2048-55JU AT27C2048-55PU 44J 40P6 Industrial (-40° C to 85° C) 90 35 0.1 AT27C2048-90JU AT27C2048-90PU 44J 40P6 Industrial (-40° C to 85° C) Package Type 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 40V 40-lead, Plastic Thin Small Outline Package (VSOP)

0632F–EPROM–12/07 AT27C2048 20. Packaging Information 20.1 44J – PLCC Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 Note 2 E 17.399 – 17.653 E1 16.510 – 16.662 Note 2 D2/E2 14.986 – 16.002 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 D2/E2 B e E1 E D 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B44J 10/04/01

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San Jose, CA 95131 TITLE DRAWING NO. R REV.

0632F–EPROM–12/07 AT27C2048 20.2 40P6 – PDIP San Jose, CA 95131 TITLE DRAWING NO. R REV. 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B40P6 09/28/01 PIN B REF E C L SEATING PLANE A 0º ~ 15º D e eB COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.826 A1 0.381 – – D 52.070 – 52.578 Note 2 E 15.240 – 15.875 E1 13.462 – 13.970 Note 2 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

0632F–EPROM–12/07 AT27C2048 20.3 40V – VSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) B40V 10/18/01 PIN 1 D1 D Pin 1 Identifier be E A A2 SEATING PLANE 0º ~ 8º c L GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-142, Variation CA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 13.80 14.00 14.20 D1 12.30 12.40 12.50 Note 2 E 9.90 10.00 10.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC

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